JPS5946416B2 - How to form electrode leads - Google Patents
How to form electrode leadsInfo
- Publication number
- JPS5946416B2 JPS5946416B2 JP12116079A JP12116079A JPS5946416B2 JP S5946416 B2 JPS5946416 B2 JP S5946416B2 JP 12116079 A JP12116079 A JP 12116079A JP 12116079 A JP12116079 A JP 12116079A JP S5946416 B2 JPS5946416 B2 JP S5946416B2
- Authority
- JP
- Japan
- Prior art keywords
- protrusion
- lead
- eutectic
- temperature
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Description
【発明の詳細な説明】
近年、ＬＳＩの機能増大にしたがい、ＬＳＩの半導体素
子から導出されるリード端子の数も４０〜８０個におよ
び、従来の如く一本づつＡｕ、Ａｌ線によつて接続する
ワイヤボンディング方法では、ボンディングに使用され
る時間が前記電極端子数の増加とともに増大し、ＬＳＩ
のコストを高めるばかりでなく、接続の信頼性も低下さ
せるものであつた。Detailed Description of the Invention In recent years, as the functions of LSIs have increased, the number of lead terminals derived from the semiconductor elements of LSIs has increased to 40 to 80, and it is no longer possible to connect them one by one with Au and Al wires as in the past. In the wire bonding method, the time used for bonding increases as the number of electrode terminals increases.
This not only increased the cost of the connection, but also reduced the reliability of the connection.
この様なワイヤボンディングの欠点を一掃するために、
ギャングボンディング法が開発され、実用化されてきた
。In order to eliminate these drawbacks of wire bonding,
A gang bonding method has been developed and put into practical use.
一般的な方法を第１図で説明する。ポリイミド樹脂フィ
ルム１上に形成されたＣｕリード（厚さ３５μｍ）２に
は０．２〜０．６μｍの厚さにＳｎメッキ層３が形成さ
れている。A general method is explained in FIG. A Cu lead (thickness: 35 μm) 2 formed on a polyimide resin film 1 is provided with a Sn plating layer 3 having a thickness of 0.2 to 0.6 μm.
半導体基板４（４’は５１０２膜）の電極端子上にはＣ
ｒ−Ｃｕ、Ｔｈ−Ｃｕ等の複数層からなら金属膜５（バ
リヤメタルと呼ばれる）が真空蒸着法やスパッター蒸着
法等により形成され、更に前記金属膜５上に電解メッキ
法によりＡｕ突起物６が１０〜２０ｐｍの厚さに形成さ
れる。C on the electrode terminal of the semiconductor substrate 4 (4' is 5102 film)
If it is made of multiple layers of r-Cu, Th-Cu, etc., a metal film 5 (called a barrier metal) is formed by vacuum evaporation, sputter evaporation, etc., and further, Au protrusions 6 are formed on the metal film 5 by electrolytic plating. It is formed to a thickness of 10 to 20 pm.
前記Ａｕ突起物６は半導体素子の電極端子の位置に電極
端子の数だけ形成され、更に前記ポリイミド樹脂フィル
ム上のＣｕリードは前記端子に合致する位置まで延在さ
れるものである。The Au protrusions 6 are formed at the positions of the electrode terminals of the semiconductor element in the same number as the electrode terminals, and further, the Cu leads on the polyimide resin film are extended to positions matching the terminals.
第１図の如く構成されたＡｕ突起物６と、Ｃｕリード２
とは互いに位置合せされＣｕリード２側から４８０℃程
度に加熱した治具で全Ｃｕリード２を一度に押えればＡ
ｕ−Ｓｎの共晶物（約２８０℃で発生）が発生し、前記
治具を取り除けば、Ａｕ突起物６とＣｕリード２とは完
全に接続される事になる。ところがこの様なＡｕ−Ｓｎ
を用いる接続方法は接続の強度や、高い信頼性を期特出
来るものの、第２図に示す問題が発生する。なお、第１
図においてｂ図は、加熱治具５０（例えばパルス的にボ
ンディング時のみ加熱する治具もしくは、ヒーターを内
蔵し、常時加熱されている治具等がある。Au protrusions 6 and Cu leads 2 configured as shown in FIG.
If all Cu leads 2 are aligned with each other and pressed at once with a jig heated to about 480°C from the Cu lead 2 side, A
A u-Sn eutectic (generated at about 280° C.) is generated, and when the jig is removed, the Au protrusion 6 and the Cu lead 2 are completely connected. However, such Au-Sn
Although the connection method using the above method can ensure high connection strength and reliability, the problem shown in FIG. 2 occurs. In addition, the first
In the figure, figure b shows a heating jig 50 (for example, a jig that heats only during bonding in a pulsed manner, or a jig that has a built-in heater and is constantly heated).
）が降下してきて、Ｃｕリード２とＡｕ突記物６を加圧
し、前記Ｃｕリード２とＡｕ突起物６とを圧接した状態
である。次いで前記加熱治具５０にパルス電流５１を流
すと、前記加熱治具５０は所定の温度までに瞬時に達す
る。この時、前記加熱治具５０の温度度はＣｕリード２
から、熱伝導率の良いＡｕ突起物６を介して半導体基板
４の方へ逃げる事になる（矢印５２）。このためにＡｕ
突起物６と接しているＣｕリード２の部分５３の温度は
前記加熱治具５０で発生した温度よりも低くなるが、Ａ
ｕ突起物６と接していないＣｕリード２の部分５４，５
１の温度はほぼ前記加熱治具５０の温度と等しくなる。
すなわち、Ｃｕリードの部分５３と５４，５４′との間
に温度差が発生する。この状態が瞬時（約５００ｍｓ以
内）に発生するためにＡｕ−Ｓｎの共晶物はＡｕ突起物
６の端５５，５５′で発生し、次いでＡｕ突起物６の上
５３でこの部分の温度がＡｕ−Ｓｎの共晶温度（２８０
℃）に達した後発生する。ところがＡｕ突起物６上に発
生した共晶物５６は第１図Ｃの如くＡｕ突起物６上のみ
に存在するが、瞬時に大量に出来たＡｕ突起物６の端５
５，５５′の共晶物は第２図Ａ，ｂに示した如く半導体
基板４上に流れ落ちる。これが共晶物により発生する（
第２図Ａ，ｂで説明する）クラツクの原因である。した
がつてＣｕリード２上のＳｎ層がＡｕ突起物６よりはみ
だしていることがクラツクを発生させる原因である。こ
れに対し、Ａｕ突起物６の端６の端５５，５５１で発生
する共晶物の発生量を極力押えるためにＳｎメツキの厚
さを調整することが容易に考えられる。一般に共晶物の
発生量はＳｎメツキ厚さが厚く、加熱治具５０の温度が
高い程発生しやすい。) descends and pressurizes the Cu lead 2 and the Au protrusion 6, bringing the Cu lead 2 and the Au protrusion 6 into pressure contact. Next, when a pulse current 51 is passed through the heating jig 50, the heating jig 50 instantly reaches a predetermined temperature. At this time, the temperature of the heating jig 50 is
Therefore, it escapes toward the semiconductor substrate 4 via the Au protrusion 6 having good thermal conductivity (arrow 52). For this purpose, Au
Although the temperature of the portion 53 of the Cu lead 2 in contact with the protrusion 6 is lower than the temperature generated by the heating jig 50,
Portions 54, 5 of the Cu lead 2 that are not in contact with the u protrusion 6
1 is approximately equal to the temperature of the heating jig 50.
That is, a temperature difference occurs between the Cu lead portions 53 and 54, 54'. Since this state occurs instantaneously (within about 500 ms), Au-Sn eutectic is generated at the ends 55, 55' of the Au protrusion 6, and then the temperature of this part increases at the top 53 of the Au protrusion 6. Au-Sn eutectic temperature (280
Occurs after reaching ℃). However, the eutectic 56 generated on the Au protrusion 6 exists only on the Au protrusion 6 as shown in FIG.
The 5,55' eutectic flows down onto the semiconductor substrate 4 as shown in FIGS. 2A and 2B. This is caused by eutectics (
This is the cause of cracks (explained in Fig. 2A and b). Therefore, the fact that the Sn layer on the Cu lead 2 protrudes beyond the Au protrusion 6 is the cause of cracks. On the other hand, it is easy to consider adjusting the thickness of the Sn plating in order to suppress the amount of eutectic generated at the ends 55, 551 of the ends 6 of the Au protrusions 6 as much as possible. In general, the amount of eutectic generated is more likely to occur as the Sn plating thickness increases and the temperature of the heating jig 50 increases.
したがつて、Ｓｎメツキの厚さと、加熱温度の２つを，
制御する事が必要であるが、最も問題となる事は加熱治
具の温度分布の不均一性である。例えば加熱治具５０の
Ｃｕリードを加圧する側の寸法が２．４×４．０７１Ｌ
ｍ（例えば４ＫｂｉｔＲＡＭの寸法）とすれば、この様
な微少面積において、４８００Ｃ．の温度を前記２．４
×６．０ｍ１の全領域において均一にする事は著しく困
難である。加熱治具の端部においては放熱が激しく急激
な温度勾配を示す。第１図ｄは２．４×６．０１１のパ
ルスツールでの実測値を示したものである。最初のＡｕ
−Ｓｎ共晶を発生一させるボンデイング条件が４８０℃
であつたとすれば中央附近では良いが周辺附近では余り
にも温度差がありすぎる。周辺附近の温度４１５℃を４
８０℃にするためには少なくとも、中央附近の温度を５
５０〜５６０℃に高くしなければならない。この場合、
−加熱治具の中央附近にあるＡｕ突起物上では共晶物の
発生量が著しく大きくなり、過剰の共晶物は半導体基板
４へ流れ落ちクラツ久の発生をまねくものである。又、
第１図ｄの如くの温度分布の場合、Ｓｎメツキ厚を厚く
して、低い温度でも共晶を作らせる事が出来るが、４１
５℃附近では適量の共晶物が出来ても、４８０℃附近で
は、Ｓｎメツキ厚さが厚いから、その分だけ共晶物の量
が多くなつてしまい、結果的に、クラツクの発生をまね
くものである。すなわち、Ｓｎメツキ厚さを調整するに
しても加熱治具の温度分布を度外視する事が出来ないの
で、根本的な解決策とはならない。第２図ａにおいて、
Ａｕ突起物６とＣｕリード２とはＡｕ，Ｓｎの共晶物７
′によつて接続されているが、前記共晶物７′が発生す
る瞬間に余剰に発生した共晶物７は半導体基板４のＳｉ
Ｏ２膜４′上に瞬間的に落下する。Therefore, the thickness of the Sn plating and the heating temperature are
Although it is necessary to control the temperature, the biggest problem is the non-uniformity of the temperature distribution in the heating jig. For example, the dimensions of the heating jig 50 on the side that presses the Cu lead are 2.4 x 4.071L.
m (for example, the size of a 4Kbit RAM), in such a small area, 4800C. The temperature of 2.4
It is extremely difficult to achieve uniformity over the entire area of ×6.0 m1. At the end of the heating jig, heat radiation is intense and a sharp temperature gradient is exhibited. FIG. 1d shows actual measured values using a 2.4×6.011 pulse tool. First Au
-The bonding conditions for generating Sn eutectic are 480℃
If it were, it would be fine near the center, but there would be too much temperature difference near the periphery. The temperature around the surrounding area is 415℃.
In order to reach 80℃, the temperature near the center must be at least 5℃.
The temperature must be increased to 50-560°C. in this case,
- The amount of eutectic material generated on the Au protrusion near the center of the heating jig becomes significantly large, and the excess eutectic material flows down onto the semiconductor substrate 4, leading to the occurrence of cracks. or,
In the case of the temperature distribution as shown in Figure 1 d, it is possible to increase the Sn plating thickness and form a eutectic even at a low temperature.
Even if an appropriate amount of eutectic is produced at around 5°C, at around 480°C, the thickness of the Sn plating is thick, so the amount of eutectic increases accordingly, resulting in the occurrence of cracks. It is something. That is, even if the Sn plating thickness is adjusted, the temperature distribution of the heating jig cannot be ignored, so this is not a fundamental solution. In Figure 2a,
The Au protrusion 6 and the Cu lead 2 are a eutectic material 7 of Au and Sn.
However, at the moment when the eutectic 7' is generated, the excess eutectic 7 is connected to the Si of the semiconductor substrate 4.
It instantly falls onto the O2 film 4'.
この時に前記ＳｉＯ２膜１１半導体基板４あるいはバリ
ヤメタル５との熱膨張の差により瞬時にクラツク８を発
生せしめる。前記クラツク８はＣｕリード２の引張強度
を著しく低下する一方、半導体基板４内に形成されてい
るＰ・Ｎ接合を損傷してしまい、電気的特性の低下をま
ねくものであつた。又、前記Ａｕ突起物６と半導体基板
４の端が比較的接近している様な構成にあつては、第２
図ｂに示す如く共晶物９が、半導体基板４の端まで流れ
出し、半導体基板４と接触（矢印１０で示した）してし
まい、電気的に短絡する問題を発生させていた。本発明
はＡｕ−Ｓｎ共晶によつて接続を行なうギヤングボンデ
イングにおいて、前述した如くの共晶物の余剰物による
半導体基板のクラツクや、共晶物と半導体基板との短絡
を積極的に防止した信頼性の高いリード形成方法を提供
せんとするものである。At this time, cracks 8 are instantaneously generated due to the difference in thermal expansion between the SiO2 film 11 and the semiconductor substrate 4 or barrier metal 5. The cracks 8 significantly reduced the tensile strength of the Cu lead 2, and also damaged the P/N junction formed in the semiconductor substrate 4, leading to a decrease in electrical characteristics. In addition, in a configuration where the Au protrusion 6 and the edge of the semiconductor substrate 4 are relatively close to each other, the second
As shown in FIG. b, the eutectic 9 flows out to the edge of the semiconductor substrate 4 and comes into contact with the semiconductor substrate 4 (indicated by arrow 10), causing an electrical short circuit problem. The present invention actively prevents cracks in the semiconductor substrate due to excess eutectic material and short circuits between the eutectic material and the semiconductor substrate in the gigantic bonding in which connections are made using Au-Sn eutectic material. The present invention aims to provide a highly reliable lead forming method.
第３図で本発明の構成を示す。FIG. 3 shows the configuration of the present invention.
半導体基板１１上の電極端子に相当する位置にＣｒ−Ｃ
ｕ，Ｔｈ−Ｎｉ等のバリヤメタル１２が抵抗加熱法、ス
パツタ一蒸着法によつて形成され、更に１０〜２０μｍ
の厚さにＡｕメツキ法によりＡｕ突起物１３が形成され
る。Cr-C is placed on the semiconductor substrate 11 at a position corresponding to the electrode terminal.
A barrier metal 12 such as u, Th-Ni, etc. is formed by a resistance heating method or a sputtering vapor deposition method, and further has a thickness of 10 to 20 μm.
Au protrusions 13 are formed by Au plating to a thickness of .
一方、ポリイミド樹脂フイルム１４のＣｕリード１５の
先端にはＳｎメツキ１６が施こされている。前記Ｓｎメ
ツキ１６は前記ＣｕｌＪ−ドの先端のみに部分的に形成
されているが、この形成はＣｕリードのエツチングによ
る形成が終了した段階で、再度、感光性樹脂を塗布し、
前記Ｃｕリードの先端のみを露出させたパターンを形成
せしめ、無電解メツキする事により第３図ａの構造を得
る事が出来る。第３図の本発明の実施例において、前記
ＣｕＩＪード１５に設けたＳｎメツキ１６の長さＡは、
Ａｕ突起物１３の長さＢよりも小さい事が本発明の特徴
である。例えば仮にＡｕ突起物１３の長さＢが１００μ
ｍであれば、Ｃｕリード１５に設けたＳｎメツキ１６の
長さＢは８０μｍ程度となる。On the other hand, Sn plating 16 is applied to the tip of the Cu lead 15 of the polyimide resin film 14. The Sn plating 16 is partially formed only on the tip of the CulJ-de, but this formation is done by applying photosensitive resin again after the etching of the Cu lead is completed.
The structure shown in FIG. 3a can be obtained by forming a pattern in which only the tips of the Cu leads are exposed and performing electroless plating. In the embodiment of the present invention shown in FIG. 3, the length A of the Sn plating 16 provided on the CuIJ board 15 is as follows:
A feature of the present invention is that the length of the Au protrusion 13 is smaller than the length B. For example, if the length B of the Au protrusion 13 is 100μ
m, the length B of the Sn plating 16 provided on the Cu lead 15 is about 80 μm.
前記Ａ（！：：Ｂの関係は単に長さ方向だけでなく幅に
関しても同様の事が必要である。第３図ａは断面図を示
すものであるが、平面図を第４図に示した。The relationship A(!::B) needs to be the same not only in the length direction but also in the width direction. Fig. 3a shows a cross-sectional view, and Fig. 4 shows a plan view. Ta.
前記ＣｕｌＪ−ド１５に設けたＳｎメツキ１６の領域と
Ａｕ突起物１３との位置合せにおいては、第４図に示す
如く、Ｓｎメツキ１６の領域が、Ａｕ突起物１３の領域
内に入る様に行なうものである。第４図もしくは第３図
ａの状態で加熱した治具、で加圧すればＡｕ−Ｓｎの共
晶物１７が発生し、第３図ｂの如くの接続を得る事が出
来る。In aligning the area of the Sn plating 16 provided on the CulJ-do 15 and the Au protrusion 13, as shown in FIG. It is something to do. If pressure is applied using a heated jig in the state shown in FIG. 4 or FIG. 3a, Au-Sn eutectic 17 is generated, and a connection as shown in FIG. 3b can be obtained.
第３図ｂにおいて、発生した共晶物１７は、Ｓｎメツキ
１６の領域がＡｕ突起物１３よりも小さいために余剰物
となつて流れ出したり、流れ落ちる事がない。したがつ
て、従来発生していた、半導体基板のクラツクの発生に
よる電気的特性の低下や、流れ出した共晶物と半導体基
板との接触する事故が発生しない、このために信頼性の
高いリード接続を行なう事が出来るものである。In FIG. 3b, the generated eutectic 17 does not flow out or fall as a surplus because the area of the Sn plating 16 is smaller than the Au protrusion 13. Therefore, the deterioration of electrical characteristics due to cracks in the semiconductor substrate, which occurred in the past, and the accidents where the flowing eutectic material comes into contact with the semiconductor substrate do not occur, resulting in highly reliable lead connections. It is possible to do this.
第１図Ａ，ｂ，ｃは従来例の構成断面図、同図ｄは温度
分布図、第２図Ａ，ｂは従来例のボンデイングによる問
題を示す断面図、第３図Ａ，ｂは本発明の一実施例の構
成断面図、第４図は本発明の一実施例の構成平面図であ
る。
１１・・・・・・半導体基板、１３・・・・・・Ａｕ突
起物、１５・・・・・・Ｃｕリード、１６・・・・・・
Ｓｎメツキ。Figures 1A, b, and c are cross-sectional views of the structure of the conventional example, d of the same figure is a temperature distribution diagram, Figures 2A and b are sectional views showing problems caused by bonding in the conventional example, and Figures 3A and b are of the present invention. FIG. 4 is a cross-sectional view of the structure of an embodiment of the invention, and FIG. 4 is a plan view of the structure of the embodiment of the invention. 11...Semiconductor substrate, 13...Au protrusion, 15...Cu lead, 16...
Sn Metsuki.
Claims (1)
フィルムテープ上に設けたＳｎメッキしたＣｕリードと
をギャングボンディングする方法において、前記Ｃｕリ
ードにメッキされているＳｎ層が一定厚でメッキ領域の
長さが、前記Ａｕ突起物の長さよりも短かくかつ前記Ｓ
ｎ層のメッキ領域の幅が、前記Ａｕ突起物の幅よりも短
かく形成されるとともに、前記Ｃｕリードにメッキされ
ているＳｎ層の領域が前記Ａｕ突起物の領域内において
ギャングボンディングし、前記Ｓｎ層とＡｕ突起物の共
晶物を前記Ａｕ突起物の領域内に形成させることによつ
て電極リードを形成することを特徴とする電極リードの
形成方法。1. In a method of gang-bonding Au protrusions provided on electrode terminals on a semiconductor element and Sn-plated Cu leads provided on a resin film tape, the Sn layer plated on the Cu lead has a constant thickness in the plated area. is shorter than the length of the Au protrusion and the length of the S
The width of the plating region of the n layer is formed to be shorter than the width of the Au protrusion, and the region of the Sn layer plated on the Cu lead is gang-bonded within the region of the Au protrusion. A method for forming an electrode lead, comprising forming an electrode lead by forming a eutectic of a Sn layer and an Au protrusion in a region of the Au protrusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12116079A JPS5946416B2 (en) | 1979-09-19 | 1979-09-19 | How to form electrode leads |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12116079A JPS5946416B2 (en) | 1979-09-19 | 1979-09-19 | How to form electrode leads |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5645044A JPS5645044A (en) | 1981-04-24 |
| JPS5946416B2 true JPS5946416B2 (en) | 1984-11-12 |
Family
ID=14804325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12116079A Expired JPS5946416B2 (en) | 1979-09-19 | 1979-09-19 | How to form electrode leads |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5946416B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0756771B2 (en) * | 1988-06-27 | 1995-06-14 | 松下電工株式会社 | Remote control relay |
| CN107978582A (en) * | 2016-10-25 | 2018-05-01 | 矽创电子股份有限公司 | Chip-packaging structure and relevant pins joint method |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS596570A (en) * | 1982-07-02 | 1984-01-13 | Toshiba Corp | Semiconductor device |
| JP4104889B2 (en) * | 2002-03-29 | 2008-06-18 | 株式会社東芝 | Optical semiconductor device |
-
1979
- 1979-09-19 JP JP12116079A patent/JPS5946416B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0756771B2 (en) * | 1988-06-27 | 1995-06-14 | 松下電工株式会社 | Remote control relay |
| CN107978582A (en) * | 2016-10-25 | 2018-05-01 | 矽创电子股份有限公司 | Chip-packaging structure and relevant pins joint method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5645044A (en) | 1981-04-24 |
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