JP4104889B2 - Optical semiconductor device - Google Patents
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- JP4104889B2 JP4104889B2 JP2002094148A JP2002094148A JP4104889B2 JP 4104889 B2 JP4104889 B2 JP 4104889B2 JP 2002094148 A JP2002094148 A JP 2002094148A JP 2002094148 A JP2002094148 A JP 2002094148A JP 4104889 B2 JP4104889 B2 JP 4104889B2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1705—Shape
- H01L2224/17051—Bump connectors having different shapes
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Semiconductor Lasers (AREA)
- Light Receiving Elements (AREA)
- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
Description
【０００１】
【発明の属する技術の分野】
本発明は発光素子または受光素子から構成される光半導体素子を配線基板に搭載する光半導体装置に係り、特に前記光半導体素子を電気配線層と光配線層を有する前記配線基板上にフリップチップ実装する光半導体装置に関する。
【０００２】
【従来の技術】
近年、長距離・大容量の光ファイバー伝送システムは急速に普及して、現在では、ギガビットからテラビットの光伝送技術の研究開発が多く行われている。特に、ＦＴＴＨ（Ｆｉｂｅｒ Ｔｏ Ｔｈｅ Ｈｏｍｅ）における、センター局から一般家庭まで光ファイバーを用いて情報を伝送する光加入者系システムに関しては多くの研究が行われている。具体的には、この光加入者系システム用の光デバイスモジュールを汎用化させるために、製造コストを低減させることが求められており、その製造コストを低減するための手段として、例えば、特開平１１−２７４４４６号公報に記載されるシリコンプラットホーム基板にＶ溝形成して光ファイバーとの位置合わせを容易化する方法などのパッシブアライメント法を用いた光デバイスと光ファイバーの結合技術の提案が多く行われている。
一方、シリコンＬＳＩにおいても高集積化のための研究開発は多く行われており、その動作速度と集積規模は著しく向上される方向にある。この性能向上を行う上での課題が信号配線における転送速度および信号配線の実装密度である。すなわち、トランジスタなどの機能素子の性能向上が行われても、信号配線における信号転送速度と信号配線の高密度化が行わなければ、これらが律速となり、モジュール性能向上の実現は困難である。また、一般に電気信号配線には信号伝達のための遅延が存在するため、これも上記の性能向上を阻害する要因となっている。さらに、信号転送速度の高速化と信号配線の高密度化を行った場合にはＥＭＩ（Ｅｌｅｃｔｒｏｍａｇｎｅｔｉｃ Ｉｎｔｅｒｆｅｒｅｎｃｅ）の影響が顕著になるため、その対策を十分に講じる必要もある。
【０００３】
このような電気信号配線における問題を解決するものとして、例えば、電子情報通信学会論文誌Ｖｏｌ．Ｊ８４−Ｃ，Ｎｏ．９，ｐｐ７３６−７４３，２０００に公開される光インターコネクション技術が最近の技術として有力になっている。現在、この光インターコネクション技術は、電子機器間、電子機器内ボード間、あるいはボード内チップ間など、多くの用途に適用可能と考えられており、例えば、電子機器間の光インターコネクションとして、コア径が大きく接続の容易なプラスティック光ファイバーを用いた光リンクの利用、電子機器内の光インターコネクションとしては、フレキシブルな光導波路を使用した光リンクの利用、ボード内チップ間の光インターコネクションとして、光導波路またはフリースペースによる光配線などの利用が提案されている。したがって、上記に記載したＦＴＴＨにおける光加入者系システムも広義において光インターコネクション技術の１つとすることができる。
【０００４】
光インターコネクションの具体例として、電子情報通信学会論文誌Ｖｏｌ．Ｊ８４−Ｃ，Ｎｏ．９，ｐｐ７９３−７９９には、ボード内チップ間接続としての光バンプインターフェイスが公開されている。この技術は、発光素子と受光素子を搭載した光パッケージと電子機器ボード間の光インターフェイスとして、両者にマイクロレンズを形成して、その空間をコリメート光で接続するもので、ＳＭＴ（Ｓｕｒｆａｃｅ Ｍｏｕｎｔ ｔｅｃｈｎｏｌｏｇｙ）の搭載位置ずれを許容できる大きなビーム径で接続するものである。この技術によれば、これまで高い精度が必要となっていた光デバイスと光ファイバー間のアライメントを容易に緩和できるだけでなく、ボード上での光ファイバー収納、コネクタ接続作業も不要になるため、結果として低コストで光インターコネクションモジュールを実現できる特徴を有している。
【０００５】
【発明が解決しようとする課題】
以上のように、高密度・高速通信技術の次世代技術として有効な光インターコネクション技術では、光を発生するレーザダイオードのような発光素子、光を受信するフォトダイオードなどの受光素子が必要とされるが、このような発光素子または受光素子（受発光素子）のうち、光の発信方向または受信方向が基板に対して垂直な方向の面型受発光素子は、各素子を２次元的に集積できることから、特に、前記光インターコネクション技術に適応される光素子として有効であり、その光ファイバーとの結合方法を考慮した受発光素子の実装方法には多くの提案が行われている。
例えば、特開２０００−２７７８４４号公報の従来の技術には、面発光レーザの一般的な実装方法が記載されている。具体的には，ＬＥＤ（発光ダイオード）の実装に用いられる汎用の台座に搭載する方法が記載されている。この方法によれば、この面発光レーザは不活性ガス雰囲気中に搭載されているため、表面の酸化によって素子劣化が発生せず、かつ面発光レーザの光が基板と垂直方向に出射することから、上面に光を出す電気光変換素子を小型に簡便に作製することができるものである。さらに、特開２０００−２８４１５１号公報には，面発光レーザ素子を２次元アレイ状に配列した面発光レーザアレイに対して、金属プレートに搭載したフェルールを用いて光ファイバーとの接続を実現するモジュール構造が公開されている。
【０００６】
また、受光素子の実装方法に関しては、例えば、特開平５−３７００４号公報と特開平５−１２９６３８号公報に、光ファイバーと良好な光結合が容易なフリップチップ型の受光素子の実装構造が公開されている。この方法は、半導体基板の表面に形成され、裏面側から入射した光を受光して電流に変換する受光部と、半導体基板の裏面側の受光部に対応する部分に受光部に光を導く光ファイバーの先端部を収納するように形成されている凹部を備えることを特徴とするもので、光結合すべき光ファイバーを単に凹部に挿入するだけで、その端面から出射される光信号を正確に光吸収層に導くことができるものである。
【０００７】
しかしながら、これらの実装方法は、光素子をマイクロオプティック的にブロック状に配列する同軸型のモジュール実装構成であるため、低コスト化を実現する、複数の光素子を同一配線基板上に配列する光ＳＭＴ技術には適していない。具体的には、光ＳＭＴは、例えばシリコンプラットホーム基板上にＬＤ、ＰＤ、導波路、合分波器、光ファイバーなどを配置する構成で、半導体プロセス技術を用いてシリコン基板上に導波路、合分波器、光ファイバー用のＶ溝を一括形成することで、製作コストと実装コストの低減及び実装面積の高密度化を実現するものであるが、上記に記載した受発光素子の実装方法では、光ファイバーが配線基板の空間方向に対して垂直方向に結合されるため、光ＳＭＴ技術の基本的な必須構造である配線基板上の表面実装ができない問題を有している。
【０００８】
上記のような問題を部分的に解決する方法として、上記に記載した電子情報通信学会論文誌Ｖｏｌ．Ｊ８４−Ｃ，Ｎｏ．９ｐｐ７９３−７９９，２０００に公開される光バンプインターフェイス構造が挙げられる。図９に示すように、この方法によれば、はんだボールのセルフアライメント効果を光ファイバーとの光結合に利用しており、さらに、面発光レーザアレイ素子を搭載する光パッケージ構造も光ＳＭＴに適した構造が実現できるが、パッケージ内部の面発光レーザアレイ素子はワイヤーボンディングで接続しているため、面発光レーザアレイ素子としての高密度化には限界があった。なお、図９において、４１は光電気配線基板、４２はポリマー導波路、４３は４５度ミラー、４４は面発光レーザアレイ素子、４５はホトダイオード、４６は送信信号制御ＬＳＩ、４７は受信信号制御ＬＳＩ、４８は制御ＬＳＩ、４９はマイクロレンズアレイ、５０ははんだボールである。
【０００９】
また、上記に記載した面発光レーザアレイでは、図８に示すように、各面発光レーザ素子６４の近傍に形成された電極部に個別に接続される電気信号配線６３を、各素子の間を通して、面発光レーザアレイ素子６２の周囲に配置されるＩ／Ｏ電極６１に接続する必要がある。このＩ／Ｏ電極６１は、ワイヤーボンディング法で配線基板の電極端子と接続されるのが一般的である。ところが、このような構成では、各面発光レーザ素子６４の個別の電極部に接続される電気信号の配線が複雑になり、電気信号配線６３の配線密度が向上するため、高速変調特性の劣化が生じるなどの問題があった。さらに、このように面発光レーザアレイ素子６２のチップ周囲に電気配線のためのＩ／Ｏ電極６１を配置すると、面発光レーザ素子の集積を行っても、Ｉ／Ｏ電極の配置密度が律速となり、結果として面発光レーザアレイ素子を高密度化できない問題があった。
【００１０】
このため、各面発光レーザ素子に接続される電極部にバンプ電極を形成して、面発光レーザアレイ素子をフリップチップ実装する方法が考えられるが、この方法では、フリップチップ実装する面発光レーザアレイ素子と配線基板の熱膨張係数の相違に起因する歪がバンプ電極の破壊を発生させることになり、光インターコネクションモジュールとしての信頼性を確保するには多くの問題があった。この問題は、特に発熱量の大きな面発光レーザ素子などを配線基板上にフリップチップ実装する場合に顕著なものである。したがって、例えば、フリップチップ実装する面発光レーザアレイ素子と配線基板の間に封止樹脂を配置することでバンプ応力歪を緩和することも考えられるが、このように封止樹脂を配置する方法では、封止樹脂が面発光レーザ素子の発光部にまで配置されることから、光受信部に十分な光強度を到達させられない問題も発生していた。
【００１１】
本発明は上記の問題を鑑みてなされたものであり、特に発光素子または受光素子をから構成される面型の光半導体素子を、電気配線層と光配線層を有する配線基板に高い接続信頼性でフリップチップ実装する光半導体装置を実現するものである。
【００１２】
【課題を解決するための手段】
本発明は上記課題を解決するため、少なくとも１つの発光素子または受光素子を有する光半導体素子を、電気絶縁部と電気伝送部からなる電気配線層および光絶縁部と光伝送部からなる光配線層を有する配線基板上に搭載する光半導体装置において、前記光半導体素子上に配置される前記発光素子または受光素子は、前記各素子周囲に配置される第１の電極上に形成され、前記発光素子または前記受光素子で出射された光信号を光伝送する光伝送部を備えた環状電極により、前記配線基板に主面が対向して前記光配線層の前記光伝送部に光学的に接続され、さらに、前記光半導体素子上には、前記発光素子または受光素子と接続される第２の電極が前記各素子に対応して形成されており、前記第２の電極上に、内部に第１の金属とその周囲に第２の金属を配置したバンプ電極が形成されており、前記バンプ電極を構成する前記第１の金属の融点は前記第２の金属の融点よりも高く構成されており、前記光半導体素子と前記配線基板との距離は前記第１の金属の高さとほぼ同一であり、前記光半導体素子は前記バンプ電極により前記配線基板に主面が対向して前記電気配線層の前記電気伝送部に接続されており、前記発光素子または受光素子と前記配線基板とで構成される隙間には樹脂が封止されていることを特徴とするものである。
【００１３】
さらに、前記光半導体素子裏面上には、前記発光素子または受光素子と接続される第３の電極が形成されており、前記第３の電極は前記光半導体素子よりも大きい寸法と熱伝導性を有する導電性材料板が接続されており、前記導電性材料板には、内部に第１の金属とその周囲に第２の金属を配置したバンプ電極が形成されており、前記バンプ電極を構成する前記第１の金属の融点は前記第２の金属の融点よりも高く、前記バンプ電極の高さ寸法は前記光半導体素子の厚み寸法と前記環状電極の高さ寸法との総和以上の寸法を有することを特徴とするものである。
さらに、前記第１の電極上に形成する環状電極と、前記バンプ電極を構成する第２の金属は、Ｐｂ，Ｓｎ，Ａｇ，Ｓｂ，Ｉｎ，Ｂｉから選択される金属またはこれら金属を主成分とする合金であって、前記バンプ電極を構成する第１の金属は、Ａｌ，Ａｕ，Ｗ，Ｃｕ，Ｎｉ，Ｃｒ，Ｐｔ，Ｐｄから選択される金属またはこれら金属を主成分とする合金であることを特徴とするものである。
さらに、前記発光素子は面発光型レーザであって、前記受光素子はフォトダイオードであり、前記発光素子または受光素子と前記配線基板が作る隙間には樹脂が封止されていることを特徴とするものである。
【００１４】
本発明によれば、これまでの技術では実現が困難であったアレイ型の光半導体素子のフリップチップ実装を容易に実現できる。したがって、本発明によれば、光半導体素子の主面の受発光素子配置領域上に光半導体素子と接続する第２電極を形成することができるため、これまでの技術のように、アレイ型の光半導体素子をワイヤーボンディングで接続する場合に必要となっていたチップ周囲でのＩ／Ｏ電極配置に必要な電気信号配線が不要になり、さらにＩ／Ｏ電極で律速となっていた光半導体素子の高集積化も可能になり、結果として光半導体素子の小型化が実現できる。
特に、本発明のように受発光素子部を接続する第１電極上に環状電極をはんだなどを形成して、光半導体素子をフリップチップ実装することにより、受発光素子を近接配置した場合でも、信号伝送を行う光を環状電極内部に完全に閉じ込めることができるため、クロストークなどの問題も解決することができる。
【００１５】
さらに本発明によれば、光半導体素子と接続する第２電極上に、内部に銅などの高融点金属を配置して、その周囲にはんだなどの低融点金属を配置してバンプ電極を構成しているため、第１電極上に形成する環状電極だけでは困難であった、光半導体素子と配線基板の作る隙間寸法を厳密に制御することができる。特に、第１金属周囲に配置した、はんだなどの第２金属により、光半導体素子の配線基板に対するセルフアライメント効果が効率的に向上するため、光半導体素子と配線基板の光導波路などの位置合わせ精度が向上して、受発光素子と光導波路との結合効率も極めて向上させることが可能になる。
【００１６】
また、このバンプ電極は、熱伝導性の高い金属を第１の金属とすることで光半導体素子からの熱を配線基板に効率的に放熱させることもできる。なお、この光半導体素子と配線基板の作る隙間寸法制御構造、および光半導体素子からの放熱構造は、光半導体素子裏面に光半導体素子寸法よりも大きい寸法を有する第３の電極を形成した構造においても同様の作用を発揮する。
【００１７】
さらに、本発明によれば、第１の電極上に形成する環状電極により、光半導体素子と配線基板の作る隙間部分に封止樹脂を配置しても、受発光素子部に封止樹脂が流入することがなくなるため、封止樹脂による光強度劣化などの問題を効果的に解決することができる。この作用は、光半導体素子の熱膨張係数と配線基板の熱膨張係数を考慮した封止樹脂として、石英フィラなどを含有する封止樹脂を容易に用いることができる点で特に効果的である。
【００１８】
【発明の実施の形態】
以下，本発明の実施形態につき、図１、図２、図３、図４、図５、図６、図７に示す本発明の実施例を基に説明する。
図１は本発明に係る光半導体装置にフリップチップ実装される光半導体素子の第１の実施例を示す平面図であり、図２は本発明に係る光半導体装置の第１の実施例を示す第１の部分拡大断面図であり、図３は本発明に係る光半導体装置の第１の実施例を示す部分拡大平面図であり、図４は本発明に係る光半導体装置の第１の実施例を示す第２の部分拡大断面図であり、図５は本発明に係る光半導体装置の第２の実施例を示す第１の部分拡大断面図であり、図６は本発明に係る光半導体装置の第２の実施例を示す第２の部分拡大断面図、図７は本発明の変形例を示す断面図である。
【００１９】
図１から図７において、１は光半導体素子、２は面型発光素子、３は発光部、４はバンプ電極で（第１の金属：９）、５は環状電極、６は第１の電極、７は第２の電極、８は光入力部、１０は第２の金属、１１は光配線層、１２は電気配線層、１３は配線基板、１４は光伝送部、１５は第３の金属である。
【００２０】
以下、本発明に係る半導体装置の実施例の製造方法を図１から図４を用いて説明する。
まず図１において、面型発光素子として基板に対して垂直方向にレーザ光を出射する面発光レーザ素子がアレイ状に配置された面発光レーザアレイ素子を用意する。この面発光レーザ素子は本発明の主旨から一般的なものであり、例えば、特開２０００−２９４８７４号公報、特開２０００−１２４５４５号公報に記載される方法で製造することができるが、本発明では説明のため、例えば、ｎｏｎ−ｄｏｐｅのＧａＡｓからなる活性層（活性領域）をｎ型ＧａＡｌＡｓ，ｐ型ＧａＡｌＡｓからなる２つのクラッド層で挟み、ｎ型ＧａＡｌＡｓ層の外面、ｐ型ＧａＡｌＡｓ層の外面にそれぞれ多層膜からなる反射鏡を設けた構成で、この２つの反射鏡の間でレーザ発振を起こさせることによりクラッド層及び活性層の積層方向にレーザ光を出力する構造の面発光レーザ素子を用いた。したがって、面発光レーザ素子の光が出射される主面には、ｐ型コンタクトのための電極が配置されている。この素子電極は、本発明の趣旨から、凹部となる光出射部を囲む環状電極の形状を有している。さらに、本発明での面発光レーザアレイ素子は、上記の発光素子が、１００μｍピッチで、１ｍｍ×１ｍｍのチップ上に、８×８のレイアウトで配置されている。なお、この発光素子レイアウトと電極材料などは限定されるものではないが、本発明では、説明のため８×８のレイアウトとして、電極材料には、Ａｕ／Ｎｉ／Ｔｉを用いた。なお、レーザアレイ素子は、面発光素子に限るものではない。
【００２１】
さらに、図２に示す配線基板は以下に記載する方法で製造することができる。具体的には、光配線層は、石英ガラス基板上に設けられた厚さ数十ミクロンのＳｉＯ２（酸化ケイ素）で製造することができる。さらに具体的には、この光配線層は、光絶縁部中に光伝送部が直径５０μｍ，ピッチ１５０μｍで形成され、必要に応じて曲部が設けられている。
【００２２】
この光配線層における光絶縁部と光伝送部はＳｉＯ２中に含有される不純物濃度による光の屈折率の相違により分離でき、光伝送部の方が、光絶縁部よりも屈折率が大きくなるようにＳｉＯ２中の不純物濃度を調整してある。これにより、光は光伝送部と光絶縁部の境界で全反射して、光伝送部の中を伝達していくことになっている。
【００２３】
さらに、この光配線層は必要に応じて多層構造になっており、異なる光配線層間の光伝送部は、例えば４５度ミラーなどを有するコンタクトホールで結合され、このコンタクトホールの材料組成は、上記に記載した光伝送部と同一材料で構成されている。この光配線層の表面に露出されるコンタクトホールが光入力部となり、配線基板上に搭載される面発光レーザ素子の光出力部と対向して、第１電極が直径３０μｍで構成されている。この配線基板の光入力部と面発光レーザ素子の光出力部は、図２に示すように、内径３０μｍ、外形５０μｍ、高さ５０μｍ寸法のはんだ（Ｐｂ／Ｓｎ＝３７／６３）から構成される環状電極で接続されている。したがって、面発光レーザ素子から出射された光信号は、直接またははんだ環状電極の内壁に反射され、光入力部であるコンタクトホールに向かい、光伝送部により光伝送される。なお、このはんだ環状電極の中空部を伝送、または内壁で反射する光信号は、光伝送部での光伝送または反射と異なり減衰が大きくなるが、その距離が数十μｍであるため、その伝送特性が問題になることは殆どない。なお、この環状電極の材料組成に関しては、特に限定されるものではないが、基本的には、Ｐｂ，Ｓｎ，Ａｇ，Ｓｂ，Ｉｎ，Ｂｉから選択される金属またはこれら金属を主成分とする合金であることが好ましいため、本発明における実施例では、説明のため，Ｐｂ／Ｓｎ＝６３／３７はんだを用いた。
【００２４】
さらに、配線基板の内部には、第２の電極と接続される電気配線層が電気絶縁層と電気伝送部から構成されている。この第２の電極は、図２に示すように、バンプ電極で面発光レーザ素子の主面に露出させた電流供給電極に接続されている。したがって、面発光レーザ素子の主面に形成したバンプ電極に接続される電極端子は、通常はｎ型コンタクトになっている。なお、この第２電極上に接続されるバンプ電極の寸法は、本発明の趣旨から特に限定されるものではないが、本発明における実施例では、２５μｍφの銅から構成される第１の金属を中心に配置して、その周囲をはんだ（Ｐｂ／Ｓｎ＝６３／３７）から構成される第２の金属で囲んで、全体寸法としては５０μｍ高さと、５０μｍφの寸法を有するバンプ電極を形成した。
【００２５】
なお、この第１の金属材料と第２の金属材料組成に関しても、特に限定されるものではないが、基本的には、第１の金属材料としては、Ａｌ，Ａｕ，Ｗ，Ｃｕ，Ｎｉ，Ｃｒ，Ｐｔ，Ｐｄから選択される金属またはこれらを主成分とする合金であることが好ましく、第２の金属組成としては、Ｐｂ，Ｓｎ，Ａｇ，Ｓｂ，Ｉｎ，Ｂｉから選択される金属またはこれら金属を主成分とする合金であることが好ましいため、本発明における実施例では、説明のため，第１の金属としてＣｕ、第２の金属としてＰｂ／Ｓｎ＝６３／３７はんだを用いた。
【００２６】
図３は、はんだ環状電極とバンプ電極の部分平面図である。なお、本発明の実施例に記載するように、環状電極とバンプ電極のレイアウトとしては、環状電極を４隅とした場合の中心部にバンプ電極を配置する方法が実装密度的には最も有利である。
【００２７】
さらに、これらの第１の電極上と第２の電極上に配置される環状電極とバンプ電極の製造方法についても、本発明の趣旨から特に限定されるものではないが、公知の技術である電気めっき法の中でも厚膜レジストをめっきマスクとした、公知の技術であるパターンめっき法を用いて、配線基板側に形成することが製造プロセス的には有利である。これは、面発光レーザ素子を形成する基板材料が一般的に酸に対して溶解性の高い材料を使用しているのに対して、配線基板の構成材料は酸耐性が一般的に高い材料を任意に選択できるためである。
【００２８】
なお、面発光レーザ素子と配線基板とのフリップチップ実装接続は、例えば以下のような方法を用いることができる。具体的には、公知の技術であるハーフミラーを有して位置合せを行うフリップチップボンダーを用いて、面発光レーザアレイ素子と、環状電極及びバンプ電極の形成された配線基板の位置合せを行う。この位置合せは、面発光レーザアレイ素子に形成された電極端子と、配線基板上に形成された環状電極及びバンプ電極で行うことが製造的には容易である。なお、この面発光レーザアレイ素子は、加熱機構を有するコレットに保持され、３５０℃の窒素雰囲気中で予備加熱されている。
【００２９】
次いで，面発光レーザアレイ素子と、配線基板の環状電極及びバンプ電極が接触された状態で、コレットをさらに下方移動して、圧力３０ｋｇ／ｍｍ２を加え、面発光レーザアレイ素子と配線基板を機械的圧力が加わった状態で接触させる。さらにこの状態で温度を３７０℃まで上昇させて環状電極とバンプ電極を構成するはんだを溶融させ、面発光レーザアレイ素子と配線基板を接続する。
このように面発光レーザアレイ素子と配線基板をはんだ接続することにより、公知の技術であるセルフアライメント効果で、面発光レーザアレイ素子と配線基板は正確な位置合せが実現され、面発光レーザ素子の光出力部と配線基板の光入力部は、概ね±１μｍ〜２μｍの誤差精度で接続することが可能になった。さらに、バンプ電極に配置した第１の金属のスタンドオフ効果で、面発光レーザアレイ素子と配線基板の高さばらつきを、第１の金属高さである，５０μｍ±２μｍ程度まで小さくすることも可能になった。
【００３０】
さらに、図４に示すように、必要に応じて、面発光レーザアレイ素子と配線基板の作る隙間部分に公知技術である、封止樹脂を配置することも可能である。封止する樹脂としては特に限定されるものではないが、例えば、ビスフェノール系エポキシとイミダゾール効果触媒、酸無水物硬化剤と球状の石英フィラを重量比で４５ｗｔ％含有するエポキシ樹脂などを用いることができる。したがって、例えばクレゾールノボラックタイプのエポキシ樹脂（ＥＣＯＮ−１９５ＸＬ；住友化学社製）１００重量部、硬化剤としてのフェノール樹脂５４重量部、充填剤としての熔融シリカ１００重量部、触媒としてのベンジルジメチルアミン０．５重量部、その他添加剤としてカーボンブラック３重量部、シランカップリング剤３重量部を粉砕、混合、溶融したエポキシ樹脂溶融体などを用いることもできる。
【００３１】
図５は、本発明に係る第２の実施例を示す部分断面構成図である。この図において、面発光レーザアレイ素子及び面発光レーザアレイ素子を搭載する配線基板については、第１の実施例で用いたものと、本発明の目的とする範囲において基本的に相違する部分はないが、第２の実施例で用いた面発光レーザアレイ素子は、ｎ型電極がチップ裏面に全体的に配置されている。さらに、第２の実施例に記載する面発光レーザアレイ素子裏面には、第３の電極が配置されており、この第３の電極には、面発光レーザアレイ素子の厚み寸法である３００μｍとはんだ環状電極の厚み寸法である５０μｍの総和である３５０μｍ高さのバンプ電極が形成され、配線基板内部の電気配線層と接続される第２電極と電気的に接続されている。なお、第３の金属の材料組成としては、熱伝導性と導電性を有していれば特に限定されるものではないが、本発明では説明のため、バンプ電極の接続部分のみがレジスト開口され、その表面にＡｕ／Ｎｉ薄膜が被覆された銅板を用いた。
さらに図６に示すように、必要に応じて，面発光レーザアレイ素子及び第３の金属が配線基板と作る隙間部分に第１の実施例の場合と同様に、公知の技術である封止樹脂を配置することも可能である。この封止樹脂の組成に関しても、第１の実施例の場合と同様に、配線基板の熱膨張係数および面発光レーザアレイ素子の熱膨張係数を考慮した値であれば、特に限定されるものではないため、本発明における第２の実施例では、第１の実施例に記載した封止樹脂と同一組成の封止樹脂を用いた。
【００３２】
なお、本発明はその趣旨から、光半導体素子としては，上記に記載する面発光レーザ素子と同様に、公知の技術で製造される面型受光素子を用いることも可能である。したがって、詳細には記載しないが、この場合の受光素子としては、例えば，以下のようなものを用いることが可能である。具体的には、受光素子は、ｎ＋−ＩｎＰ基板上に受光部となるＰＩＮホトダイオードを有しているもので、この受光部はメサ部と周辺部とから構成され、これらは基板側から１．５μｍの厚さで、ｎ＝１０１５ｃｍ−３のｎ−ＩｎＰバッファ層と、１．９μｍの厚さでｎ＝１０１５ｃｍ−３であるｎ−Ｇａ０．４７Ｉｎ０．５３Ａｓの光吸収層と１．０μｍの厚さでｐ＝１０１６ｃｍ−３のＩｎＰ層の積層構造となっているものである。
【００３３】
また、上記実施例では光配線層が１層の例について説明したが、たとえば、図７に示すように多層構造にしても良く、さらに、波長の異なる面発光レーザ素子を複数設けても良い。
【００３４】
次に，以上の様に製造した本発明による光半導体装置の性能を評価したところ以下の結果を得ることができた。
まず、上記に記載した面発光レーザ素子を８×８配置でレイアウトした面発光レーザアレイ素子において、従来までの技術によりチップ周囲にワイヤーボンディングするためのＩ／Ｏ電極を配置した場合の面発光レーザアレイ素子のチップ寸法は，１ｍｍ×１ｍｍであったが、本発明に記載する方法では、Ｉ／Ｏ電極をチップ周囲に配置するための信号配線が不要になり、さらに、チップ寸法もＩ／Ｏ電極により律速されることがなくなり、結果として１ｍｍ×１ｍｍの面発光レーザアレイ素子が実現でき、光半導体素子の小型化が実現できた。
【００３５】
さらに、本発明による構造では、面発光レーザ素子からの光出力部と配線基板上の光入力部との間がはんだ環状電極により完全に覆われているため、従来までの方法では、約−５ｄＢ程度あったクロストークは本発明では確認されなかった。またこ、の光入出力部における光結合損失は約０．２ｄＢ程度であり、光インターコネクション技術として用いるには問題のない値であった。
さらにまた、本発明による構造の放熱特性を評価した結果、面発光レーザアレイ素子と配線基板との熱抵抗は、第１の実施例では約２０Ｗ／℃、第２の実施例では１５Ｗ／℃であり、従来までの技術での熱抵抗が３０Ｗ／℃であったことと比較すると、その放熱特性が極めて向上されていることが確認された。
【００３６】
さらに、本発明による光半導体装置の信頼性評価を行ったところ次のような結果を得た。なお、信頼性試験評価は本発明の第１の実施例に記載した光半導体装置で行った。そして、面発光レーザ素子を光入力部とした６４個の環状電極とそれに対応する６４個のバンプ電極の合計１２８個において、１箇所でも接続がオープンになった場合を不良にして評価した。サンプル数は１０００個を評価して、温度サイクル条件は（−５５℃（３０ｍｉｎ）〜２５℃（５ｍｉｎ）〜１２５℃（３０ｍｉｎ）〜２５℃（５ｍｉｎ））で行った。
評価の結果、封止樹脂を配置しない構造では、１０００サイクルで接続不良が発生して２０００サイクルで接続不良が１００％になった。ところが封止樹脂を配置した構造では、３５００サイクルまで接続不良は発生せず、光半導体素子のフリップチップ実装の接続信頼性が極めて向上することが確認された。
【００３７】
以上の結果から、本発明による光半導体装置は、発光素子または受光素子を有する光半導体素子に対して、配線基板と光結合効率が高く、光半導体素子の小型化が可能なフリップチップ実装構造の光半導体装置を、放熱特性と接続信頼性を確保しながら容易に実現できる、これまでの問題を解決できる有効性の高いものであることが確認された。
なお、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々に変更可能である。例えば、本実施例中では搭載される配線基板は，石英基板に対して記載したが、ポリマー導波路を有するガラスエポキシ基板から構成される構造の配線基板を用いても良く、さらに、光半導体素子に搭載される受発光素子数とその材料構成についても特に限定されるものではない。したがって、当然ながら、光半導体素子として、同一チップ上に発光素子と受光素子が搭載される集積型の光半導体素子を用いても良く、さらに、光半導体素子と配線基板が作る隙間部分に封止する樹脂、配線基板と接続する環状電極数とその環状電極の平面的な断面形状などについても限定されるものではない。
以上説明したように、本発明の実施例によれば、これまでの技術では実現が困難であった接続信頼性の高いアレイ型の光半導体素子のフリップチップ実装を容易に実現できる。さらに、光半導体素子の主面の受発光素子配置領域上に光半導体素子と接続する第２電極を形成することができるため、アレイ型の光半導体素子をワイヤーボンディングで接続する場合に必要となっていたチップ周囲のＩ／Ｏ電極配置に必要な電気信号配線が不要になり、Ｉ／Ｏ電極で律速となっていた光半導体素子の高集積化も可能になることから、結果として光半導体素子の小型化が実現できる。
【００３８】
特に、本発明では、受発光素子部を接続する第１電極上に環状電極をはんだなどを形成して、光半導体素子をフリップチップ実装するため、受発光素子を光半導体チップ上で近接配置した場合でも、信号伝送を行う光を環状電極内部に完全に閉じ込めることができることから、クロストークなどの問題も解決することができる。
【００３９】
さらに本発明の実施例によれば、光半導体素子と接続する第２電極上に、内部に銅などの高融点金属を配置して、その周囲にはんだなどの低融点金属を配置してバンプ電極を構成しているため、第１電極上に形成する環状電極だけでは困難であった、光半導体素子と配線基板の作る隙間寸法を厳密に制御することができる。特に、第１金属周囲に配置した、はんだなどの第２金属により、光半導体素子の配線基板に対するセルフアライメント効果が効率的に向上するため、光半導体素子と配線基板の光導波路などの位置合わせ精度が向上して、受発光素子と光導波路との結合効率も極めて向上させることができる。なお、このバンプ電極は、熱伝導性の高い金属を第１の金属とすることで光半導体素子からの熱を配線基板に効率的に放熱させることもできる。
【００４０】
さらに、本発明の実施例によれば、第１の電極上に形成する環状電極により、光半導体素子と配線基板の作る隙間部分に接続信頼性を向上させる封止樹脂を配置しても、受発光素子部に封止樹脂が流入することがなくなるため、封止樹脂による光強度劣化などの問題を効果的に解決することができる。なお、この効果は、光半導体素子の熱膨張係数と配線基板の熱膨張係数を考慮した封止樹脂として、石英フィラなどを含有する封止樹脂を容易に用いることができる点で特に効果的である。
【００４１】
【発明の効果】
本発明によれば、発光素子または受光素子をから構成される面型の光半導体素子を、電気配線層と光配線層を有する配線基板に高い接続信頼性でフリップチップ実装する光半導体装置を実現することができる。
【図面の簡単な説明】
【図１】 本発明に係る光半導体装置の第１の実施例を示す平面図。
【図２】 本発明に係る光半導体装置の第１の実施例を示す第１の部分拡大断面図。
【図３】 本発明に係る光半導体装置の第１の実施例を示す部分拡大平面図。
【図４】 本発明に係る光半導体装置の第１の実施例を示す第２の部分拡大断面図。
【図５】 本発明に係る光半導体装置の第２の実施例を示す第１の部分拡大断面図。
【図６】 本発明に係る光半導体装置の第２の実施例を示す第２の部分拡大断面図。
【図７】 本発明に係る光半導体装置の変形例を示す断面図。
【図８】 従来の技術を説明するための図
【図９】 従来の技術を説明するための図
【符号の説明】
１ 光半導体素子
２ 面型発光素子
３ 発光部
４ バンプ電極
５ 環状電極
６ 第１の電極
７ 第２の電極
８ 光入力部
９ 第１の金属
１０ 第２の金属
１１ 光配線層
１２ 電気配線層
１３ 配線基板
１４ 光伝送部
１５ 第３の金属
１６ 封止樹脂[0001]
[Field of the Invention]
The present invention relates to an optical semiconductor device in which an optical semiconductor element composed of a light emitting element or a light receiving element is mounted on a wiring board, and in particular, the optical semiconductor element is flip-chip mounted on the wiring board having an electrical wiring layer and an optical wiring layer. The present invention relates to an optical semiconductor device.
[0002]
[Prior art]
In recent years, long-distance and large-capacity optical fiber transmission systems have spread rapidly, and many researches and developments are now being made on gigabit to terabit optical transmission technologies. In particular, many studies have been conducted on an optical subscriber system that transmits information using optical fibers from a center station to a general household in FTTH (Fiber To The Home). Specifically, in order to generalize the optical device module for this optical subscriber system, it is required to reduce the manufacturing cost. Many proposals have been made on a technique for coupling an optical device and an optical fiber using a passive alignment method such as a method of forming a V-groove in a silicon platform substrate described in Japanese Patent Application Laid-Open No. 11-274446 to facilitate alignment with an optical fiber. Yes.
On the other hand, many researches and developments for high integration have also been performed in silicon LSI, and the operation speed and integration scale are remarkably improved. The issues in improving the performance are the transfer speed in the signal wiring and the mounting density of the signal wiring. That is, even if the performance of a functional element such as a transistor is improved, unless the signal transfer speed in the signal wiring and the density of the signal wiring are increased, these are rate limiting, and it is difficult to improve the module performance. In general, since there is a delay for signal transmission in the electrical signal wiring, this is also a factor that hinders the above-described performance improvement. Further, when the signal transfer speed is increased and the signal wiring density is increased, the influence of EMI (Electromagnetic Interference) becomes remarkable, and it is necessary to take sufficient countermeasures.
[0003]
As a solution to such problems in electrical signal wiring, see, for example, IEICE Transactions Vol. J84-C, No. 9, optical interconnection technology disclosed in pp 733-743, 2000 has become a promising recent technology. At present, this optical interconnection technology is considered applicable to many applications such as between electronic devices, between boards in electronic devices, or between chips in boards. For example, as an optical interconnection between electronic devices, Use of optical links using plastic optical fibers with large diameter and easy connection, optical interconnections in electronic equipment, use of optical links using flexible optical waveguides, optical interconnection between chips on board, optical The use of optical wiring by a waveguide or free space has been proposed. Therefore, the optical subscriber system in FTTH described above can be one of optical interconnection technologies in a broad sense.
[0004]
As a specific example of optical interconnection, the IEICE Transactions Vol. J84-C, No. 9, pp 793-799 discloses an optical bump interface as an inter-chip connection between boards. In this technology, a microlens is formed as an optical interface between an optical package mounted with a light emitting element and a light receiving element and an electronic device board, and the space is connected with collimated light. SMT (Surface Mount technology) The connection is made with a large beam diameter that can tolerate the mounting position deviation. According to this technology, not only the alignment between optical devices and optical fibers, which has been required to be highly accurate, can be easily relaxed, but also the optical fiber storage and connector connection work on the board is not required, resulting in a low result. The optical interconnection module can be realized at a low cost.
[0005]
[Problems to be solved by the invention]
As described above, optical interconnection technology that is effective as the next generation technology for high-density and high-speed communication technology requires light-emitting elements such as laser diodes that generate light and light-receiving elements such as photodiodes that receive light. However, among such light emitting elements or light receiving elements (light emitting / receiving elements), a surface type light emitting / receiving element whose light transmitting direction or receiving direction is perpendicular to the substrate is two-dimensionally integrated. Since it is possible, it is particularly effective as an optical element adapted to the optical interconnection technology, and many proposals have been made for a method of mounting a light receiving and emitting element in consideration of the coupling method with the optical fiber.
For example, the conventional technique disclosed in Japanese Patent Laid-Open No. 2000-277844 describes a general method for mounting a surface emitting laser. Specifically, a method for mounting on a general-purpose pedestal used for mounting LEDs (light emitting diodes) is described. According to this method, since the surface emitting laser is mounted in an inert gas atmosphere, no element deterioration occurs due to surface oxidation, and the surface emitting laser light is emitted in a direction perpendicular to the substrate. The electro-optical conversion element that emits light on the upper surface can be easily produced in a small size. Further, Japanese Patent Laid-Open No. 2000-284151 discloses a module structure that realizes connection with an optical fiber by using a ferrule mounted on a metal plate for a surface emitting laser array in which surface emitting laser elements are arranged in a two-dimensional array. Is published.
[0006]
Regarding the mounting method of the light receiving element, for example, in JP-A-5-37004 and JP-A-5-129638, a mounting structure of a flip chip type light-receiving element that facilitates good optical coupling with an optical fiber is disclosed. ing. In this method, a light receiving portion that is formed on the front surface of the semiconductor substrate and receives light incident from the back surface side and converts it into a current, and an optical fiber that guides the light to the light receiving portion to a portion corresponding to the light receiving portion on the back surface side of the semiconductor substrate The optical fiber to be optically coupled can be accurately absorbed by simply inserting the optical fiber to be optically coupled into the recess. That is what can lead to a layer.
[0007]
However, these mounting methods are coaxial-type module mounting configurations in which optical elements are arranged in a micro-optic block form. Therefore, an optical device in which a plurality of optical elements are arranged on the same wiring board to achieve cost reduction. Not suitable for SMT technology. Specifically, the optical SMT has a configuration in which, for example, an LD, PD, waveguide, multiplexer / demultiplexer, optical fiber, etc. are arranged on a silicon platform substrate. By forming the V-groove for the waver and the optical fiber at once, the manufacturing cost and the mounting cost can be reduced and the mounting area can be increased in density. Are coupled in a direction perpendicular to the spatial direction of the wiring board, and therefore there is a problem that surface mounting on the wiring board, which is a basic essential structure of the optical SMT technology, cannot be performed.
[0008]
As a method of partially solving the above problem, the above-mentioned Journal of Electronic Information Communication Society Vol. J84-C, No. The optical bump interface structure disclosed in 9 pp 793-799, 2000 is mentioned. As shown in FIG. 9, according to this method, the self-alignment effect of the solder balls is used for optical coupling with the optical fiber, and the optical package structure on which the surface emitting laser array element is mounted is also suitable for the optical SMT. Although the structure can be realized, since the surface emitting laser array elements inside the package are connected by wire bonding, there is a limit to increasing the density as the surface emitting laser array element. In FIG. 9, 41 is an opto-electric wiring board, 42 is a polymer waveguide, 43 is a 45-degree mirror, 44 is a surface emitting laser array element, 45 is a photodiode, 46 is a transmission signal control LSI, and 47 is a reception signal control LSI. , 48 is a control LSI, 49 is a microlens array, and 50 is a solder ball.
[0009]
In the surface emitting laser array described above, as shown in FIG. 8, the
[0010]
For this reason, a method of forming a bump electrode in an electrode portion connected to each surface emitting laser element and flip-chip mounting the surface emitting laser array element is conceivable. In this method, a surface emitting laser array to be flip-chip mounted is conceivable. The strain resulting from the difference in the thermal expansion coefficient between the element and the wiring board causes the bump electrode to be broken, and there are many problems in securing the reliability as the optical interconnection module. This problem is particularly noticeable when a surface emitting laser element having a large heat generation amount is flip-chip mounted on a wiring board. Therefore, for example, it may be possible to alleviate the bump stress distortion by arranging a sealing resin between the surface emitting laser array element to be flip-chip mounted and the wiring board. However, in this method of arranging the sealing resin, Further, since the sealing resin is disposed up to the light emitting portion of the surface emitting laser element, there has been a problem that sufficient light intensity cannot reach the light receiving portion.
[0011]
The present invention has been made in view of the above-described problems, and in particular, a surface-type optical semiconductor element composed of a light emitting element or a light receiving element is highly connected to a wiring board having an electric wiring layer and an optical wiring layer. Thus, an optical semiconductor device to be flip-chip mounted is realized.
[0012]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides an optical semiconductor element having at least one light-emitting element or light-receiving element, an electric wiring layer composed of an electric insulating part and an electric transmission part, and an optical wiring layer composed of an optical insulating part and an optical transmission part In the optical semiconductor device mounted on the wiring substrate having the light emitting element, the light emitting element or the light receiving element disposed on the optical semiconductor element is formed on a first electrode disposed around each element, and the light emitting element Alternatively, an annular electrode including an optical transmission unit that optically transmits an optical signal emitted from the light receiving element is optically connected to the optical transmission unit of the optical wiring layer with a main surface facing the wiring substrate, Furthermore, a second electrode connected to the light emitting element or the light receiving element is formed on the optical semiconductor element corresponding to each element, and the first electrode is formed on the second electrode. Metal and surroundings The second metal is arranged the bump electrode is formed, the first metal melting point constituting the bump electrode is higher than the melting point of the second metal Composed , The distance between the optical semiconductor element and the wiring board is substantially the same as the height of the first metal, The optical semiconductor element is connected to the electrical transmission portion of the electrical wiring layer with the bump electrode facing a main surface of the wiring substrate. And , Resin is sealed in a gap formed by the light emitting element or light receiving element and the wiring board. It is characterized by being.
[0013]
Furthermore, a third electrode connected to the light emitting element or the light receiving element is formed on the back surface of the optical semiconductor element, and the third electrode has a size and thermal conductivity larger than those of the optical semiconductor element. A conductive material plate is connected to the conductive material plate, and the conductive material plate includes a bump electrode in which a first metal and a second metal are arranged around the first metal, and constitutes the bump electrode. The melting point of the first metal is higher than the melting point of the second metal, and the height dimension of the bump electrode is equal to or greater than the sum of the thickness dimension of the optical semiconductor element and the height dimension of the annular electrode. It is characterized by this.
Further, the annular electrode formed on the first electrode and the second metal constituting the bump electrode are a metal selected from Pb, Sn, Ag, Sb, In, and Bi, or these metals as a main component. The first metal constituting the bump electrode is a metal selected from Al, Au, W, Cu, Ni, Cr, Pt, and Pd, or an alloy containing these metals as a main component. It is characterized by.
Further, the light emitting element is a surface emitting laser, the light receiving element is a photodiode, and a resin is sealed in a gap formed between the light emitting element or the light receiving element and the wiring board. Is.
[0014]
According to the present invention, it is possible to easily realize flip-chip mounting of an array type optical semiconductor element, which has been difficult to realize with conventional techniques. Therefore, according to the present invention, the second electrode connected to the optical semiconductor element can be formed on the light receiving and emitting element arrangement region on the main surface of the optical semiconductor element. The electric signal wiring required for the I / O electrode arrangement around the chip, which is necessary when connecting the optical semiconductor element by wire bonding, is unnecessary, and the optical semiconductor element has been rate-controlled by the I / O electrode. High integration is also possible, and as a result, downsizing of the optical semiconductor element can be realized.
In particular, even when the light emitting and receiving elements are arranged close to each other by forming the annular electrode on the first electrode connecting the light emitting and receiving element portions as in the present invention, and mounting the optical semiconductor element by flip chip mounting, Since light for signal transmission can be completely confined inside the annular electrode, problems such as crosstalk can be solved.
[0015]
Further, according to the present invention, a bump electrode is formed by disposing a high melting point metal such as copper on the second electrode connected to the optical semiconductor element and disposing a low melting point metal such as solder around the second electrode. Therefore, it is possible to strictly control the gap size formed between the optical semiconductor element and the wiring board, which has been difficult with only the annular electrode formed on the first electrode. In particular, the second metal such as solder disposed around the first metal effectively improves the self-alignment effect of the optical semiconductor element with respect to the wiring substrate. As a result, the coupling efficiency between the light emitting / receiving element and the optical waveguide can be greatly improved.
[0016]
In addition, the bump electrode can also efficiently dissipate heat from the optical semiconductor element to the wiring board by using a metal having high thermal conductivity as the first metal. The gap dimension control structure formed by the optical semiconductor element and the wiring board and the heat dissipation structure from the optical semiconductor element are the structures in which a third electrode having a dimension larger than the optical semiconductor element dimension is formed on the back surface of the optical semiconductor element. Exhibits the same effect.
[0017]
Furthermore, according to the present invention, the annular resin formed on the first electrode causes the sealing resin to flow into the light emitting / receiving element portion even if the sealing resin is disposed in the gap formed by the optical semiconductor element and the wiring board. Therefore, problems such as light intensity deterioration due to the sealing resin can be effectively solved. This action is particularly effective in that a sealing resin containing quartz filler or the like can be easily used as a sealing resin considering the thermal expansion coefficient of the optical semiconductor element and the thermal expansion coefficient of the wiring board.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described based on the embodiments of the present invention shown in FIGS. 1, 2, 3, 4, 5, 6, and 7. FIG.
FIG. 1 is a plan view showing a first embodiment of an optical semiconductor element flip-chip mounted on an optical semiconductor device according to the present invention, and FIG. 2 shows a first embodiment of the optical semiconductor device according to the present invention. FIG. 3 is a first partial enlarged cross-sectional view, FIG. 3 is a partial enlarged plan view showing a first embodiment of the optical semiconductor device according to the present invention, and FIG. 4 is a first embodiment of the optical semiconductor device according to the present invention. FIG. 5 is a second partial enlarged sectional view showing an example, FIG. 5 is a first partial enlarged sectional view showing a second embodiment of the optical semiconductor device according to the present invention, and FIG. 6 is an optical semiconductor according to the present invention. FIG. 7 is a sectional view showing a modified example of the present invention, and FIG. 7 is a second partial enlarged sectional view showing the second embodiment of the apparatus.
[0019]
1 to 7, 1 is an optical semiconductor element, 2 is a surface light emitting element, 3 is a light emitting portion, 4 is a bump electrode (first metal: 9), 5 is an annular electrode, and 6 is a first electrode. 7 is the second electrode, 8 is the optical input unit, 10 is the second metal, 11 is the optical wiring layer, 12 is the electrical wiring layer, 13 is the wiring board, 14 is the optical transmission unit, and 15 is the third metal. It is.
[0020]
A method for manufacturing an embodiment of a semiconductor device according to the present invention will be described below with reference to FIGS.
First, in FIG. 1, a surface emitting laser array element in which surface emitting laser elements emitting laser light in a direction perpendicular to the substrate are arranged in an array as a surface light emitting element is prepared. This surface emitting laser element is general from the gist of the present invention, and can be manufactured, for example, by the method described in Japanese Patent Application Laid-Open Nos. 2000-294874 and 2000-124545. For explanation, for example, an active layer (active region) made of non-dope GaAs is sandwiched between two clad layers made of n-type GaAlAs and p-type GaAlAs, and the outer surface of the n-type GaAlAs layer and the outer surface of the p-type GaAlAs layer. A surface-emitting laser device having a structure in which a reflecting mirror composed of a multilayer film is provided, and a laser beam is generated in the stacking direction of the cladding layer and the active layer by causing laser oscillation between the two reflecting mirrors. Using. Therefore, an electrode for a p-type contact is disposed on the main surface from which light from the surface emitting laser element is emitted. For the purpose of the present invention, this element electrode has a shape of an annular electrode surrounding a light emitting portion that becomes a recess. Further, in the surface emitting laser array element according to the present invention, the above light emitting elements are arranged in an 8 × 8 layout on a 1 mm × 1 mm chip at a pitch of 100 μm. In addition, although this light emitting element layout, electrode material, etc. are not limited, in this invention, Au / Ni / Ti was used for the electrode material as an 8x8 layout for description. The laser array element is not limited to the surface light emitting element.
[0021]
Furthermore, the wiring board shown in FIG. 2 can be manufactured by the method described below. Specifically, the optical wiring layer is a SiO film having a thickness of several tens of microns provided on a quartz glass substrate. 2 (Silicon oxide). More specifically, in this optical wiring layer, an optical transmission portion is formed in an optical insulating portion with a diameter of 50 μm and a pitch of 150 μm, and a curved portion is provided as necessary.
[0022]
The optical insulating part and the optical transmission part in this optical wiring layer are made of SiO. 2 It can be separated by the difference in the refractive index of light depending on the concentration of impurities contained therein, so that the refractive index of the optical transmission part is larger than that of the optical insulating part. 2 The impurity concentration inside is adjusted. As a result, the light is totally reflected at the boundary between the optical transmission unit and the optical insulating unit and is transmitted through the optical transmission unit.
[0023]
Furthermore, this optical wiring layer has a multilayer structure as required, and the optical transmission parts between different optical wiring layers are coupled by, for example, a contact hole having a 45-degree mirror or the like. It is comprised with the same material as the optical transmission part described in (1). The contact hole exposed on the surface of the optical wiring layer serves as a light input portion, and the first electrode is formed with a diameter of 30 μm so as to face the light output portion of the surface emitting laser element mounted on the wiring substrate. As shown in FIG. 2, the light input portion of the wiring board and the light output portion of the surface emitting laser element are composed of solder (Pb / Sn = 37/63) having an inner diameter of 30 μm, an outer diameter of 50 μm, and a height of 50 μm. They are connected by an annular electrode. Therefore, the optical signal emitted from the surface emitting laser element is reflected directly or on the inner wall of the solder annular electrode, and is optically transmitted by the optical transmission unit toward the contact hole as the optical input unit. In addition, the optical signal transmitted through the hollow part of the solder annular electrode or reflected by the inner wall is greatly attenuated unlike the optical transmission or reflection at the optical transmission part, but the distance is several tens of μm. The characteristics rarely become a problem. The material composition of the annular electrode is not particularly limited, but is basically a metal selected from Pb, Sn, Ag, Sb, In, Bi or an alloy containing these metals as a main component. Therefore, in the examples in the present invention, Pb / Sn = 63/37 solder was used for explanation.
[0024]
Furthermore, an electrical wiring layer connected to the second electrode is composed of an electrical insulating layer and an electrical transmission portion inside the wiring board. As shown in FIG. 2, the second electrode is connected to a current supply electrode exposed on the main surface of the surface emitting laser element by a bump electrode. Therefore, the electrode terminal connected to the bump electrode formed on the main surface of the surface emitting laser element is usually an n-type contact. The size of the bump electrode connected to the second electrode is not particularly limited for the purpose of the present invention, but in the embodiment of the present invention, the first metal composed of copper of 25 μmφ is used. A bump electrode having a total dimension of 50 μm and a dimension of 50 μmφ was formed by placing it in the center and surrounding it with a second metal composed of solder (Pb / Sn = 63/37).
[0025]
The first metal material and the second metal material composition are not particularly limited, but basically, as the first metal material, Al, Au, W, Cu, Ni, A metal selected from Cr, Pt, Pd or an alloy containing these as a main component is preferable, and the second metal composition is a metal selected from Pb, Sn, Ag, Sb, In, Bi, or these Since an alloy containing a metal as a main component is preferable, in the examples in the present invention, Cu is used as the first metal and Pb / Sn = 63/37 solder is used as the second metal for the sake of explanation.
[0026]
FIG. 3 is a partial plan view of the solder annular electrode and the bump electrode. As described in the embodiments of the present invention, as the layout of the annular electrode and the bump electrode, the method of arranging the bump electrode at the center when the annular electrode has four corners is most advantageous in terms of mounting density. is there.
[0027]
Further, the manufacturing method of the annular electrode and the bump electrode arranged on the first electrode and the second electrode is not particularly limited from the gist of the present invention. Among the plating methods, it is advantageous in terms of the manufacturing process to form on the wiring substrate side using a pattern plating method which is a known technique using a thick film resist as a plating mask. This is because the substrate material for forming the surface emitting laser element generally uses a material that is highly soluble in acid, whereas the constituent material of the wiring substrate is a material that generally has high acid resistance. This is because it can be arbitrarily selected.
[0028]
For example, the following method can be used for flip chip mounting connection between the surface emitting laser element and the wiring board. Specifically, a surface-emitting laser array element and a wiring substrate on which annular electrodes and bump electrodes are formed are aligned using a flip chip bonder that has a half mirror that is a known technique and performs alignment. . It is easy to manufacture this alignment by using electrode terminals formed on the surface emitting laser array element and annular electrodes and bump electrodes formed on the wiring board. This surface emitting laser array element is held by a collet having a heating mechanism and preheated in a nitrogen atmosphere at 350 ° C.
[0029]
Next, with the surface emitting laser array element, the annular electrode and the bump electrode of the wiring board in contact with each other, the collet is further moved downward, and the pressure is 30 kg / mm. 2 The surface emitting laser array element and the wiring board are brought into contact with each other with mechanical pressure applied. Further, in this state, the temperature is raised to 370 ° C. to melt the solder constituting the annular electrode and the bump electrode, and the surface emitting laser array element and the wiring board are connected.
By soldering the surface emitting laser array element and the wiring board in this manner, the surface emitting laser array element and the wiring board can be accurately aligned by a self-alignment effect that is a well-known technique. The light output portion and the light input portion of the wiring board can be connected with an error accuracy of approximately ± 1 μm to 2 μm. Furthermore, due to the standoff effect of the first metal disposed on the bump electrode, it is possible to reduce the height variation between the surface emitting laser array element and the wiring board to about 50 μm ± 2 μm, which is the first metal height. Became.
[0030]
Furthermore, as shown in FIG. 4, a sealing resin, which is a known technique, can be disposed in a gap portion formed by the surface emitting laser array element and the wiring board as necessary. The resin to be sealed is not particularly limited. For example, an epoxy resin containing 45 wt% of a bisphenol-based epoxy and an imidazole effect catalyst, an acid anhydride curing agent, and a spherical quartz filler may be used. it can. Therefore, for example, 100 parts by weight of a cresol novolac type epoxy resin (ECON-195XL; manufactured by Sumitomo Chemical Co., Ltd.), 54 parts by weight of phenol resin as a curing agent, 100 parts by weight of fused silica as a filler, and benzyldimethylamine 0 as a catalyst It is also possible to use an epoxy resin melt obtained by pulverizing, mixing, and melting 3 parts by weight of carbon black and 3 parts by weight of a silane coupling agent as other additives.
[0031]
FIG. 5 is a partial sectional view showing a second embodiment according to the present invention. In this figure, the surface-emitting laser array element and the wiring board on which the surface-emitting laser array element is mounted are basically not different from those used in the first embodiment within the scope of the present invention. However, in the surface emitting laser array element used in the second embodiment, the n-type electrode is entirely disposed on the back surface of the chip. Further, a third electrode is disposed on the back surface of the surface emitting laser array element described in the second embodiment. The third electrode has a thickness of 300 μm, which is the thickness of the surface emitting laser array element, and a solder. A bump electrode having a height of 350 μm, which is the sum total of the thickness dimension of the annular electrode of 50 μm, is formed, and is electrically connected to the second electrode connected to the electric wiring layer inside the wiring board. The material composition of the third metal is not particularly limited as long as it has thermal conductivity and conductivity. However, in the present invention, for the purpose of explanation, only the connection portion of the bump electrode is opened with a resist. A copper plate having an Au / Ni thin film coated on its surface was used.
Further, as shown in FIG. 6, as necessary, a sealing resin, which is a known technique, is formed in a gap portion formed between the surface emitting laser array element and the third metal and the wiring board as required. Can also be arranged. The composition of the sealing resin is not particularly limited as long as it is a value that takes into consideration the thermal expansion coefficient of the wiring board and the thermal expansion coefficient of the surface emitting laser array element, as in the case of the first embodiment. Therefore, in the second embodiment of the present invention, a sealing resin having the same composition as the sealing resin described in the first embodiment was used.
[0032]
From the spirit of the present invention, a surface light-receiving element manufactured by a known technique can be used as the optical semiconductor element, similarly to the surface-emitting laser element described above. Therefore, although not described in detail, as the light receiving element in this case, for example, the following can be used. Specifically, the light receiving element is n + -Having a PIN photodiode as a light receiving portion on an InP substrate, this light receiving portion is composed of a mesa portion and a peripheral portion, which are 1.5 μm thick from the substrate side, and n = 10 15 cm -3 N-InP buffer layer and n = 10 at a thickness of 1.9 μm 15 cm -3 N-Ga 0.47 In 0.53 P = 10 with As light absorption layer and 1.0 μm thickness 16 cm -3 This is a laminated structure of InP layers.
[0033]
In the above embodiment, an example in which the optical wiring layer is one layer has been described. For example, a multilayer structure may be used as shown in FIG. 7, and a plurality of surface emitting laser elements having different wavelengths may be provided.
[0034]
Next, when the performance of the optical semiconductor device according to the present invention manufactured as described above was evaluated, the following results were obtained.
First, in a surface emitting laser array element in which the surface emitting laser elements described above are laid out in an 8 × 8 arrangement, a surface emitting laser in which an I / O electrode for wire bonding is arranged around the chip by a conventional technique. The chip size of the array element is 1 mm × 1 mm. However, in the method described in the present invention, signal wiring for arranging the I / O electrodes around the chip is not necessary, and the chip size is also I / O. As a result, the surface emitting laser array element of 1 mm × 1 mm can be realized and the optical semiconductor element can be downsized.
[0035]
Furthermore, in the structure according to the present invention, since the space between the light output portion from the surface emitting laser element and the light input portion on the wiring board is completely covered with the solder annular electrode, in the conventional method, about -5 dB. The degree of crosstalk was not confirmed in the present invention. Further, the optical coupling loss in the optical input / output unit is about 0.2 dB, which is a value that is not problematic for use as an optical interconnection technology.
Furthermore, as a result of evaluating the heat dissipation characteristics of the structure according to the present invention, the thermal resistance between the surface emitting laser array element and the wiring board is about 20 W / ° C. in the first embodiment and 15 W / ° C. in the second embodiment. In addition, it was confirmed that the heat dissipation characteristics were extremely improved as compared with the conventional thermal resistance of 30 W / ° C.
[0036]
Furthermore, when the reliability of the optical semiconductor device according to the present invention was evaluated, the following results were obtained. The reliability test evaluation was performed with the optical semiconductor device described in the first embodiment of the present invention. Then, in the case of a total of 128 annular electrodes and 64 bump electrodes corresponding to the surface emitting laser element as the light input portion, the case where the connection was opened even at one place was evaluated as defective. 1000 samples were evaluated, and the temperature cycle conditions were (-55 ° C. (30 min) to 25 ° C. (5 min) to 125 ° C. (30 min) to 25 ° C. (5 min)).
As a result of the evaluation, in the structure in which the sealing resin is not disposed, the connection failure occurs at 1000 cycles and the connection failure becomes 100% at 2000 cycles. However, in the structure in which the sealing resin is disposed, connection failure does not occur until 3500 cycles, and it has been confirmed that the connection reliability of flip chip mounting of the optical semiconductor element is extremely improved.
[0037]
From the above results, the optical semiconductor device according to the present invention has a flip-chip mounting structure that has high optical coupling efficiency with the wiring substrate and can reduce the size of the optical semiconductor element compared to the optical semiconductor element having the light emitting element or the light receiving element. It was confirmed that the optical semiconductor device can be easily realized while ensuring the heat radiation characteristics and the connection reliability, and is highly effective in solving the problems so far.
In addition, this invention is not limited to the said Example, It can change variously in the range which does not deviate from the summary. For example, in the present embodiment, the wiring board to be mounted is described with respect to the quartz substrate. However, a wiring board having a structure composed of a glass epoxy substrate having a polymer waveguide may be used. There are no particular limitations on the number of light emitting / receiving elements mounted on the substrate and the material configuration thereof. Therefore, as a matter of course, an integrated optical semiconductor element in which a light emitting element and a light receiving element are mounted on the same chip may be used as the optical semiconductor element, and further, sealed in a gap portion formed by the optical semiconductor element and the wiring board. The resin to be used, the number of annular electrodes connected to the wiring board, the planar sectional shape of the annular electrodes, and the like are not limited.
As described above, according to the embodiments of the present invention, it is possible to easily realize flip-chip mounting of an array type optical semiconductor element with high connection reliability, which has been difficult to realize with conventional techniques. Further, since the second electrode connected to the optical semiconductor element can be formed on the light receiving / emitting element arrangement region on the main surface of the optical semiconductor element, it is necessary when connecting the array type optical semiconductor element by wire bonding. This eliminates the need for the electrical signal wiring necessary for the I / O electrode arrangement around the chip, and also enables high integration of the optical semiconductor element that has been rate-controlled by the I / O electrode. As a result, the optical semiconductor element Can be miniaturized.
[0038]
In particular, in the present invention, an annular electrode is formed on the first electrode that connects the light emitting / receiving element portion with solder or the like, and the optical semiconductor element is flip-chip mounted. Even in this case, the light for signal transmission can be completely confined in the annular electrode, so that problems such as crosstalk can be solved.
[0039]
Further, according to the embodiment of the present invention, a high melting point metal such as copper is disposed inside the second electrode connected to the optical semiconductor element, and a low melting point metal such as solder is disposed around the bump electrode. Therefore, it is possible to strictly control the gap size formed between the optical semiconductor element and the wiring board, which is difficult with only the annular electrode formed on the first electrode. In particular, the second metal such as solder disposed around the first metal effectively improves the self-alignment effect of the optical semiconductor element with respect to the wiring substrate. As a result, the coupling efficiency between the light emitting / receiving element and the optical waveguide can be greatly improved. In addition, this bump electrode can also efficiently dissipate heat from the optical semiconductor element to the wiring board by using a metal having high thermal conductivity as the first metal.
[0040]
Furthermore, according to the embodiment of the present invention, the annular electrode formed on the first electrode can be received even when the sealing resin for improving the connection reliability is arranged in the gap portion formed between the optical semiconductor element and the wiring board. Since the sealing resin does not flow into the light emitting element portion, problems such as light intensity deterioration due to the sealing resin can be effectively solved. This effect is particularly effective in that a sealing resin containing a quartz filler or the like can be easily used as a sealing resin considering the thermal expansion coefficient of the optical semiconductor element and the thermal expansion coefficient of the wiring board. is there.
[0041]
【The invention's effect】
According to the present invention, an optical semiconductor device in which a planar optical semiconductor element composed of a light emitting element or a light receiving element is flip-chip mounted with high connection reliability on a wiring substrate having an electrical wiring layer and an optical wiring layer is realized. can do.
[Brief description of the drawings]
FIG. 1 is a plan view showing a first embodiment of an optical semiconductor device according to the present invention.
FIG. 2 is a first partial enlarged cross-sectional view showing a first embodiment of an optical semiconductor device according to the invention.
FIG. 3 is a partially enlarged plan view showing a first embodiment of an optical semiconductor device according to the present invention.
FIG. 4 is a second partial enlarged sectional view showing a first embodiment of the optical semiconductor device according to the invention.
FIG. 5 is a first partial enlarged sectional view showing a second embodiment of the optical semiconductor device according to the invention.
FIG. 6 is a second partial enlarged sectional view showing a second embodiment of the optical semiconductor device according to the invention.
FIG. 7 is a sectional view showing a modification of the optical semiconductor device according to the invention.
FIG. 8 is a diagram for explaining a conventional technique;
FIG. 9 is a diagram for explaining a conventional technique;
[Explanation of symbols]
1 Optical semiconductor device
Two-sided light emitting device
3 Light emitting part
4 Bump electrode
5 ring electrode
6 First electrode
7 Second electrode
8 Optical input section
9 First metal
10 Second metal
11 Optical wiring layer
12 Electrical wiring layer
13 Wiring board
14 Optical transmission part
15 Third metal
16 Sealing resin
Claims (4)
前記光半導体素子上に配置される前記発光素子または受光素子は、前記各素子周囲に配置される第１の電極上に形成され、前記発光素子または前記受光素子で出射された光信号を光伝送する光伝送部を備えた環状電極により、前記配線基板に主面が対向して前記光配線層の前記光伝送部に光学的に接続されており、
また、前記光半導体素子上には、前記発光素子または受光素子と接続される第２の電極が前記各素子に対応して形成されており、前記第２の電極上には、内部に第１の金属とその周囲に第２の金属を配置したバンプ電極が形成されており、前記バンプ電極を構成する前記第１の金属は前記第２の金属の融点よりも高い材料で構成されており、前記光半導体素子と前記配線基板との距離は，前記第１の金属の高さとほぼ同一であり、前記光半導体素子は、前記バンプ電極により前記配線基板に主面が対向して前記電気配線層の前記電気伝送部に接続されており、前記発光素子または受光素子と前記配線基板とで構成される隙間には樹脂が封止されていることを特徴とする光半導体装置。An optical semiconductor in which an optical semiconductor element having at least one light emitting element or light receiving element is mounted on a wiring substrate having an electrical wiring layer composed of an electrical insulation part and an electrical transmission part and an optical wiring layer composed of an optical insulation part and an optical transmission part In the device
The light emitting element or the light receiving element disposed on the optical semiconductor element is formed on a first electrode disposed around each element, and optically transmits an optical signal emitted from the light emitting element or the light receiving element. An annular electrode provided with an optical transmission part that is optically connected to the optical transmission part of the optical wiring layer with the main surface facing the wiring board,
In addition, a second electrode connected to the light emitting element or the light receiving element is formed on the optical semiconductor element corresponding to each element, and the first electrode is formed on the second electrode. metal and its surroundings are bump electrodes and the second metal is arranged is formed, the first metal constituting the bump electrode is formed of a material higher than the melting point of the second metal, The distance between the optical semiconductor element and the wiring substrate is substantially the same as the height of the first metal, and the optical semiconductor element has the main surface opposed to the wiring substrate by the bump electrode and the electric wiring layer. said being connected to the electrical transmission unit, an optical semiconductor device, characterized in that the resin is sealed in the gap formed between the wiring substrate and the light emitting element or a light receiving element.
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| JP2002094148A JP4104889B2 (en) | 2002-03-29 | 2002-03-29 | Optical semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| JP2002094148A JP4104889B2 (en) | 2002-03-29 | 2002-03-29 | Optical semiconductor device |
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| JP4104889B2 true JP4104889B2 (en) | 2008-06-18 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2005079385A (en) | 2003-09-01 | 2005-03-24 | Toshiba Corp | Optical semiconductor device and optical signal input/output device |
| US7453058B2 (en) * | 2005-03-15 | 2008-11-18 | Fujitsu Limited | Optical bumps for low-loss interconnection between a device and its supported substrate and related methods |
| JP4040644B2 (en) * | 2005-07-28 | 2008-01-30 | シャープ株式会社 | Method for manufacturing solder mounting structure and solder mounting method |
| JP4421528B2 (en) | 2005-07-28 | 2010-02-24 | シャープ株式会社 | Solder mounting structure, manufacturing method thereof, and use thereof |
| JP2007242686A (en) * | 2006-03-06 | 2007-09-20 | Ricoh Co Ltd | Surface light emitting laser array and image forming device having same |
| JP4793169B2 (en) | 2006-08-24 | 2011-10-12 | 日立電線株式会社 | Connector and optical transceiver module |
| EP1906496B1 (en) * | 2006-09-29 | 2010-01-06 | OSRAM Opto Semiconductors GmbH | Semiconductor laser and method for manufacturing the same |
| JP6536004B2 (en) * | 2014-08-11 | 2019-07-03 | 株式会社リコー | Surface emitting laser device and method of manufacturing the same |
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| JPS5946416B2 (en) * | 1979-09-19 | 1984-11-12 | 松下電器産業株式会社 | How to form electrode leads |
| JPS5660025A (en) * | 1979-10-19 | 1981-05-23 | Sharp Corp | Bonding method for semiconductor element |
| JP2888385B2 (en) * | 1991-08-22 | 1999-05-10 | 京セラ株式会社 | Flip-chip connection structure of light receiving / emitting element array |
| JP3257011B2 (en) * | 1992-01-08 | 2002-02-18 | 松下電器産業株式会社 | Method of assembling semiconductor device |
| JP3171477B2 (en) * | 1992-02-26 | 2001-05-28 | 株式会社東芝 | Semiconductor device |
| JPH05243391A (en) * | 1992-03-03 | 1993-09-21 | Nec Corp | Connecting method of optical ic to multilayer interconnection substrate |
| JP3162464B2 (en) * | 1992-03-18 | 2001-04-25 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JPH07142488A (en) * | 1993-11-15 | 1995-06-02 | Nec Corp | Bump structure, formation thereof and flip-chip mounting structure |
| JP3378334B2 (en) * | 1994-01-26 | 2003-02-17 | 株式会社東芝 | Semiconductor device mounting structure |
| JPH10270498A (en) * | 1997-03-27 | 1998-10-09 | Toshiba Corp | Manufacture of electronic device |
| JP3612243B2 (en) * | 1999-06-29 | 2005-01-19 | 株式会社東芝 | Optical wiring package and optical wiring device |
| JP3728147B2 (en) * | 1999-07-16 | 2005-12-21 | キヤノン株式会社 | Opto-electric hybrid wiring board |
| JP3625778B2 (en) * | 2001-03-30 | 2005-03-02 | 三洋電機株式会社 | Printed circuit board for mounting coin-type electrical elements |
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