JPS63252447A - Formation of bump of semiconductor element - Google Patents
Formation of bump of semiconductor elementInfo
- Publication number
- JPS63252447A JPS63252447A JP62087310A JP8731087A JPS63252447A JP S63252447 A JPS63252447 A JP S63252447A JP 62087310 A JP62087310 A JP 62087310A JP 8731087 A JP8731087 A JP 8731087A JP S63252447 A JPS63252447 A JP S63252447A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- semiconductor element
- plated
- protruding electrodes
- gold plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 230000015572 biosynthetic process Effects 0.000 title description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000010931 gold Substances 0.000 claims abstract description 24
- 229910052737 gold Inorganic materials 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000007747 plating Methods 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000004033 plastic Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 14
- 238000007906 compression Methods 0.000 abstract 2
- 230000007423 decrease Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 239000011889 copper foil Substances 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 150000001844 chromium Chemical class 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は電気機器等に使用される半導体素子の突起電極
の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming protruding electrodes of semiconductor elements used in electrical equipment and the like.
従来の技術 。Conventional technology.
従来の半導体素子の突起電極形成方法の第１の方法の各
工程を第４図ａ−ｃに従って具体的に説明する。まず第
４図ａに示すようにリード線となる銅箔１０の先端に厚
みが約６０μｍ〜１００μｍの金よりなる電極９が熱圧
着されたものを用意する。次に第４図すに示すように熱
圧着治具７を用いて半導体素子３の電極取出部となるア
ルミ電極５上に、前述の銅箔１０と一体化した金電極９
を熱圧着し、第４図０に示す半導体素子３のアルミ電極
６上に突起電極が形成された完成品を得る。Each step of the first method of the conventional method for forming protruding electrodes of a semiconductor device will be explained in detail with reference to FIGS. 4a to 4c. First, as shown in FIG. 4a, a copper foil 10 serving as a lead wire is prepared with an electrode 9 made of gold having a thickness of about 60 μm to 100 μm bonded by thermocompression to the tip. Next, as shown in FIG. 4, using a thermocompression bonding jig 7, a gold electrode 9 integrated with the aforementioned copper foil 10 is placed on the aluminum electrode 5 which will become the electrode extraction part of the semiconductor element 3.
are thermocompressed to obtain a finished product in which protruding electrodes are formed on the aluminum electrodes 6 of the semiconductor element 3 shown in FIG.
なお、４は半導体素子３の保護層を示している。Note that 4 indicates a protective layer of the semiconductor element 3.
次に、第２の方法の各工程を第６図ａ −ｆに従って具
体的に説明する。なお、第４図と同一の構成部品には同
一符号を付している。まず、第６図ａに示すように半導
体素子３のアルミ電極６を含む面全体にスパッタリング
によりクロム層１１を形成する。このクロム層１１の上
から銅をスパッタリングし銅薄膜層１２を形成した状態
を第５図すに示す。次に第６図Ｃに示すようにフォトレ
ジスト１３を全面にスピンナ塗布・硬化した後、所定の
パターニングを行い、さらに第５図ｄに示すように銅の
層を厚くする目的で銅メッキを行い銅メッキ層１４を形
成する。しかる後に、第６図ｅに示すようにフォトレジ
スト１３をエツチング除去し、銅薄膜１２やクロムＮ１
１の不要部分をエツチングする。この銅メッキ層１４の
上に半田ボール１５をリフローにて接合し、第６図ｆに
示す完成品となる。Next, each step of the second method will be specifically explained according to FIGS. 6a-f. Note that the same components as in FIG. 4 are given the same reference numerals. First, as shown in FIG. 6a, a chromium layer 11 is formed on the entire surface of the semiconductor element 3 including the aluminum electrode 6 by sputtering. FIG. 5 shows a state in which a thin copper film layer 12 is formed by sputtering copper from above this chromium layer 11. Next, as shown in FIG. 6C, photoresist 13 is coated with a spinner over the entire surface and cured, followed by predetermined patterning, and then copper plating is performed to thicken the copper layer as shown in FIG. 5D. A copper plating layer 14 is formed. Thereafter, as shown in FIG. 6e, the photoresist 13 is removed by etching, and the copper thin film 12 and chromium N1 are removed.
Etch the unnecessary parts of 1. Solder balls 15 are bonded onto this copper plating layer 14 by reflow, resulting in a completed product shown in FIG. 6f.
発明が解決しようとする問題点
ところが、上記第１の方法についてはリード線となる銅
箔１０が半導体素子７の表面に直接液することなく、電
極９を介して銅箔１０とアルミ電極６とを接合するため
には、金よりなる電極９の厚みが約５０μｍ〜１００μ
ｍ必要であるためコストは非常に高いものとなる。上記
第２の方法については工程が複雑であり、メッキ液やエ
ツチング液等が半導体素子３に触れるために半導体素子
３へのダメージが大きく信頼性が著しく低下する。Problems to be Solved by the Invention However, in the first method, the copper foil 10 serving as the lead wire is not directly applied to the surface of the semiconductor element 7, but is connected to the copper foil 10 and the aluminum electrode 6 via the electrode 9. In order to bond
Since m is required, the cost is very high. The second method has complicated steps, and since the plating solution, etching solution, etc. come into contact with the semiconductor element 3, the damage to the semiconductor element 3 is large and the reliability is significantly reduced.
また、製造工程で必要な設備がスピンナ塗布機。Additionally, a spinner coating machine is required equipment in the manufacturing process.
紫外線露光機、スパッタリング装置、メッキ装置等の高
価な設備が多いので製造費用も高くついてしまう欠点が
あった。This method has the disadvantage that manufacturing costs are high because it requires a lot of expensive equipment such as an ultraviolet exposure machine, a sputtering device, and a plating device.
本発明はこのような従来の問題点を解消するものであり
、簡単な構成で低コスト、かつ高信頼性の半導体素子の
突起電極形成方法を提供するものである。The present invention solves these conventional problems and provides a method for forming protruding electrodes of a semiconductor element with a simple structure, low cost, and high reliability.
問題点を解決するための手段
本発明の半導体素子の突起電極形成方法は、少なくとも
第１の面およびその第１の面に対向する第２の面にそれ
ぞれ金メッキされた部材の前記第１の面を、半導体素子
表面の電極取出部に熱圧着により接合することにより突
起電極を形成せんとするものである。Means for Solving the Problems The method for forming protruding electrodes of a semiconductor device according to the present invention provides a first surface of a member in which at least a first surface and a second surface opposite to the first surface are each plated with gold. A protruding electrode is formed by bonding the protruding electrode to the electrode lead-out portion on the surface of the semiconductor element by thermocompression bonding.
作用
この本発明の半導体素子の突起電極形成方法によれば、
突起電極として表面が金メッキされた部材を用いるため
に、金メッキの厚みは薄くてよくコストは非常に安くな
る。また、半導体素子のアルミ電極部に、この突起電極
を熱圧着して接合するだけであるため形成工法における
半導体素子へのダメージは少なく、かつ簡単な方法で工
程費用も安く形成できるものである。Effect: According to the method for forming protruding electrodes of a semiconductor device of the present invention,
Since a member whose surface is plated with gold is used as the protruding electrode, the thickness of the gold plating can be thin and the cost can be very low. Furthermore, since the protruding electrodes are simply bonded to the aluminum electrode portion of the semiconductor element by thermocompression bonding, there is little damage to the semiconductor element during the formation method, and the process can be formed using a simple method and at low cost.
実施例
以下、本発明の一実施例について各工程を第２図ａ ％
Ｃに従って具体的に説明する。なお、第５図と同一構
成部品には同一符号を付している。第２図＆は突起電極
の核になる部材１の断面図を示すもので、この部材１は
金属・セラミック・プラスチックのいづれであってもよ
いが、部材１の第１の表面となる１つの面１１Ｌは少な
くとも平坦であり、かつ半導体素子３のアルミ電極６の
面よりも外形サイズが小さいことを必要とするが、他の
形状については任意でよい。この部材１の全表面に第２
図すに示すように金をメッキし、金メッキ層２を形成す
る。次に第２図Ｃに示すように半導体素子３の上に、ア
ルミ電極６に対応する部分に孔のおいているメタルマス
ク６をのせて、金メッキされた前記部材１の面１ａがア
ルミ電極５と接するよりにアルミ電極５の位置に対応さ
せて配設し、熱圧着治具７を用いて熱圧着を行う。熱圧
着後メタルマスク６を除去して、第１図に示すように半
導体素子３のアルミ電極５上に突起電極を形成した完成
品ができる。この実施例によジ作成された突起電極は部
材１の第１の表面１ａとその表面に対向する第２の表面
１ｂとが金メッキ層２により電気的に接続されているた
め、部材１として電気抵抗の低い金属や熱伝導率の良い
セラミック、または軽量で成形が容易な樹脂等の内より
目的に応じて自由に選択できるものである。Example Below, each process of an example of the present invention is shown in Figure 2 a%.
This will be explained in detail according to Section C. Note that the same components as in FIG. 5 are given the same reference numerals. Figure 2 & shows a cross-sectional view of the member 1 that will become the core of the protruding electrode. This member 1 may be made of metal, ceramic, or plastic; Although the surface 11L needs to be at least flat and smaller in external size than the surface of the aluminum electrode 6 of the semiconductor element 3, other shapes may be arbitrary. A second layer is applied to the entire surface of this member 1.
As shown in the figure, gold is plated to form a gold plating layer 2. Next, as shown in FIG. The aluminum electrode 5 is placed so as to correspond to the position of the aluminum electrode 5 rather than being in contact with the aluminum electrode 5, and thermocompression bonding is performed using a thermocompression bonding jig 7. After thermocompression bonding, the metal mask 6 is removed to obtain a completed product in which protruding electrodes are formed on the aluminum electrodes 5 of the semiconductor element 3, as shown in FIG. The protruding electrode created in this example has a first surface 1a of the member 1 and a second surface 1b opposite to the first surface 1b which are electrically connected by the gold plating layer 2. Depending on the purpose, it can be freely selected from metals with low resistance, ceramics with good thermal conductivity, resins that are lightweight and easy to mold, etc.
以下、本発明の第２の実施例について第３図の各工程ａ
−ｄに従って具体的に説明する。この実施例における
第３回器に示す突起電極の核になる部材８は、酸化ルテ
ニウム等の電気的抵抗材料、あるいはチタン酸バリウム
等の比誘電率の大きなコンデンサ材料でできており、そ
の形状は第１の実施例と同一である。この部材８の第１
の表面８＆とその第１の表面８ａに対向する第２の表面
８ｂにのみ第３図すに示すように金メッキ２を行う。し
かる後に前述の第１の実施例の工程Ｃと同様にして、半
導体素子３のアルミ電極５上に金メッキ層２の形成され
た部材１を熱圧着し、熱圧着後メタルマスク６を除去し
て第３図ｄに示すように半導体素子３のアルミ電極６上
に突起電極を形成した完成品ができる。この実施例の場
合、前記部材８が電気抵抗体材料であれば、所定の電気
抵抗を介して信号の受授が行われるものであり、前記部
材８がコンデンサ材料であれば、所定の容量を介して信
号の受授が行なえるものである。Hereinafter, each step a in FIG. 3 regarding the second embodiment of the present invention.
-d will be specifically explained. The member 8, which is the core of the protruding electrode shown in the third part of this embodiment, is made of an electrically resistive material such as ruthenium oxide or a capacitor material with a high dielectric constant such as barium titanate, and its shape is This is the same as the first embodiment. The first part of this member 8
As shown in FIG. 3, gold plating 2 is applied only to the surface 8& and the second surface 8b opposite to the first surface 8a. Thereafter, the member 1 on which the gold plating layer 2 is formed is thermocompression bonded onto the aluminum electrode 5 of the semiconductor element 3 in the same manner as step C of the first embodiment described above, and after the thermocompression bonding, the metal mask 6 is removed. As shown in FIG. 3d, a finished product is produced in which protruding electrodes are formed on the aluminum electrode 6 of the semiconductor element 3. In the case of this embodiment, if the member 8 is an electrical resistor material, signals are received and received through a predetermined electrical resistance, and if the member 8 is a capacitor material, it has a predetermined capacitance. It is possible to send and receive signals through the device.
発明の効果
以上のように、本発明の半導体素子の突起電極形成方法
は、少なくとも対向する２つの表面に金メッキが施され
た部材を半導体素子表面の電極取出部に熱圧着して接合
し、半導体素子の突起電極を形成する方法であり、部材
の表面を金メッキして突起電極とするだめに金メッキの
厚さは薄くてよくコストは大幅に安く、また半導体素子
の受けるダメージは熱圧着時の熱と若干の圧力だけであ
るため信頼性も向上する。さらに部材に種々の材料を選
択できるために、突起電極自体にコンデンサあるいは抵
抗体等の様々な機能をもたすことができる等、実用性の
高い極めて有用なものである。Effects of the Invention As described above, the method for forming protruding electrodes on a semiconductor element according to the present invention includes bonding members whose at least two opposing surfaces are plated with gold to the electrode lead-out portions on the surface of the semiconductor element by thermocompression bonding. This is a method of forming protruding electrodes on devices. Since the surface of the component is plated with gold to form protruding electrodes, the thickness of the gold plating is thin and the cost is significantly lower. In addition, damage to semiconductor devices is caused by the heat generated during thermocompression bonding. Since only a slight amount of pressure is required, reliability is also improved. Furthermore, since various materials can be selected for the members, the projecting electrode itself can have various functions such as a capacitor or a resistor, making it highly practical and extremely useful.
第１図は本発明により作成された半導体素子の概略をボ
す側断面図、第２図は本発明の一実施例である半導体素
子の突起電極形成方法を行程順にに示す側断面図、第３
図は本発明の第２の実施例である半導体素子の突起電極
形成方法を工程順に示す側断面図、第４図は従来の半導
体素子の突起電極形成方法を工程順に示す側断面図、第
６図は従来の半導体素子の他の突起電極形成方法を工程
順に示す側断面図である。
１・・・・・・部材、２・・・・・・金メッキ層、３・
・・・・・半導体素子、４・・・・・・保護層、６・・
・・・・アルミ電極。FIG. 1 is a side cross-sectional view schematically showing a semiconductor device manufactured according to the present invention, and FIG. 3
FIG. 4 is a side sectional view showing a conventional method for forming protruding electrodes on a semiconductor device in order of steps, according to a second embodiment of the present invention; FIG. The figure is a side sectional view showing the process order of another conventional method for forming protruding electrodes of a semiconductor element. 1... Member, 2... Gold plating layer, 3.
...Semiconductor element, 4...Protective layer, 6...
...Aluminum electrode.
Claims (6)
る第２の表面にそれぞれ金メッキ処理された部材を、前
記第１の表面が半導体素子の電極取出部と当接するより
熱圧着して接合することを特徴とする半導体素子の突起
電極形成方法。(1) At least a first surface and a second surface opposite the first surface are each plated with gold, and the first surface is in contact with the electrode lead-out portion of the semiconductor element by thermocompression bonding. A method for forming protruding electrodes of a semiconductor device, the method comprising bonding.
囲第１項記載の半導体素子の突起電極形成方法。(2) The method for forming protruding electrodes of a semiconductor device according to claim 1, wherein the member is made of metal.
の表面に施された金メッキが前記部材の側面に施された
金メッキにより電気的に接続されていることを特徴とす
る特許請求の範囲第１項記載の半導体素子の突起電極形
成方法。(3) The member is ceramic, and the first surface and the second surface
2. The method of forming protruding electrodes of a semiconductor element according to claim 1, wherein the gold plating applied to the surface of the member is electrically connected to the gold plating applied to the side surface of the member.
２の表面に施された金メッキが前記部材の側面に施され
た金メッキにより電気的に接続された金メッキにより電
気的に接続されていることを特徴とする特許請求の範囲
第１項記載の半導体素子の突起電極形成方法。(4) The member is made of plastic, and the gold plating applied to the first surface and the second surface are electrically connected by the gold plating applied to the side surface of the member. A method for forming protruding electrodes of a semiconductor device according to claim 1, characterized in that:
特許請求の範囲第１項記載の半導体素子の突起電極形成
方法。(5) A method for forming protruding electrodes of a semiconductor device according to claim 1, wherein the member is an electrical resistor material.
面と第２の表面に施された金メッキ層間でコンデンサを
形成することを特徴とする特許請求の範囲第１項記載の
半導体素子の突起電極形成方法。(6) The semiconductor according to claim 1, wherein the member is made of a material with a high dielectric constant, and a capacitor is formed between the gold plating layer applied to the first surface and the second surface. Method for forming protruding electrodes of elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62087310A JP2502581B2 (en) | 1987-04-09 | 1987-04-09 | Method for forming protruding electrode of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62087310A JP2502581B2 (en) | 1987-04-09 | 1987-04-09 | Method for forming protruding electrode of semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63252447A true JPS63252447A (en) | 1988-10-19 |
| JP2502581B2 JP2502581B2 (en) | 1996-05-29 |
Family
ID=13911262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62087310A Expired - Fee Related JP2502581B2 (en) | 1987-04-09 | 1987-04-09 | Method for forming protruding electrode of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2502581B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0362927A (en) * | 1989-07-31 | 1991-03-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| US5665639A (en) * | 1994-02-23 | 1997-09-09 | Cypress Semiconductor Corp. | Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal |
| JP2002353264A (en) * | 2001-05-29 | 2002-12-06 | Toppan Printing Co Ltd | Semiconductor element with bumps and semiconductor device using the same |
| WO2009136468A1 (en) * | 2008-05-09 | 2009-11-12 | パナソニック株式会社 | Semiconductor device and method for manufacturing the same |
| JP2011009742A (en) * | 2009-06-25 | 2011-01-13 | Internatl Business Mach Corp <Ibm> | Integrated circuit chip package, structure and method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5265860A (en) * | 1975-11-29 | 1977-05-31 | Fujitsu Ltd | Method of connecting lead wire |
| JPS59143352A (en) * | 1983-02-05 | 1984-08-16 | Matsushita Electric Ind Co Ltd | Film carrier with bump and manufacture thereof |
-
1987
- 1987-04-09 JP JP62087310A patent/JP2502581B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5265860A (en) * | 1975-11-29 | 1977-05-31 | Fujitsu Ltd | Method of connecting lead wire |
| JPS59143352A (en) * | 1983-02-05 | 1984-08-16 | Matsushita Electric Ind Co Ltd | Film carrier with bump and manufacture thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0362927A (en) * | 1989-07-31 | 1991-03-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| US5665639A (en) * | 1994-02-23 | 1997-09-09 | Cypress Semiconductor Corp. | Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal |
| JP2002353264A (en) * | 2001-05-29 | 2002-12-06 | Toppan Printing Co Ltd | Semiconductor element with bumps and semiconductor device using the same |
| WO2009136468A1 (en) * | 2008-05-09 | 2009-11-12 | パナソニック株式会社 | Semiconductor device and method for manufacturing the same |
| US8415794B2 (en) | 2008-05-09 | 2013-04-09 | Panasonic Corporation | Semiconductor device having stable signal transmission at high speed and high frequency |
| JP2011009742A (en) * | 2009-06-25 | 2011-01-13 | Internatl Business Mach Corp <Ibm> | Integrated circuit chip package, structure and method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2502581B2 (en) | 1996-05-29 |
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