JPH01175294A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPH01175294A JPH01175294A JP33483687A JP33483687A JPH01175294A JP H01175294 A JPH01175294 A JP H01175294A JP 33483687 A JP33483687 A JP 33483687A JP 33483687 A JP33483687 A JP 33483687A JP H01175294 A JPH01175294 A JP H01175294A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- resistor
- pattern
- circuit board
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 38
- 239000011521 glass Substances 0.000 claims abstract description 18
- 239000012212 insulator Substances 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 abstract description 12
- 239000010408 film Substances 0.000 abstract description 7
- 239000010409 thin film Substances 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract 3
- 230000000694 effects Effects 0.000 description 2
- 229910009973 Ti2O3 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- GQUJEMVIKWQAEH-UHFFFAOYSA-N titanium(III) oxide Chemical compound O=[Ti]O[Ti]=O GQUJEMVIKWQAEH-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はガラス基板を用い、このガラス基板上に抵抗お
よびコンデンサが混在して形成される回路基板に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a circuit board using a glass substrate on which resistors and capacitors are formed in a mixed manner.
従来の技術
従来、回路基板に実装される電子部品として、半導体部
品はパッケージされた物が用いられ、他の個別部品はデ
ィスクリートの物が用いられることが多かった。しかし
、近年、実装面積の削減、コストダウンの目的のために
、半導体部品としてパッケージされてないペアチップを
実装し、基板上に個別部品を印刷、焼成して構成された
回路基 板を用いた製品が多くなってきた。BACKGROUND ART Conventionally, packaged semiconductor components have often been used as electronic components mounted on circuit boards, and other individual components have often been discrete. However, in recent years, in order to reduce the mounting area and cost, products using circuit boards that are constructed by mounting paired chips that are not packaged as semiconductor components, printing and firing individual components on the board have been introduced. are becoming more common.
ガラス基板上に半導体部品をフェースダウンしく素子形
成面をガラス基板に向けて実装し）、フリップチップ実
装した例を第２図に示す。半導体チップ１は、ガラス基
板２の上に形成された配線のんパターン３に、半導体チ
ップｌの電極部に形成されたＡｕバンプ４を熱圧着させ
て実装されている。FIG. 2 shows an example of flip-chip mounting in which semiconductor components are mounted face down on a glass substrate with the element formation surface facing the glass substrate. The semiconductor chip 1 is mounted on a wiring pattern 3 formed on a glass substrate 2 by thermocompression bonding Au bumps 4 formed on electrode portions of the semiconductor chip 1.
また、個別部品の抵抗とコンデンサを同じガラス基板２
の上に形成した例を第３図と第４図に示す。抵抗５は第
３図に示すように、ガラス基板２の上の配線のＡｕパタ
ーン３の間に抵抗体のＲｕ２Ｏ３の薄膜６を形成して構
成され、コンデンサ７は第４図に示すように、ガラス基
板２の上の配線のんパターン３の上に高誘電体のＰｄＴ
ｉ２Ｏ．からなる絶総膜８を形成し、さらにその上に第
２層Ｍパターン９を形成して構成されている。コンデン
サ７はＡｕパターン３．９を両方の電極としている。In addition, the individual components resistors and capacitors are placed on the same glass substrate.
An example formed on the surface is shown in FIGS. 3 and 4. As shown in FIG. 3, the resistor 5 is constructed by forming a thin film 6 of Ru2O3 as a resistor between the Au patterns 3 of the wiring on the glass substrate 2, and the capacitor 7 is as shown in FIG. High dielectric PdT is placed on the wiring pattern 3 on the glass substrate 2.
i2O. An absolute film 8 is formed, and a second layer M pattern 9 is further formed thereon. Capacitor 7 has Au pattern 3.9 as both electrodes.
発明が解決しようとする問題点
しかし、従来のコンデンサ７の構成ではんパターンを２
度印刷、焼成する必要があり、ガラス基板２の１に構成
しようとするコンデンサ７の数が少ない場合、特に工数
増加によるコストダウンメリットの減少となっていた。Problems to be Solved by the Invention However, the configuration of the conventional capacitor 7 has two solder patterns.
It is necessary to print and bake the glass substrate 2 repeatedly, and when the number of capacitors 7 to be constructed on one of the glass substrates 2 is small, the cost reduction advantage is reduced due to an increase in the number of man-hours.
本発明は上記問題点を解決するものであり、工数を削減
し、コストダウンが図れる回路基板を提供することを目
的とするものである。The present invention solves the above problems, and aims to provide a circuit board that can reduce the number of man-hours and reduce costs.
問題点を解決するための手段
と記問題点を解決するため本発明は、部品実装基板にガ
ラス基板を用い、前記ガラス基板上に抵抗およびコンデ
ンサの一方の極となるパターンをＲｕ２Ｏ．で形成し、
前記コンデンサの一方の極とななる配線パターンと前記
抵抗に接続される配線パターンとをんで形成してなるも
のである。Means for Solving the Problems and Description: In order to solve the problems, the present invention uses a glass substrate as a component mounting board, and a pattern of Ru2O. formed with
It is formed by a wiring pattern that becomes one pole of the capacitor and a wiring pattern that is connected to the resistor.
作用
上記構成によれば、コンデンサをガラス基板にて構成さ
れた部品実装基板上に構成するにあたり、コンデンサの
一方の電極を抵抗を形成するＲｕ２Ｏ。Effect According to the above configuration, when a capacitor is constructed on a component mounting board made of a glass substrate, one electrode of the capacitor is made of Ru2O forming a resistor.
で形成し、コンデンサの他方の電極を、抵抗に接続され
る配線パターンの形成と同時にひとつの勤パターンで形
成する。よって、抵抗とコンデンサが混在する回路基板
の工数は、従来のように抵抗を形成し、コンデンサの両
方の極をＡｕパターンで形成する回路基板の工数より少
なくなる。The other electrode of the capacitor is formed in a single pattern at the same time as the wiring pattern connected to the resistor is formed. Therefore, the number of man-hours required for a circuit board in which a resistor and a capacitor are mixed together is smaller than that for a circuit board in which a resistor is formed and both poles of a capacitor are formed with an Au pattern as in the past.
実施例 以下、本発明の一実施例を図面に基づいて説明する。Example Hereinafter, one embodiment of the present invention will be described based on the drawings.
第１図（ａ）および第１図（ｂ）は本発明の回路基板の
断面図および抵抗、コンデンサ部の平面図である。FIGS. 1(a) and 1(b) are a sectional view of a circuit board of the present invention and a plan view of a resistor and a capacitor portion.
第１図（ａ）、（ｂ）において、部品実装基板であるガ
ラス基板１１の上に半導体チップ１２が実装され、抵抗
１３およびコンデンサ１４が形成されて回路基板が構成
されている。In FIGS. 1(a) and 1(b), a semiconductor chip 12 is mounted on a glass substrate 11 which is a component mounting board, and a resistor 13 and a capacitor 14 are formed to constitute a circuit board.
第１図（ａ）に示す上記回路基板の形成方法を説明する
。まず、ガラス基板１１の上に抵抗１３およびコンデン
サ１４の一方の極となるパターンをＲｕ２Ｏ３の薄膜１
５で形成し、コンデンサ１４の一方の極となるＲｕ２Ｏ
，のパターンの薄膜１５の上に高誘導体で絶縁体のＰｄ
Ｔｉ２Ｏ３の絶縁膜１６を形成し、さらに、このＰｄＴ
ｉ！０３の絶縁膜１Ｇの上に形成されてコンデンサ１４
の他方の極となる配線パターンと、抵抗１３に接続され
る配線パターンと、抵抗１３とコンデンサ１４の一方の
極とを接続するパターンとを同じＡｕパターン１７で形
成する。Ｒｕ２Ｏ．の比抵抗は数１０Ωメロであり、第
１図（ｂ）に示すように、コンデンサ１４の下の一方の
電極として用いる部分は充分広い幅をとることで抵抗値
を小さくできる。A method of forming the circuit board shown in FIG. 1(a) will be explained. First, a pattern that will become one pole of the resistor 13 and the capacitor 14 is formed on the glass substrate 11 using a thin film 1 of Ru2O3.
5 and becomes one pole of the capacitor 14.
, on the thin film 15 with a pattern of
A Ti2O3 insulating film 16 is formed, and this PdT
i! The capacitor 14 is formed on the insulating film 1G of 03.
The wiring pattern serving as the other pole, the wiring pattern connected to the resistor 13, and the pattern connecting the resistor 13 and one pole of the capacitor 14 are formed of the same Au pattern 17. Ru2O. The specific resistance of the capacitor 14 is several tens of ohms, and as shown in FIG. 1(b), the resistance value can be reduced by making the portion used as one electrode under the capacitor 14 sufficiently wide.
次にＡｕパターン１７に半導体チップ１２の電極部に形
成されたＡｕバンプ１８を熱圧着させて半導体チップ１
２を実装し回路基板が形成される。Next, the Au bumps 18 formed on the electrode portions of the semiconductor chip 12 are bonded to the Au pattern 17 by thermocompression, and the semiconductor chip 1
2 is mounted to form a circuit board.
このように、従来のコンデンサの両方の極をＡｕパター
ンで形成した回路基板の工数と比較して、コンデンサの
一方の極をＲｕ２Ｏ３の薄膜１５で代用し、他方の極を
他の配線パターンと同じＡｕパターンで形成するため、
Ａｕパターンを形成する工程が少なくて済み、コストダ
ウンを図ることができる。In this way, compared to the man-hours required for a circuit board in which both poles of a conventional capacitor are formed with an Au pattern, one pole of the capacitor is replaced with a thin film 15 of Ru2O3, and the other pole is made with the same wiring pattern as the other one. Since it is formed with an Au pattern,
There are fewer steps to form the Au pattern, and costs can be reduced.
発明の効果
以上のように本発明によれば、コンデンサをガラス基板
にて構成された部品実装基板上に形成するにあたり、コ
ンデンサの一方の電極を抵抗を形成するＲｕ２Ｏ３で形
成し、他方の電極を、抵抗に接続される配線パターンと
同じＡｕパターンで形成することにより、抵抗とコンデ
ンサが混在する回路基板の工数を、コンデンサの両極を
Ａｕパターンで形成する回路基板の工数より削減するこ
とができ、コストダウンを図ることができる。Effects of the Invention As described above, according to the present invention, when a capacitor is formed on a component mounting board made of a glass substrate, one electrode of the capacitor is formed of Ru2O3 which forms a resistance, and the other electrode is formed of Ru2O3, which forms a resistance. By forming the wiring pattern with the same Au pattern as the wiring pattern connected to the resistor, the number of man-hours required for a circuit board in which a resistor and a capacitor are mixed can be reduced compared to the number of man-hours required for a circuit board in which both poles of the capacitor are formed with an Au pattern. Cost reduction can be achieved.
第１図（ａ）および（ｂ）は本発明の一実施例を示す回
路基板の断面図および抵抗、コンデンサ部の平面因、第
２図は従来の半導体チップを実装した回路基板の断面図
、第３図は従来の抵抗を基板上に形成した回路基板の断
面図、第４図は従来のコンデンサを基板上に形成した回
路基板の断面図である。
１１・・・ガラス基板、１３・・・抵抗、１４・・・コ
ンデンサ、１５−Ｒｕ２Ｏ３（７） ｎ膜、１６−Ｐｄ
Ｔｉ 、Ｏ８の絶縁膜、１７ ・・・Ａｕパターン。FIGS. 1(a) and (b) are a cross-sectional view of a circuit board showing an embodiment of the present invention, and the plan view of the resistor and capacitor portions; FIG. 2 is a cross-sectional view of a circuit board on which a conventional semiconductor chip is mounted; FIG. 3 is a sectional view of a circuit board on which a conventional resistor is formed, and FIG. 4 is a sectional view of a circuit board on which a conventional capacitor is formed. 11...Glass substrate, 13...Resistor, 14...Capacitor, 15-Ru2O3(7)n film, 16-Pd
Ti, O8 insulating film, 17...Au pattern.
Claims (1)
上に抵抗およびコンデンサの一方の極となるパターンを
Ｒｕ＿２Ｏ＿３で形成し、前記コンデンサの一方の極と
なるＲｕ＿２Ｏ＿３のパターン上に高誘電体で絶縁体の
ＰｄＴｉ＿２Ｏ＿３を形成し、前記ＰｄＴｉ＿２Ｏ＿３
の上に形成されて前記コンデンサの他方の極となる配線
パターンと前記抵抗に接続される配線パターンとをＡｕ
で形成してなる回路基板。1. A glass substrate is used as a component mounting board, a pattern of Ru_2O_3 is formed on the glass substrate to become one pole of a resistor and a capacitor, and a high dielectric insulator is formed on the pattern of Ru_2O_3 which is one pole of the capacitor. PdTi_2O_3 is formed, and the PdTi_2O_3
A wiring pattern formed on the top and serving as the other pole of the capacitor and a wiring pattern connected to the resistor are made of Au.
A circuit board made of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62334836A JP2545107B2 (en) | 1987-12-28 | 1987-12-28 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62334836A JP2545107B2 (en) | 1987-12-28 | 1987-12-28 | Circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01175294A true JPH01175294A (en) | 1989-07-11 |
| JP2545107B2 JP2545107B2 (en) | 1996-10-16 |
Family
ID=18281764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62334836A Expired - Lifetime JP2545107B2 (en) | 1987-12-28 | 1987-12-28 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2545107B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0387055A (en) * | 1989-08-30 | 1991-04-11 | Nec Corp | Thin film capacitor and manufacture thereof |
| JPH03108752A (en) * | 1989-09-22 | 1991-05-08 | Nec Corp | Semiconductor device |
-
1987
- 1987-12-28 JP JP62334836A patent/JP2545107B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0387055A (en) * | 1989-08-30 | 1991-04-11 | Nec Corp | Thin film capacitor and manufacture thereof |
| JPH03108752A (en) * | 1989-09-22 | 1991-05-08 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2545107B2 (en) | 1996-10-16 |
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