JPH03116797A - Thick film surface package circuit - Google Patents
Thick film surface package circuitInfo
- Publication number
- JPH03116797A JPH03116797A JP1253330A JP25333089A JPH03116797A JP H03116797 A JPH03116797 A JP H03116797A JP 1253330 A JP1253330 A JP 1253330A JP 25333089 A JP25333089 A JP 25333089A JP H03116797 A JPH03116797 A JP H03116797A
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- film conductor
- printed
- dried
- anisotropic conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 31
- 239000011347 resin Substances 0.000 claims abstract description 18
- 229920005989 resin Polymers 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 9
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000000853 adhesive Substances 0.000 abstract description 10
- 230000001070 adhesive effect Effects 0.000 abstract description 10
- 229910000679 solder Inorganic materials 0.000 abstract description 8
- 239000006071 cream Substances 0.000 abstract description 5
- 230000001681 protective effect Effects 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 238000001035 drying Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000010301 surface-oxidation reaction Methods 0.000 description 2
- 230000000740 bleeding effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はアルミナ基板上に設けた表面実装回路に関する
。特にアルミナ基板上に設けた高周波回路用の多層から
なる厚膜導体配線からなる高密度表面実装回路に関する
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to surface mount circuits provided on alumina substrates. In particular, the present invention relates to a high-density surface mount circuit made of multilayer thick film conductor wiring for high frequency circuits provided on an alumina substrate.
従来の技術
近年、実装密度の向上にともない配線パターンの微細化
、抵抗体・コンデンサー内蔵、多層化、放熱効率の観点
からセラミック基板上に厚膜配線を施した表面実装が大
きな比重を占めるようになってきた。Conventional technology In recent years, as packaging density has improved, surface mounting, which uses thick film wiring on ceramic substrates, has become more popular from the viewpoints of finer wiring patterns, built-in resistors and capacitors, multilayering, and heat dissipation efficiency. It has become.
この種の多層厚膜導体配線は、第２図に示す要部構成を
有していた。すなわち、アルミナ基板２１上にＡｇ−Ｐ
ｄｒ！ＬｌｌあるいはＣｕ厚膜からなる厚膜導体２２と
、ガラスを主成分とする絶縁層２３と、Ａｇ−Ｐｄ厚膜
あるいはＣｕ厚膜からなる厚膜導体２４とをおのおの所
定の形状に印刷・乾燥・焼成の後、保護樹脂２５を印刷
・乾燥させる。続いて、クリーム半田２６を印刷し、例
えば樹脂モールドＩＣ２７を接着し、リフロー工程を施
すことにより樹脂モールドＩＣ２７の端子２７ａ、２７
ｂと厚膜導体２２とを半田付けを行い表面実装していた
。This type of multilayer thick film conductor wiring had the main part configuration shown in FIG. That is, Ag-P is placed on the alumina substrate 21.
dr! A thick film conductor 22 made of Lll or Cu thick film, an insulating layer 23 mainly made of glass, and a thick film conductor 24 made of Ag-Pd thick film or Cu thick film are each printed, dried, and shaped into a predetermined shape. After baking, the protective resin 25 is printed and dried. Next, cream solder 26 is printed, the resin molded IC 27 is bonded, and a reflow process is performed to form the terminals 27a, 27 of the resin molded IC 27.
b and the thick film conductor 22 were soldered and surface mounted.
発明が解決しようとする課題
近年、表面実装の高密度化に伴い樹脂モールドＩＣの端
子間ピッチ距離の狭小化が計られている。Problems to be Solved by the Invention In recent years, with the increasing density of surface mounting, efforts have been made to reduce the pitch distance between terminals of resin molded ICs.
従来の１−ピッチから０．８ｍピッチの実用化が行われ
、更に０．６５＋ａピツチの実用化が一部で進められて
いる、しかし、表面実装の高密度・微細化に伴い、前記
従来技術にかかる構成では、例えば０．４−ピッチでは
、クリーム半田の印刷性が十分でなく、クリーム半田の
かすれ・にじみ等により微細パターンの形成が困難であ
った。更に、リフロー工程において、第２図に示す端子
半田付の半田２６が半田の表面張力により接合し、端子
間で短絡し実装不良が発生すると言うＲ，Ｂを有してい
た。The conventional 1-pitch has been put into practical use with a pitch of 0.8 m, and furthermore, the practical use of a 0.65+a pitch is progressing in some areas. However, with the increasing density and miniaturization of surface mounting, the conventional technology In such a configuration, for example, at a pitch of 0.4, the printability of the cream solder was not sufficient, and it was difficult to form a fine pattern due to blurring, bleeding, etc. of the cream solder. Furthermore, in the reflow process, the solder 26 of the terminal soldering shown in FIG. 2 was bonded due to the surface tension of the solder, and had R and B which caused a short circuit between the terminals and a mounting failure.
上記課題を解決するために、Ａｇ−Ｐｄ厚膜配線上に異
方性導電接着剤を介して樹脂モールドＩＣと電気的接続
を得る方法が提案されている。しかし、この方法では配
線抵抗がＣｕ厚膜配線に比べ１桁高いため高周波回路に
は適さない、一方、Ｃｕ厚膜配線の場合、異方性導電接
着剤による表面実装は、Ｃｕ厚膜表面の酸化膜により良
好な電気的接続が得られないと言う課題を有していた。In order to solve the above-mentioned problems, a method of obtaining electrical connection with a resin molded IC via an anisotropic conductive adhesive on Ag--Pd thick film wiring has been proposed. However, this method is not suitable for high-frequency circuits because the wiring resistance is one order of magnitude higher than that of Cu thick film wiring.On the other hand, in the case of Cu thick film wiring, surface mounting using an anisotropic conductive adhesive is The problem was that a good electrical connection could not be obtained due to the oxide film.
本発明は上記課題に鑑みて、従来の高密度・微細化に係
る実装不良の改善をはかることを目的とするものである
。In view of the above-mentioned problems, the present invention aims to improve the mounting defects associated with conventional high-density and miniaturization.
課題を解決するための手段
本発明は、アルミナ基板上に所定の回路形状に設けたＡ
ｇを主成分とする第１厚膜導体と、前記第１厚膜導体上
に所定の形状に設けた絶縁層と、前記絶縁層に具備され
たビアホールを介して前記第１厚膜導体と電気的に短絡
させたＣｕを主成分とする第２厚膜導体とを備え、前記
第１厚＋ｉ導体とチップ部品を異方性導電樹脂により電
気的に短絡させた構成により厚膜表面実装回路を形成す
るものである。Means for Solving the Problems The present invention provides an A, which is provided in a prescribed circuit shape on an alumina substrate.
a first thick film conductor whose main component is g, an insulating layer provided in a predetermined shape on the first thick film conductor, and an electrical connection between the first thick film conductor and the first thick film conductor through a via hole provided in the insulating layer. A thick film surface mount circuit is provided with a second thick film conductor mainly composed of Cu which is short-circuited, and the first thick conductor and the chip component are electrically short-circuited by an anisotropic conductive resin. It is something that forms.
作用
本発明の構成によれば、第１厚膜導体をＡｇを主成分と
しているので、導体表面の酸化が無いため、異方性導電
接着剤と容易に電気的に接続が可能である。更に、異方
性導電接着剤を用いているので、端子間距離０．１ｍｓ
＋ピンチの樹脂モールドＩＣとの電気的接続が可能であ
る。かつ端子接続以外の信号配線はＣｕを主成分とする
第２厚膜導体を用いているので配線インピーダンスが低
く高側以下に図面を参照して本究明の厚膜衣ＩＩＯ炎暑
回路の一実施例について詳細に説明する。Effects According to the structure of the present invention, since the first thick film conductor is mainly composed of Ag, there is no oxidation of the conductor surface, so that electrical connection with the anisotropic conductive adhesive is easily possible. Furthermore, since an anisotropic conductive adhesive is used, the distance between terminals is 0.1ms.
It is possible to electrically connect with a pinch resin molded IC. Moreover, since the signal wiring other than the terminal connection uses the second thick film conductor whose main component is Cu, the wiring impedance is low. will be explained in detail.
本発明に係る実施例を第１図に示す、同図は本発明の要
部断面構造を示したものである。すなわち、アルミナ基
板１１上にＡｇ−Ｐｄ厚膜からなる第１厚膜導体１２を
印刷・乾燥し、更に絶縁層１３を印刷・乾燥したのち、
空気中９００℃で焼成する。An embodiment according to the present invention is shown in FIG. 1, which shows a cross-sectional structure of the main part of the present invention. That is, after printing and drying the first thick film conductor 12 made of Ag-Pd thick film on the alumina substrate 11 and further printing and drying the insulating layer 13,
Calcinate in air at 900°C.
続いて、低温焼成用のＣｕ厚膜（第２厚膜等体）１４を
印刷・乾燥したのち、窒素雰囲気中６５０℃にて焼成す
る。この工程において第１厚膜導体（Ａｇ−Ｐｄ厚膜１
２とＣｕ厚膜１４とは絶縁層１３に設けたビアホール１
３ａを介して電気的に接続される。Subsequently, a Cu thick film (second thick film etc.) 14 for low temperature firing is printed and dried, and then fired at 650° C. in a nitrogen atmosphere. In this step, the first thick film conductor (Ag-Pd thick film 1
2 and the Cu thick film 14 are the via holes 1 provided in the insulating layer 13.
It is electrically connected via 3a.
次に、配線保護のため保護樹脂１５を印刷・乾燥させる
。クリーム半田を印刷しチップ抵抗、チップコンデンサ
ー等のチップ部品を接着し、リフロー工程において半田
付けを行う、この工程において、第１厚膜導体１２は表
面温度２００〜２６０℃の温度に晒されるが、Ａｇ−Ｐ
ｄ厚膜の表面酸化は問題とはならない０次に異方性導電
接着剤１６を印刷し、樹脂モールドＩＣ１７を接着・乾
燥硬化させる。この接着・乾燥硬化工程において、異方
性導電接着剤１６中の金属成分が互いに結合し、樹脂モ
ールドＩＣ端子１７ａ、１７ｂと第１厚膜導体１２が各
々独立に電気的に短絡し、ＩＣ実装が完了するものであ
る。Next, a protective resin 15 is printed and dried to protect the wiring. Cream solder is printed, chip components such as chip resistors and chip capacitors are bonded, and soldering is performed in a reflow process. In this process, the first thick film conductor 12 is exposed to a surface temperature of 200 to 260°C. Ag-P
d Surface oxidation of the thick film is not a problem. A zero-order anisotropic conductive adhesive 16 is printed, and the resin molded IC 17 is bonded and dried to harden. In this adhesion/drying and curing process, the metal components in the anisotropic conductive adhesive 16 bond to each other, and the resin molded IC terminals 17a, 17b and the first thick film conductor 12 are each independently electrically short-circuited, and the IC is mounted. is completed.
更に、Ａｇ−Ｐｄ厚膜をアース配線として用いることに
より、シールド効果をあげることができ、高密度高周波
用回路として適している。Furthermore, by using the Ag--Pd thick film as the ground wiring, a shielding effect can be achieved, making it suitable for high-density, high-frequency circuits.
発明の効果
本発明に係る厚膜表面実装回路は、樹脂モールド【Ｃを
Ａｇ−Ｐｄ厚膜配線と異方性導電接着剤とを用いて実装
する構造である。したがって、ＩＣ以外の他のチップ部
品を半田リフロー工程で実装したのち、ＩＣを実装して
もＡｇ−Ｐｄ厚膜配線の表面酸化は問題熱いため容易に
電気的結合が可能であると言う効果を有している。更に
、この構造を用いることにより、ＩＣ端子間ピッチ０．
１■も実現可能であり、この種の厚膜表面実装回路の高
密度化に極めて効果のあるものである。Effects of the Invention The thick film surface mount circuit according to the present invention has a structure in which a resin mold [C] is mounted using Ag-Pd thick film wiring and an anisotropic conductive adhesive. Therefore, even if the IC is mounted after other chip components other than the IC are mounted using the solder reflow process, the surface oxidation of the Ag-Pd thick film wiring is a problem, so the effect that electrical connection is easily possible can be avoided. have. Furthermore, by using this structure, the pitch between IC terminals can be reduced to 0.
1 is also possible and is extremely effective in increasing the density of this type of thick film surface mount circuit.
第１図は本発明の一実施例にかかる厚膜表面実装回路の
要部構造を示す断面図、第２図は従来の技術に係る要部
断面図である。
１１・・・・・・アルミナ基板、１２・・・・・・第１
厚膜導体、１３・・・・・・絶縁層、１４・・・・・・
第２厚膜導体、１５・・・・・・保護樹脂、１６・・・
・・・異方性導電接着剤、１７・・・・・・樹脂モール
ドＩＣ０FIG. 1 is a sectional view showing the main structure of a thick film surface mount circuit according to an embodiment of the present invention, and FIG. 2 is a sectional view of the main part according to a conventional technique. 11... Alumina substrate, 12... First
Thick film conductor, 13...Insulating layer, 14...
Second thick film conductor, 15... Protective resin, 16...
...Anisotropic conductive adhesive, 17...Resin mold IC0
Claims (1)
分とする第１厚膜導体と、前記第１厚膜導体上に所定の
形状に設けた絶縁層と、前記絶縁層に具備されたビアホ
ールを介して前記第１厚膜導体と電気的に短絡させたＣ
ｕを主成分とする第２厚膜導体とを備え、前記第１厚膜
導体とチップ部品を異方性導電樹脂により電気的に短絡
させたことを特徴とする厚膜表面実装回路。A first thick film conductor mainly composed of Ag provided in a predetermined circuit shape on an alumina substrate, an insulating layer provided in a predetermined shape on the first thick film conductor, and a via hole provided in the insulating layer. C electrically shorted to the first thick film conductor via
1. A thick film surface mount circuit comprising: a second thick film conductor containing u as a main component, the first thick film conductor and a chip component being electrically short-circuited by an anisotropic conductive resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1253330A JPH03116797A (en) | 1989-09-28 | 1989-09-28 | Thick film surface package circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1253330A JPH03116797A (en) | 1989-09-28 | 1989-09-28 | Thick film surface package circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03116797A true JPH03116797A (en) | 1991-05-17 |
Family
ID=17249811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1253330A Pending JPH03116797A (en) | 1989-09-28 | 1989-09-28 | Thick film surface package circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03116797A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05191028A (en) * | 1991-11-15 | 1993-07-30 | Toshiba Corp | Semiconductor module |
| JPH0670279U (en) * | 1993-03-05 | 1994-09-30 | 株式会社アドバンテスト | Hybrid IC |
| US5540835A (en) * | 1994-02-17 | 1996-07-30 | Sanderson; Charles H. | Growth regulation of zebra mussels through magnetic water treatment |
-
1989
- 1989-09-28 JP JP1253330A patent/JPH03116797A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05191028A (en) * | 1991-11-15 | 1993-07-30 | Toshiba Corp | Semiconductor module |
| JPH0670279U (en) * | 1993-03-05 | 1994-09-30 | 株式会社アドバンテスト | Hybrid IC |
| US5540835A (en) * | 1994-02-17 | 1996-07-30 | Sanderson; Charles H. | Growth regulation of zebra mussels through magnetic water treatment |
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