JPS57193051A - Multilayer circuit board - Google Patents

Multilayer circuit board

Info

Publication number
JPS57193051A
JPS57193051A JP7895981A JP7895981A JPS57193051A JP S57193051 A JPS57193051 A JP S57193051A JP 7895981 A JP7895981 A JP 7895981A JP 7895981 A JP7895981 A JP 7895981A JP S57193051 A JPS57193051 A JP S57193051A
Authority
JP
Japan
Prior art keywords
circuit board
pins
layer
board
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7895981A
Other languages
Japanese (ja)
Inventor
Tatsuo Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7895981A priority Critical patent/JPS57193051A/en
Publication of JPS57193051A publication Critical patent/JPS57193051A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a multilayer circuit board which can be readily corrected in high density by mounting externally connecting pins on one surface of the ceramic circuit board of multilayer and connecting the pins to the circuit formed in the interior or on the surface of an insulating layer of organic macromolecule on the other surface. CONSTITUTION:A conductive pattern printed on a green sheet is positioned, superposed, baked and solidified to form a laminated ceramic circuit board 30 having a conductive layer 32 and a pad 33. Externally connecting pins 34 made of Kovar alloy are soldered to the board 30. Then, an insulating layer 35 of polyimide series is formed on the board 30, a conductive layer 36 is selectively formed by copper plating, and a multilayer wiring layer is formed repeatedly. Since the layers 35 and 36 can be formed by a low temperature treatment, they can be formed without damaging the mounting of the pins 34, and can be corrected. The layer 36 may be formed in a high density by a photoetching method.
JP7895981A 1981-05-25 1981-05-25 Multilayer circuit board Pending JPS57193051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7895981A JPS57193051A (en) 1981-05-25 1981-05-25 Multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7895981A JPS57193051A (en) 1981-05-25 1981-05-25 Multilayer circuit board

Publications (1)

Publication Number Publication Date
JPS57193051A true JPS57193051A (en) 1982-11-27

Family

ID=13676424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7895981A Pending JPS57193051A (en) 1981-05-25 1981-05-25 Multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS57193051A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2567684A1 (en) * 1984-07-10 1986-01-17 Nec Corp MODULE HAVING A MULTILAYER CERAMIC SUBSTRATE AND A MULTILAYER CIRCUIT ON THE SUBSTRATE AND METHOD FOR THE PRODUCTION THEREOF
JPS62119951A (en) * 1985-11-19 1987-06-01 Nec Corp Multilayer interconnection substrate
US5196089A (en) * 1990-08-28 1993-03-23 Ngk Spark Plug Co., Ltd. Multilayer ceramic substrate for mounting of semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50526A (en) * 1973-05-09 1975-01-07
JPS5028655A (en) * 1973-07-17 1975-03-24
JPS5341190A (en) * 1976-08-27 1978-04-14 Ibm Method of improving adhesion to polyimide layer of metallic layer
JPS6225737A (en) * 1985-07-26 1987-02-03 Canon Inc Indicator for frame number of film

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50526A (en) * 1973-05-09 1975-01-07
JPS5028655A (en) * 1973-07-17 1975-03-24
JPS5341190A (en) * 1976-08-27 1978-04-14 Ibm Method of improving adhesion to polyimide layer of metallic layer
JPS6225737A (en) * 1985-07-26 1987-02-03 Canon Inc Indicator for frame number of film

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2567684A1 (en) * 1984-07-10 1986-01-17 Nec Corp MODULE HAVING A MULTILAYER CERAMIC SUBSTRATE AND A MULTILAYER CIRCUIT ON THE SUBSTRATE AND METHOD FOR THE PRODUCTION THEREOF
JPS62119951A (en) * 1985-11-19 1987-06-01 Nec Corp Multilayer interconnection substrate
JPH053760B2 (en) * 1985-11-19 1993-01-18 Nippon Electric Co
US5196089A (en) * 1990-08-28 1993-03-23 Ngk Spark Plug Co., Ltd. Multilayer ceramic substrate for mounting of semiconductor device

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