JPS6424446A - Printed board and manufacture thereof - Google Patents

Printed board and manufacture thereof

Info

Publication number
JPS6424446A
JPS6424446A JP62181926A JP18192687A JPS6424446A JP S6424446 A JPS6424446 A JP S6424446A JP 62181926 A JP62181926 A JP 62181926A JP 18192687 A JP18192687 A JP 18192687A JP S6424446 A JPS6424446 A JP S6424446A
Authority
JP
Japan
Prior art keywords
copper sheet
recession
power supply
patterns
gnd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62181926A
Other languages
Japanese (ja)
Other versions
JPH0787223B2 (en
Inventor
Nobuhiro Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62181926A priority Critical patent/JPH0787223B2/en
Publication of JPS6424446A publication Critical patent/JPS6424446A/en
Publication of JPH0787223B2 publication Critical patent/JPH0787223B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]

Abstract

PURPOSE:To cool down a mounted electronic part without decreasing the inner resistance value of power supply or earth patterns due to formation of a recession enabling the patterns to be exposed to a capacitor by cooling down the power supply or earth (GND) layer. CONSTITUTION:A copper sheet 12 is formed after the pattern of a power supply or GND by photoetching process etc., to be held by two each of insulating sheets 3 and then copper foils 1 are arranged both outsides of the insulating sheets to be laminated. Then, specified wiring patterns are formed on both surface and rear side of the copper sheet 1 by photoetching process etc. Next, a recession 14 reaching the copper sheet 12 is formed by machining the position to mount an electronic part and the wiring pattern vacancy on the main surface side. Then, an electronic component (semiconductor element) 5 is cooled down by cooling down the copper sheet 12 after mounting the electronic component 5 on the copper sheet 12 exposed to the recession 14. In such a constitution, the inner resistance value of the patterns of power supply or GND is not varied due to the thickness of copper sheet 12 laminated in several hundred mum even if the pattern of copper sheet 12 is damaged by a minor error in the depth from the surface to the bottom by machining so that the recession 14 may be formed easily.
JP62181926A 1987-07-20 1987-07-20 Printed circuit board and manufacturing method thereof Expired - Lifetime JPH0787223B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62181926A JPH0787223B2 (en) 1987-07-20 1987-07-20 Printed circuit board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62181926A JPH0787223B2 (en) 1987-07-20 1987-07-20 Printed circuit board and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS6424446A true JPS6424446A (en) 1989-01-26
JPH0787223B2 JPH0787223B2 (en) 1995-09-20

Family

ID=16109316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62181926A Expired - Lifetime JPH0787223B2 (en) 1987-07-20 1987-07-20 Printed circuit board and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH0787223B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277142A (en) * 1988-09-13 1990-03-16 Nec Corp Package structure
EP0407905A2 (en) * 1989-07-08 1991-01-16 DODUCO GMBH + Co Dr. Eugen DÀ¼rrwächter Flat body, in particular for application as a heat sink for electronic power components
JPH08130272A (en) * 1994-10-31 1996-05-21 Nec Corp Semiconductor integrated circuit device
WO1996042134A1 (en) * 1995-06-09 1996-12-27 Matsushita Electric Industrial Co., Ltd. Amplifier
JP2018207118A (en) * 2018-08-10 2018-12-27 太陽誘電株式会社 Circuit module
CN113271719A (en) * 2021-06-23 2021-08-17 昆山丘钛生物识别科技有限公司 Flexible circuit board processing method, device and equipment

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5897956B2 (en) * 2012-03-29 2016-04-06 京セラ株式会社 Component built-in board and mounting structure
JP5623364B2 (en) * 2011-09-30 2014-11-12 京セラ株式会社 Wiring board, mounting structure, and electronic device
CN103843467B (en) * 2011-09-30 2016-11-23 京瓷株式会社 Circuit board, built-in substrate and assembling structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198790A (en) * 1983-04-26 1984-11-10 イビデン株式会社 Printed circuit board
JPS62263685A (en) * 1986-05-12 1987-11-16 沖電気工業株式会社 Printed wiring board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198790A (en) * 1983-04-26 1984-11-10 イビデン株式会社 Printed circuit board
JPS62263685A (en) * 1986-05-12 1987-11-16 沖電気工業株式会社 Printed wiring board

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277142A (en) * 1988-09-13 1990-03-16 Nec Corp Package structure
EP0407905A2 (en) * 1989-07-08 1991-01-16 DODUCO GMBH + Co Dr. Eugen DÀ¼rrwächter Flat body, in particular for application as a heat sink for electronic power components
JPH08130272A (en) * 1994-10-31 1996-05-21 Nec Corp Semiconductor integrated circuit device
WO1996042134A1 (en) * 1995-06-09 1996-12-27 Matsushita Electric Industrial Co., Ltd. Amplifier
JP2018207118A (en) * 2018-08-10 2018-12-27 太陽誘電株式会社 Circuit module
CN113271719A (en) * 2021-06-23 2021-08-17 昆山丘钛生物识别科技有限公司 Flexible circuit board processing method, device and equipment
CN113271719B (en) * 2021-06-23 2022-07-08 昆山丘钛生物识别科技有限公司 Flexible circuit board processing method, device and equipment

Also Published As

Publication number Publication date
JPH0787223B2 (en) 1995-09-20

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