JPH0277142A - Package structure - Google Patents
Package structureInfo
- Publication number
- JPH0277142A JPH0277142A JP63230324A JP23032488A JPH0277142A JP H0277142 A JPH0277142 A JP H0277142A JP 63230324 A JP63230324 A JP 63230324A JP 23032488 A JP23032488 A JP 23032488A JP H0277142 A JPH0277142 A JP H0277142A
- Authority
- JP
- Japan
- Prior art keywords
- lsi
- layer
- printed wiring
- wiring board
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004308 accommodation Effects 0.000 abstract description 2
- 239000000853 adhesive Substances 0.000 abstract description 2
- 238000005476 soldering Methods 0.000 abstract description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はパッケージ構造に関し、特にＬＳＩの実装構造
を改良したパッケージ構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package structure, and particularly to a package structure in which an LSI mounting structure is improved.
従来のパッケージ構造は、第２図Ａ、Ｂに示すように、
第１の信号層２、第２の信号層３、グランド層４、電源
層５からなる。プリント配線板１の一部分を切り抜き、
そこにテープ・オートメイテッド・ボンディング（ＴＡ
Ｂ）構造などのＬＳＩ８を挿入し、ＬＳＩにつながるリ
ード７をプリント配線板１上に設けられた電極９に接続
することにより薄型化を図っていた。The conventional package structure is as shown in Fig. 2A and B.
It consists of a first signal layer 2, a second signal layer 3, a ground layer 4, and a power layer 5. Cut out a part of the printed wiring board 1,
Tape automated bonding (TA)
B) A thinner structure was achieved by inserting an LSI 8 such as a structure and connecting a lead 7 connected to the LSI to an electrode 9 provided on the printed wiring board 1.
上述した従来のパッケージ構造は、ＬＳＩのプリント配
線板への固定がリードだけによってなされているため、
ＬＳＩから発生した熱は主にＬＳＩのリードを伝わって
プリント配線板へ伝導される経路しか放熱経路を持たず
、ＬＳＩの温度が高くなってしまい誤動作の原因になる
という欠点がある。また、ＬＳＩの固定がリードだけで
なされているため、振動、衝撃などの機械的強度が弱い
という欠点がある。In the conventional package structure described above, the LSI is fixed to the printed wiring board only by the leads.
The only heat dissipation path for the heat generated from the LSI is through the leads of the LSI and conducted to the printed wiring board, which has the drawback of increasing the temperature of the LSI and causing malfunction. Furthermore, since the LSI is fixed only with leads, there is a drawback that mechanical strength against vibrations, shocks, etc. is weak.
さらに、薄型化のためにプリント配線板を完全に切り抜
いてしまうため信号層のパターン収容性が悪くなるとい
う欠点もある。Furthermore, since the printed wiring board is completely cut out in order to make it thinner, there is also the drawback that the pattern accommodating property of the signal layer becomes poor.
本発明は、表面に信号層を有し、内層にグランド層およ
び電源層を有するプリント配線板上に、前記信号層上に
形成された電極につながるリードを有するＬＳ工を搭載
してなるパッケージ構造において、前記プリント配線板
の該ＬＳＩ搭載エリアを表面から前記グランド層または
前記電源層まで削除したくぼみ部に前記ＬＳ工を搭載し
て構成したことを特徴とするものである。The present invention provides a package structure in which an LS fabrication having leads connected to electrodes formed on the signal layer is mounted on a printed wiring board having a signal layer on the surface and a ground layer and a power layer on the inner layer. In the present invention, the LSI mounting area of the printed wiring board is constructed by mounting the LS work in a recessed portion removed from the surface to the ground layer or the power supply layer.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図Ａは本発明の一実施例の縦断面図、第１図Ｂは本
発明の他の実施例の縦断面図である。FIG. 1A is a longitudinal cross-sectional view of one embodiment of the present invention, and FIG. 1B is a longitudinal cross-sectional view of another embodiment of the present invention.
プリント配線板１は表面に第１の信号層２および第２の
信号層３を有し、内部にグランド層４および電源層５を
有しており、さらに、部分的に表面からグランド層４ま
たは電源層５まで削除されたくぼみ部６を有している。The printed wiring board 1 has a first signal layer 2 and a second signal layer 3 on the surface, a ground layer 4 and a power layer 5 inside, and further has a ground layer 4 or a power layer 5 partially on the surface. It has a recessed portion 6 which is removed up to the power supply layer 5.
電気接続のためのリード７を有するＬＳＩ８はプリント
配線板１のくぼみ部６に搭載されハンダ付けまたは良熱
伝導性接着剤によりグランド層４またば電源層５に固着
されている。ＬＳＩ８のり−ド７はプリント配線板１上
に設けられた電極に接続されＬＳＩ８とプリント配線板
１は電気的に接続されている。An LSI 8 having leads 7 for electrical connection is mounted in the recess 6 of the printed wiring board 1 and fixed to the ground layer 4 or the power layer 5 by soldering or a good heat conductive adhesive. The LSI 8 board 7 is connected to an electrode provided on the printed wiring board 1, and the LSI 8 and the printed wiring board 1 are electrically connected.
本実施例のパッケージ構造はＣｕなどの良熱伝導性の金
属からなりプリント配線板１全面に拡がった薄板状のグ
ランド層４または電源層５に、ＬＳＩ８が固着されてい
るため、ＬＳＩ８の発生した熱はこの良熱伝導性の金属
部を通してプリント配線板１全体に低熱抵抗で広がり、
ＬＳＩ８の温度を低く押えることができＬＳＩ８の誤動
作を防止できる。またＬＳＩ８が、くぼみ部６とは言え
プリント配線板１上に固着されているため、振動。In the package structure of this embodiment, the LSI 8 is fixed to a thin plate-shaped ground layer 4 or power supply layer 5 made of a metal with good thermal conductivity such as Cu and spread over the entire surface of the printed wiring board 1. Heat spreads throughout the printed wiring board 1 through this metal part with good thermal conductivity with low thermal resistance.
The temperature of the LSI 8 can be kept low and malfunctions of the LSI 8 can be prevented. Also, since the LSI 8 is fixed on the printed wiring board 1, although it is in the recessed part 6, it vibrates.
衝撃などに対する機械的強度が強い。さらに、くぼみ部
６はプリント配線板１を完全に切り抜いていないため、
第２の信号層３のＬＳＩ８の真下にあたるエリアにも信
号パターンを配置することができ、パターン収容性も高
めることができる。Strong mechanical strength against impact. Furthermore, since the recessed portion 6 does not completely cut out the printed wiring board 1,
Signal patterns can also be placed in the area directly below the LSI 8 of the second signal layer 3, and pattern accommodation can also be improved.
以上説明したように本発明は、プリント配線板のＬＳＩ
が搭載されるエリアを表面からグランド層または電源層
まで削除することにより、ＬＳＩの温度を低く押えるこ
とによる信頼性の向上および信号パターンの収容性を高
めることができるという効果を奏する。As explained above, the present invention is an LSI of a printed wiring board.
By eliminating the area where the LSI is mounted from the surface to the ground layer or power layer, it is possible to improve the reliability by keeping the temperature of the LSI low and to increase the capacity for signal patterns.
第１図Ａは本発明の一実施例の縦断面図、第１図Ｂは本
発明の他の実施例の縦断面図、第２図Ａ。
Ｂは従来例の平面図、縦断面図である。
１・・・プリント配線板、２・・・第１の信号層、３・
・・第２の信号層、４・・・グランド層、５・・・電源
層、６・・・くぼみ部、７・・・リード、８・・・ＬＳ
Ｉ、９・・・電極。FIG. 1A is a vertical cross-sectional view of one embodiment of the present invention, FIG. 1B is a vertical cross-sectional view of another embodiment of the present invention, and FIG. 2A is a vertical cross-sectional view of another embodiment of the present invention. B is a plan view and a vertical sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1... Printed wiring board, 2... First signal layer, 3...
...Second signal layer, 4...Ground layer, 5...Power supply layer, 6...Recessed portion, 7...Lead, 8...LS
I, 9...electrode.
Claims (1)
を有するプリント配線板上に、前記信号層上に形成され
た電極につながるリードを有するＬＳＩを搭載してなる
パッケージ構造において、前記プリント配線板の該ＬＳ
Ｉ搭載エリアを表面から前記グランド層または前記電源
層まで削除したくぼみ部に前記ＬＳ工を搭載して構成し
たことを特徴とするパッケージ構造。In a package structure in which an LSI having leads connected to electrodes formed on the signal layer is mounted on a printed wiring board having a signal layer on the surface and a ground layer and a power supply layer on the inner layer, the printed wiring The corresponding LS of the board
A package structure characterized in that the LS work is mounted in a recessed part where the I mounting area is removed from the surface to the ground layer or the power supply layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63230324A JPH0277142A (en) | 1988-09-13 | 1988-09-13 | Package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63230324A JPH0277142A (en) | 1988-09-13 | 1988-09-13 | Package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0277142A true JPH0277142A (en) | 1990-03-16 |
Family
ID=16906047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63230324A Pending JPH0277142A (en) | 1988-09-13 | 1988-09-13 | Package structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0277142A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5525834A (en) * | 1994-10-17 | 1996-06-11 | W. L. Gore & Associates, Inc. | Integrated circuit package |
| US5701032A (en) * | 1994-10-17 | 1997-12-23 | W. L. Gore & Associates, Inc. | Integrated circuit package |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6424446A (en) * | 1987-07-20 | 1989-01-26 | Fujitsu Ltd | Printed board and manufacture thereof |
-
1988
- 1988-09-13 JP JP63230324A patent/JPH0277142A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6424446A (en) * | 1987-07-20 | 1989-01-26 | Fujitsu Ltd | Printed board and manufacture thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5525834A (en) * | 1994-10-17 | 1996-06-11 | W. L. Gore & Associates, Inc. | Integrated circuit package |
| US5701032A (en) * | 1994-10-17 | 1997-12-23 | W. L. Gore & Associates, Inc. | Integrated circuit package |
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