JPH05136289A - Thick film circuit substrate - Google Patents

Thick film circuit substrate

Info

Publication number
JPH05136289A
JPH05136289A JP3296960A JP29696091A JPH05136289A JP H05136289 A JPH05136289 A JP H05136289A JP 3296960 A JP3296960 A JP 3296960A JP 29696091 A JP29696091 A JP 29696091A JP H05136289 A JPH05136289 A JP H05136289A
Authority
JP
Japan
Prior art keywords
wiring layer
lower wiring
bonding
layer
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3296960A
Other languages
Japanese (ja)
Inventor
Masayuki Arakawa
雅之 荒川
Masao Segawa
雅雄 瀬川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba AVE Co Ltd
Original Assignee
Toshiba Corp
Toshiba AVE Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba AVE Co Ltd filed Critical Toshiba Corp
Priority to JP3296960A priority Critical patent/JPH05136289A/en
Publication of JPH05136289A publication Critical patent/JPH05136289A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To realize good bonding without lowering bonding strength by preventing relief by glass frit during re-burning by providing an upper wiring layer with a bonding pad. CONSTITUTION:A lower wiring layer 12, and further, an insulating layer 13 are printed, burnt and formed on an insulating substrate 11. In the process, a surface of the re-burnt lower wiring layer 12 is relieved by glass frit added to copper paste and a glass layer 14 is formed. Then, a jumper line 15a and a bonding pad 15b are printed and burnt as an upper wiring layer. The jumper line 15a and the bonding pad 15b melt the glass layer 14 existing in the lower wiring layer 12 during burning and are surely combined to the lower wiring layer 12. Since there is no possibility that the bonding pad 15b is re-burnt, lower wiring layer 12 is not relieved by glass frit inside and glass is not formed. Bonding of satisfactory strength to an upper wiring layer surface becomes possible in this way.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は厚膜回路基板に係り、
特にワイヤボンディング時における接合精度の低下を防
ぐようにした厚膜回路基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thick film circuit board,
In particular, the present invention relates to a thick film circuit board that prevents a decrease in bonding accuracy during wire bonding.

【０００２】[0002]

【従来の技術】近年、電子機器の小型軽量化を図るた
め、ハイブリッドＩＣが多用されてきている。ハイブリ
ッドＩＣは一般的にアルミナなどの絶縁基板上に導電性
ペーストや抵抗ペーストを印刷、焼成して配線パターン
や抵抗体を形成した印刷配線基板上にチップタイプの受
動素子やフラットパッケージなどの能動素子を実装した
ものである。このような、ハイブリッドＩＣは高密度、
高機能化するために、ベアチップ技術が取り入れられて
きている。なかでも、ワイヤボンデッングを用いた実装
は一般的である。2. Description of the Related Art In recent years, hybrid ICs have been widely used to reduce the size and weight of electronic equipment. A hybrid IC is generally an active element such as a chip type passive element or a flat package on a printed wiring board in which a conductive pattern or a resistance paste is printed and fired on an insulating substrate such as alumina to form a wiring pattern or a resistor. It is an implementation of. Such a hybrid IC has a high density,
Bare-chip technology has been adopted for higher functionality. Of these, mounting using wire bonding is common.

【０００３】図２はワイヤボンディングによる実装技術
を用いた、従来の製造プロセスを示したものである。FIG. 2 shows a conventional manufacturing process using a mounting technique by wire bonding.

【０００４】図２の（ａ）において、アルミナなどの絶
縁回路基板２１上にスクリーン印刷法により、銅ペース
トにより回路パターンを印刷したのち、焼成して下層配
線層２２を形成する。In FIG. 2A, a circuit pattern is printed on an insulating circuit board 21 made of alumina or the like by a screen printing method using a copper paste and then baked to form a lower wiring layer 22.

【０００５】つぎに、図２（ｂ）に示すように、絶縁体
ペーストをジャンパー部に印刷、焼成して絶縁体層２３
を形成する。このとき下層配線層２２は、再度焼成され
ることになる。このとき、下層配線層２２の表面には、
下層配線層２２を絶縁回路基板２１に密着させる目的
で、銅ペーストに含有したガラスフリットが浮き出てき
てガラス層２４を形成する。Next, as shown in FIG. 2B, an insulator paste is printed on the jumper portion and fired to form the insulator layer 23.
To form. At this time, the lower wiring layer 22 will be fired again. At this time, on the surface of the lower wiring layer 22,
In order to bring the lower wiring layer 22 into close contact with the insulating circuit board 21, the glass frit contained in the copper paste is raised to form the glass layer 24.

【０００６】図２（ｃ）において、ジャンパー線２５と
して上層配線層を印刷、焼成してする。ジャンパー線２
５は、焼成時に下層配線層２２の表面に形成されたガラ
ス層２４を溶かした状態で、下層配線層２２との電気的
な接続を行う。ごれにより下層配線層２２は、再度焼成
されることとなり、ガラス層２４が増加する。In FIG. 2C, an upper wiring layer is printed as the jumper wire 25 and fired. Jumper wire 2
5 is a state in which the glass layer 24 formed on the surface of the lower wiring layer 22 at the time of firing is melted, and is electrically connected to the lower wiring layer 22. The lower wiring layer 22 is fired again due to dust, and the glass layer 24 increases.

【０００７】図２（ｄ）において、抵抗やコンデンサな
どのチップ部品２６をリフロー半田付けにより接続し、
ベアチップ２７を銀ペーストなどにより、ダイボンディ
ングを行う。In FIG. 2D, chip parts 26 such as resistors and capacitors are connected by reflow soldering,
The bare chip 27 is die-bonded with silver paste or the like.

【０００８】図２（ｅ）において、金ワイヤー２８によ
り、ベアチップ２７と下層配線層２２の所定箇所に形成
したボンディングパット２９とのワイヤボンディングを
行い、最後にポッティング樹脂３０により封止する。In FIG. 2E, the bare chip 27 and the bonding pad 29 formed at a predetermined position of the lower wiring layer 22 are wire-bonded by the gold wire 28, and finally sealed by the potting resin 30.

【０００９】上記した構成の厚膜回路基板における、ベ
アチップ２７のボンディングはチップ部品２６などの実
装後に行うため、金ワイヤー２８にガラス層２５が溶け
る程度の温度を与えてボンディングすることは不可能で
ある。このため、ガラス層２４は、下層配線層２２に設
けられたボンディングパット上に存在したままである。
この状態でボンディングを行っても十分なボンディング
強度が得られないという問題があった。In the thick-film circuit board having the above-mentioned structure, the bare chip 27 is bonded after mounting the chip parts 26 and the like, and therefore it is impossible to bond the gold wire 28 to a temperature enough to melt the glass layer 25. is there. Therefore, the glass layer 24 remains on the bonding pad provided on the lower wiring layer 22.
There is a problem that sufficient bonding strength cannot be obtained even if bonding is performed in this state.

【００１０】[0010]

【発明が解決しようとする課題】上記したように従来の
厚膜回路基板では、下層配線層に含有されるガラスフリ
ットが再焼成により、配線層表面に浮き出てくるため、
十分なボンディング強度が得られないという問題があっ
た。As described above, in the conventional thick film circuit board, the glass frit contained in the lower wiring layer comes out on the surface of the wiring layer due to re-baking.
There is a problem that sufficient bonding strength cannot be obtained.

【００１１】この発明は上記の問題点を除去し、ボンデ
ィング強度を低下させることなく、良好なボンディング
の行える厚膜回路基板を提供することを、目的とするも
のである。An object of the present invention is to eliminate the above-mentioned problems and to provide a thick film circuit board capable of good bonding without lowering the bonding strength.

【００１２】[0012]

【課題を解決するための手段】この発明の厚膜回路基板
は、絶縁基板と、前記絶縁基板上に、ガラスフリットを
含有した導電性のペーストを印刷、焼成して形成した下
層配線層と、前記下層配線層上に誘電体層を介して印
刷、焼成し、該下層配線層に電気的に結合して形成した
上層配線層と、前記上層配線層にボンディングしたベア
チップとから構成してなるものである。A thick film circuit board of the present invention comprises an insulating substrate, and a lower wiring layer formed by printing and firing a conductive paste containing glass frit on the insulating substrate. A structure comprising an upper wiring layer formed by printing and firing on the lower wiring layer through a dielectric layer and electrically coupled to the lower wiring layer, and a bare chip bonded to the upper wiring layer. Is.

【００１３】[0013]

【作用】上記した手段により、ボンディングパッドを上
層配線層に設けた構造にしたため、再焼成時のガラスフ
リットの浮き出しを生じなくすることができる。このた
め、ワイヤボンディング時に十分なボンディング強度を
得ることができる。Since the bonding pad is provided in the upper wiring layer by the above means, it is possible to prevent the glass frit from being raised during re-firing. Therefore, sufficient bonding strength can be obtained during wire bonding.

【００１４】[0014]

【実施例】以下、この発明の実施例につき図面を参照し
て詳細に説明する。図１はこの発明にかかる、厚膜回路
基板の製造プロセスのー実施例を示すものである。Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows an embodiment of a manufacturing process of a thick film circuit board according to the present invention.

【００１５】図１の（ａ）において、１１はたとえばア
ルミナで形成された絶縁基板である。この絶縁基板１１
上に銅ペーストを用い、スクリーン印刷法により回路パ
ターンを印刷したのち、焼成して下層配線層１２を形成
する。In FIG. 1A, 11 is an insulating substrate made of alumina, for example. This insulating substrate 11
A circuit pattern is printed on the top by a screen printing method using a copper paste, and then baked to form the lower wiring layer 12.

【００１６】図１（ｂ）において、絶縁性ペーストによ
り、絶縁層１３を印刷、焼成し形成する。このとき、再
焼成された下層配線層１２の表面には、下層配線層１２
を絶縁回路基板１１に密着させる目的で、銅ペーストに
含有したガラスフリットが浮き出てきてガラス層１４を
形成する。In FIG. 1B, the insulating layer 13 is formed by printing and firing with an insulating paste. At this time, on the surface of the re-fired lower wiring layer 12, the lower wiring layer 12 is
The glass frit contained in the copper paste is raised to form the glass layer 14 in order to bring the glass frit into close contact with the insulating circuit board 11.

【００１７】つぎに、図１（ｃ）において、ジャンパー
線１５ａとボンディングパッド１５ｂを上層配線層とし
て印刷焼成する。ジャンパー線１５ａとボンディングパ
ッド１５ｂは焼成時、下層配線層１２に存在するガラス
層１４を溶かして下層配線層１２に確実に結合する。Next, in FIG. 1C, the jumper wire 15a and the bonding pad 15b are printed and fired as an upper wiring layer. During firing, the jumper wires 15a and the bonding pads 15b melt the glass layer 14 present in the lower wiring layer 12 and are reliably bonded to the lower wiring layer 12.

【００１８】図１（ｄ）において、抵抗やコンデンサな
どのチップ部品１６をリフロー半田付けにより実装し、
またベアチップ１７も銀ペーストなどによりダイボンデ
ィングする。In FIG. 1D, chip components 16 such as resistors and capacitors are mounted by reflow soldering,
The bare chip 17 is also die-bonded with silver paste or the like.

【００１９】図１（ｅ）において、金ワイヤー１８によ
り、ボンディングパッド１５ｂにボンディングを行い、
最後にポッティング樹脂１９により、ボンディング部１
５ｃを封止する。In FIG. 1 (e), the gold wire 18 is used to bond the bonding pad 15b.
Finally, the potting resin 19 is used to bond 1
5c is sealed.

【００２０】上記した構成により得られた厚膜回路基板
は、ジャンパー線１５ａとボンディングパッド１５ｂな
どの上層配線層によって形成された、ボンディングパッ
ド１５ｂは、再焼成されることはない。このためボンデ
ィングパッド１５ｂからは、下層配線層１２内のガラス
フリットの浮き出しが生じることがなく、ガラスは形成
されない。したがって良好な上層配線層表面にボンディ
ングされるため、十分なボンディング強度を得ることが
できる。In the thick film circuit board obtained by the above structure, the bonding pad 15b formed by the upper wiring layer such as the jumper wire 15a and the bonding pad 15b is not re-fired. Therefore, the glass frit in the lower wiring layer 12 does not rise from the bonding pad 15b, and the glass is not formed. Therefore, since the bonding is performed on the surface of the upper wiring layer, a sufficient bonding strength can be obtained.

【００２１】[0021]

【発明の効果】以上記載したように、この発明の厚膜回
路基板によれば、ボンディング強度の低下もなく信頼性
も向上する。As described above, according to the thick film circuit board of the present invention, the bonding strength is not lowered and the reliability is improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明のー実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図２】従来の断面図である。FIG. 2 is a conventional cross-sectional view.

【符号の説明】[Explanation of symbols]

１１…絶縁基板、１２…下層配線層、１５ａ…ジャンパ
ー線、１５ｂ…ボンディングパッド、１７…ベアチッ
プ。11 ... Insulating substrate, 12 ... Lower wiring layer, 15a ... Jumper wire, 15b ... Bonding pad, 17 ... Bare chip.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 絶縁基板と、 前記絶縁基板上にガラスフリットを含有した導電性のペ
ーストを印刷、焼成して形成した下層配線層と、 前記下層配線層上に印刷、焼成し、該下層配線層に電気
的に結合して形成した上層配線層と、 前記上層配線層にボンディングしたベアチップとからな
ることを特徴とする厚膜回路基板。1. An insulating substrate, a lower wiring layer formed by printing and firing a conductive paste containing glass frit on the insulating substrate, and a lower wiring layer printed and fired on the lower wiring layer. A thick film circuit board comprising: an upper wiring layer formed by being electrically coupled to a layer; and a bare chip bonded to the upper wiring layer.
JP3296960A 1991-11-13 1991-11-13 Thick film circuit substrate Withdrawn JPH05136289A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3296960A JPH05136289A (en) 1991-11-13 1991-11-13 Thick film circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3296960A JPH05136289A (en) 1991-11-13 1991-11-13 Thick film circuit substrate

Publications (1)

Publication Number Publication Date
JPH05136289A true JPH05136289A (en) 1993-06-01

Family

ID=17840424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3296960A Withdrawn JPH05136289A (en) 1991-11-13 1991-11-13 Thick film circuit substrate

Country Status (1)

Country Link
JP (1) JPH05136289A (en)

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Legal Events

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A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990204