JPH03108752A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03108752A JPH03108752A JP1247232A JP24723289A JPH03108752A JP H03108752 A JPH03108752 A JP H03108752A JP 1247232 A JP1247232 A JP 1247232A JP 24723289 A JP24723289 A JP 24723289A JP H03108752 A JPH03108752 A JP H03108752A
- Authority
- JP
- Japan
- Prior art keywords
- oxide
- film
- dielectric
- capacitor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000003990 capacitor Substances 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 11
- 239000010409 thin film Substances 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 abstract description 24
- 230000003647 oxidation Effects 0.000 abstract description 9
- 238000007254 oxidation reaction Methods 0.000 abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 230000007423 decrease Effects 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000007740 vapor deposition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 21
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 4
- 229910001936 tantalum oxide Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000010406 interfacial reaction Methods 0.000 description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000010561 standard procedure Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- NKZSPGSOXYXWQA-UHFFFAOYSA-N dioxido(oxo)titanium;lead(2+) Chemical compound [Pb+2].[O-][Ti]([O-])=O NKZSPGSOXYXWQA-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- -1 tungsten silicide Chemical compound 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はキャパシタを含む半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device including a capacitor.
ＭＯ３型ダイナミックランダムアクセスメモリ（Ｄ−Ｒ
ＡＭ）等において基板と一体化して形成される酸化物系
薄膜を誘電体とするキャパシタにおいては、電極として
多結晶シリコンや金属からなる非酸化物導体が用いられ
、あるいはこれか検討されている。MO3 type dynamic random access memory (D-R
In capacitors whose dielectric is an oxide-based thin film formed integrally with a substrate in AM), etc., non-oxide conductors made of polycrystalline silicon or metal are used as electrodes, or are being considered.
しかしながら、非酸化物導体電極の場合には、酸化物系
誘電体薄膜形成時に酸化性雰囲気により電極表面の酸化
が生じたり、酸化物系誘電体膜と非酸化物導体電極の界
面反応により界面部の電極の酸化が生じたりする。この
ように電極の酸化が生じると、電極の酸化物が誘電体の
場合には、これによる寄生キャパシタが直列に連がり、
本来のキャパシタの容量を低下させ、また、電極の酸化
物が導体の場合においても、界面反応が生じて電極が酸
化された場合には、酸化物系誘電体膜の絶縁耐圧の劣化
やリーク電流の増加を引起す等の問題があった。However, in the case of non-oxide conductor electrodes, oxidation of the electrode surface occurs due to the oxidizing atmosphere during the formation of the oxide-based dielectric thin film, or an interfacial reaction occurs between the oxide-based dielectric film and the non-oxide conductor electrode. Oxidation of the electrodes may occur. When electrode oxidation occurs in this way, if the electrode oxide is a dielectric, a parasitic capacitor due to this is connected in series,
In addition, even if the oxide of the electrode is a conductor, if an interfacial reaction occurs and the electrode is oxidized, the dielectric strength of the oxide dielectric film may deteriorate and leak current may decrease. There were problems such as an increase in
本発明の目的は、電極の酸化に伴なう容量の低下や絶縁
性の低下を引起さないキャパシタを具備した半導体装置
を提供することにある。An object of the present invention is to provide a semiconductor device equipped with a capacitor that does not cause a decrease in capacity or insulation due to oxidation of an electrode.
上記目的を達成するため、本発明の半導体装置は、半導
体装置に含まれるキャパシタの誘電体を酸化物系薄膜に
て構成し、該誘電体に接する少くとも一方の電極を酸化
物導体にて構成したものである。In order to achieve the above object, the semiconductor device of the present invention includes a capacitor included in the semiconductor device, in which a dielectric is made of an oxide-based thin film, and at least one electrode in contact with the dielectric is made of an oxide conductor. This is what I did.
本発明による半導体装置に含まれるキャパシタにおいて
は、酸化物系薄膜からなる誘電体と、酸化物導体からな
る電極とを有しているので、酸化物系誘電体薄膜形成時
やその後の工程における反応による電極の酸化を防止又
は半減させることかできる。Since the capacitor included in the semiconductor device according to the present invention has a dielectric made of an oxide-based thin film and an electrode made of an oxide conductor, reactions occur during formation of the oxide-based dielectric thin film and subsequent steps. It is possible to prevent or halve the oxidation of the electrode due to
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図〜第４図は本発明によるキャパシタの種々の実施
例の構造を示す断面模式図である。1 to 4 are schematic cross-sectional views showing the structures of various embodiments of the capacitor according to the present invention.
第１図に示した本発明の実施例１に係るキャパシタは、
ｐ型シリコン基板１１に設けられたｎ型拡散領域１２と
、基板１１上の絶縁層１３に設けられた開孔１３ａを通
じてｎ型拡散領域１２に接触する多結晶シリコン等の非
酸化物電極１４と、非酸化物電極１４上に形成された酸
化物系誘電体膜１５と、誘電体膜１５上に形成された酸
化物導電体層１６により形成されている。この構造にお
いては、酸化物系誘電体膜１５として、非酸化物電極１
４を構成する多結晶シリコンの熱酸化や気相堆積法等に
より形成される酸化シリコン膜、若しくは窒化シリコン
膜とその上に形成した酸化物薄膜（酸化シリコン、酸化
タンタル、チタン・ジルコニウム酸鉛）との２層膜を誘
電体に用いるのか適しているが、下部電極としての非酸
化物電極１４の表面が多少酸化されることも許容できれ
ば、誘電体膜１５として酸化タンタル膜やチタン・ジル
コニウム酸鉛等の高誘電率の堆積膜を用いることができ
る。The capacitor according to Example 1 of the present invention shown in FIG.
An n-type diffusion region 12 provided in a p-type silicon substrate 11, and a non-oxide electrode 14 made of polycrystalline silicon or the like that contacts the n-type diffusion region 12 through an opening 13a provided in an insulating layer 13 on the substrate 11. , an oxide-based dielectric film 15 formed on the non-oxide electrode 14, and an oxide conductor layer 16 formed on the dielectric film 15. In this structure, the non-oxide electrode 1 is used as the oxide-based dielectric film 15.
A silicon oxide film or a silicon nitride film formed by thermal oxidation of polycrystalline silicon constituting 4 or a vapor phase deposition method, or a silicon nitride film and an oxide thin film (silicon oxide, tantalum oxide, titanium/lead zirconate) formed thereon. It is suitable to use a two-layer film as the dielectric material, but if it is acceptable that the surface of the non-oxide electrode 14 as the lower electrode is slightly oxidized, a tantalum oxide film or a titanium/zirconate film as the dielectric film 15 is suitable. A deposited film with a high dielectric constant such as lead can be used.
第２図に示した実施例２におけるキャパシタの構造にお
いては、下部電極は多結晶シリコンからなる非酸化物電
極２４と、該を極２４上に形成したタングステンシリサ
イド等のシリサイドや窒化チタン等の窒化物や炭化物よ
りなるバリヤ層１７と、酸化物電極１８とからなる３層
構造のものが用いられる。この場合には誘電体層１５と
して、酸化シリコン、酸化タンタル、あるいはチタン酸
鉛等の酸化物薄膜を用いるのが適しているが窒化シリコ
ンと酸化物薄膜との２層構造を用いることも有効である
。In the structure of the capacitor in Example 2 shown in FIG. 2, the lower electrode includes a non-oxide electrode 24 made of polycrystalline silicon, and a silicide such as tungsten silicide or nitride such as titanium nitride formed on the electrode 24. A three-layer structure consisting of a barrier layer 17 made of metal or carbide and an oxide electrode 18 is used. In this case, it is suitable to use a thin film of oxide such as silicon oxide, tantalum oxide, or lead titanate as the dielectric layer 15, but it is also effective to use a two-layer structure of silicon nitride and a thin oxide film. be.
第３図に示した実施例３におけるキャパシタの構造にお
いては、下部電極は、実施例２における３層′！ｆ４造
の代りに、タングステンシリサイド等のシリサイドある
いは窒化チタン等の金属窒化物や炭化物よりなるバリヤ
層１７と、酸化物電極１８とからなる２層構造のものが
用いられている。In the structure of the capacitor in Example 3 shown in FIG. 3, the lower electrode has three layers'! Instead of the F4 structure, a two-layer structure consisting of a barrier layer 17 made of a silicide such as tungsten silicide, or a metal nitride or carbide such as titanium nitride, and an oxide electrode 18 is used.
第４図に示した実施例４におけるキャパシタの構造にお
いては、下部電極は、実施例２における３層構造の代り
に、酸化物電＠１５からなる単層構造のものか用いられ
ている。In the structure of the capacitor in Example 4 shown in FIG. 4, the lower electrode has a single layer structure made of oxide dielectric @15 instead of the three layer structure in Example 2.
上記実施例１〜４においては、いずれも上部電極として
単層ＭＩＪ造の酸化物電ｆ２１６を用いなが、該酸化物
電極１６上にシリサイド層、窒化物層、炭化物層、金属
層、あるいは多結晶シリコン層等を積層して用いること
は電極・配線の低抵抗化やさらに他の金属配線とのコン
タクトを形成する場合のコンタクト抵抗の低減に有効で
ある。In Examples 1 to 4 above, a single-layer MIJ oxide electrode f216 is used as the upper electrode, but a silicide layer, nitride layer, carbide layer, metal layer, or multilayer layer is formed on the oxide electrode 16. The use of laminated crystalline silicon layers and the like is effective in lowering the resistance of electrodes and interconnections, as well as in reducing the contact resistance when forming contacts with other metal interconnections.
次に、上記実施例で示した構造のキャパシタをＩ）−Ｒ
ＡＭに応用した実施例について第５図を用いて説明する
。スタック型キャパシタセル構造形成の標準的な方法を
用いて第５図（ａ）に示したようにキャパシタ形成直前
の構造を形成する。ここに、５１はｐ型シリコン基板、
５２はｎ型拡散領域（不純物ドープ層）、５３はゲート
電極・配線、５４は絶縁膜、５５はコンタクト孔である
。次に、第５図（ｂ）に示したように、多結晶シリコン
よりなる非酸化物電極５６、タングステンシリサイドよ
りなるバリヤ層５７、酸化ルテニウムよりなる酸化物下
部電極５８を順次積層形成する。Next, the capacitor having the structure shown in the above example is I)-R
An example applied to AM will be explained using FIG. 5. Using a standard method for forming a stacked capacitor cell structure, a structure immediately before capacitor formation is formed as shown in FIG. 5(a). Here, 51 is a p-type silicon substrate,
52 is an n-type diffusion region (impurity doped layer), 53 is a gate electrode/wiring, 54 is an insulating film, and 55 is a contact hole. Next, as shown in FIG. 5(b), a non-oxide electrode 56 made of polycrystalline silicon, a barrier layer 57 made of tungsten silicide, and an oxide lower electrode 58 made of ruthenium oxide are sequentially laminated.
これらの層の堆積には、標準的なＣＶＤ法やスパッタ法
を用い、また、パターン化には標準的なＲＩＥ法を用い
ることかできる。第５図（Ｃ）に示したようにＣＶＤ法
により酸化タンタル膜よりなる誘電体膜５９を形成する
。次に第５図（ｄ）に示したようにスパッタ法により酸
化ルテニウムよりなる上部型ｆ！６０を形成する。その
後は、標準的なスタック型キャパシタセル構造の形成方
法に従って配線形成等を行うことで、本発明の一実施例
としてのＤ−ＲＡＭを製作できる。These layers can be deposited using standard CVD or sputtering techniques, and patterned using standard RIE techniques. As shown in FIG. 5(C), a dielectric film 59 made of tantalum oxide film is formed by the CVD method. Next, as shown in FIG. 5(d), the upper mold f! is made of ruthenium oxide by sputtering. form 60. Thereafter, a D-RAM as an embodiment of the present invention can be manufactured by forming wiring and the like according to a standard method for forming a stacked capacitor cell structure.
以上説明したように本発明によれば、酸化物系誘電体を
有するキャパシタの電極の酸化に伴なう容量の低下や絶
縁性の低下を回避したキャパシタを有する半導体装置を
実現することができるという効果が得られる。As explained above, according to the present invention, it is possible to realize a semiconductor device having a capacitor that avoids a decrease in capacitance and a decrease in insulation properties caused by oxidation of the electrode of a capacitor having an oxide-based dielectric. Effects can be obtained.
第１図〜第４図は本発明の実施例におけるキャパシタを
示す断面図、第５図（ａ）〜（ｄ）は本発明の実施例２
に係るキャパシタを具備するダイナミックランダムアク
セスメモリのキャパシタ部の製造方法を工程順に示す断
面図である。
１１、５１・・・ｐ型シリコン基板
１２、５２・・・ｎ型拡散領域
１３、５４・・・絶縁膜 １４・・・非酸化物電
極１５、５９・・・酸化物系誘電体
１６、１８．１９．５８．６０・・・酸化物電極１７、
５７・・・バリヤ層 ５３・・・ゲート電極・配線
５５・・・コンタクト孔
第２図1 to 4 are cross-sectional views showing capacitors according to embodiments of the present invention, and FIGS. 5(a) to 5(d) are sectional views showing embodiment 2 of the invention
FIG. 3 is a cross-sectional view showing, in order of steps, a method for manufacturing a capacitor section of a dynamic random access memory including a capacitor according to the present invention. 11, 51... P-type silicon substrate 12, 52... N-type diffusion region 13, 54... Insulating film 14... Non-oxide electrode 15, 59... Oxide-based dielectric 16, 18 .19.58.60...Oxide electrode 17,
57...Barrier layer 53...Gate electrode/wiring 55...Contact hole Fig. 2
Claims (1)
物系薄膜にて構成し、該誘電体に接する少くとも一方の
電極を酸化物導体にて構成したことを特徴とする半導体
装置。(1) A semiconductor device characterized in that a dielectric of a capacitor included in the semiconductor device is made of an oxide-based thin film, and at least one electrode in contact with the dielectric is made of an oxide conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1247232A JPH03108752A (en) | 1989-09-22 | 1989-09-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1247232A JPH03108752A (en) | 1989-09-22 | 1989-09-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03108752A true JPH03108752A (en) | 1991-05-08 |
Family
ID=17160419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1247232A Pending JPH03108752A (en) | 1989-09-22 | 1989-09-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03108752A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09116115A (en) * | 1995-06-26 | 1997-05-02 | Hyundai Electron Ind Co Ltd | Manufacture of capacitor for semiconductor element |
| JPH10173154A (en) * | 1996-12-04 | 1998-06-26 | Samsung Electron Co Ltd | Capacitor of semiconductor storage device and its manufacturing method |
| JP2008311676A (en) * | 1995-02-13 | 2008-12-25 | Texas Instr Inc <Ti> | Method for forming semiconductor integrated circuit structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53100455A (en) * | 1977-02-15 | 1978-09-01 | Matsushita Electric Ind Co Ltd | Solid electrolytic capacitor |
| JPH01175294A (en) * | 1987-12-28 | 1989-07-11 | Matsushita Electric Ind Co Ltd | Circuit board |
| JPH03214717A (en) * | 1989-07-17 | 1991-09-19 | Natl Semiconductor Corp <Ns> | Electrode for electric ceramic oxide apparatus |
-
1989
- 1989-09-22 JP JP1247232A patent/JPH03108752A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53100455A (en) * | 1977-02-15 | 1978-09-01 | Matsushita Electric Ind Co Ltd | Solid electrolytic capacitor |
| JPH01175294A (en) * | 1987-12-28 | 1989-07-11 | Matsushita Electric Ind Co Ltd | Circuit board |
| JPH03214717A (en) * | 1989-07-17 | 1991-09-19 | Natl Semiconductor Corp <Ns> | Electrode for electric ceramic oxide apparatus |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008311676A (en) * | 1995-02-13 | 2008-12-25 | Texas Instr Inc <Ti> | Method for forming semiconductor integrated circuit structure |
| JPH09116115A (en) * | 1995-06-26 | 1997-05-02 | Hyundai Electron Ind Co Ltd | Manufacture of capacitor for semiconductor element |
| JPH10173154A (en) * | 1996-12-04 | 1998-06-26 | Samsung Electron Co Ltd | Capacitor of semiconductor storage device and its manufacturing method |
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