JPH04303989A - Thick film circuit board - Google Patents

Thick film circuit board

Info

Publication number
JPH04303989A
JPH04303989A JP9343791A JP9343791A JPH04303989A JP H04303989 A JPH04303989 A JP H04303989A JP 9343791 A JP9343791 A JP 9343791A JP 9343791 A JP9343791 A JP 9343791A JP H04303989 A JPH04303989 A JP H04303989A
Authority
JP
Japan
Prior art keywords
layer
paste
lower conductor
conductor layer
dam
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9343791A
Other languages
Japanese (ja)
Inventor
Katsuya Sato
克也 佐藤
Akihiro Wakabayashi
若林 昭博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Lighting and Technology Corp
Original Assignee
Toshiba Lighting and Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Lighting and Technology Corp filed Critical Toshiba Lighting and Technology Corp
Priority to JP9343791A priority Critical patent/JPH04303989A/en
Publication of JPH04303989A publication Critical patent/JPH04303989A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To remarkably reduce the printing area of a solder resist layer so as to make a pattern finer and improve the yield by forming both an upper conductor layer and dam layer of conductor paste made of the same material containing the same conductive material having low solder wettability. CONSTITUTION:Lower conductor layers 12a-12e are formed on the surface of an insulating substrate 11 and an insulator layer 13 is formed on the layer 12d. In addition, an upper conductor layer 15 the part of which is connected to the layers 12c and 13e is formed on the substrate 11 so that the layer 15 can cross the layer 13. A frame-like solder resist layer (dam layer) 16 is formed on the substrate 11 including the layers 12b and 12c. The upper conductor and dam layers 15 and 16 are constituted as printed layers by respectively printing conductive paste 17 or insulating paste which contains conductive substances and low solder wettability and baking the paste after printing.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は厚膜回路基板に関し、特
に印刷回路と面付けチップ部品等で構成される厚膜回路
基板に関わる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thick film circuit boards, and more particularly to thick film circuit boards comprised of printed circuits, surface-mounted chip components, and the like.

【0002】0002

【従来の技術】図2は、従来の厚膜回路基板の断面図を
示す。
2. Description of the Related Art FIG. 2 shows a cross-sectional view of a conventional thick film circuit board.

【0003】図中の1は、アルミナなどの絶縁基板であ
る。この絶縁基板1の表面には、下部導体層2が形成さ
れている。この下部導体層2は、例えば銀−パラジウム
系導体ペ−ストを印刷,焼成することにより形成される
。前記下部導体層2の一部上には、絶縁体層3が形成さ
れている。前記絶縁基板1上には、所定の下部導体層2
とオ−バ−ラップするように抵抗体層4が形成されてい
る。前記絶縁基板1上には、一部が前記下部導体層2の
一部とオ−バ−ラップするように上部導体層5が印刷に
より形成されている。前記下部導体層2の一部は接続パ
ッド2aとなっており、この接続パッド2aを除いた部
分には半田レジスト層6が設けられている。この半田レ
ジスト層6が存在しない前記接続パッド2a上には、半
田ペ−スト層7が印刷等により設けられている。ここで
、前記半田レジスト層6としては、通常ガラスペ−スト
や樹脂ペ−ストを使用している。前記半田ペ−スト層7
上には、チップ部品8が搭載されている。
Reference numeral 1 in the figure is an insulating substrate made of alumina or the like. A lower conductor layer 2 is formed on the surface of this insulating substrate 1. This lower conductor layer 2 is formed, for example, by printing and baking a silver-palladium based conductor paste. An insulator layer 3 is formed on a portion of the lower conductor layer 2 . A predetermined lower conductor layer 2 is provided on the insulating substrate 1.
A resistor layer 4 is formed so as to overlap with the resistor layer 4. An upper conductor layer 5 is formed on the insulating substrate 1 by printing so that a portion thereof overlaps with a portion of the lower conductor layer 2. A portion of the lower conductor layer 2 serves as a connection pad 2a, and a solder resist layer 6 is provided on the portion other than the connection pad 2a. On the connection pad 2a where the solder resist layer 6 does not exist, a solder paste layer 7 is provided by printing or the like. Here, as the solder resist layer 6, glass paste or resin paste is usually used. The solder paste layer 7
A chip component 8 is mounted on the top.

【0004】0004

【発明が解決しようとする課題】しかしながら、従来の
厚膜回路基板によれば、以下に述べる問題点を有してい
た。 (1) 半田レジスト層6の形成に際してパタ−ンファ
イン化が要求されているが、半田レジスト層6は印刷に
より形成するため、限界があり、歩留り低下の原因の一
つである。 (2) 半田レジスト層6は印刷面積が比較的広いこと
、及び形成条件が他の層と異なることから、コストアッ
プを招く。また、半田レジスト層6の形成条件が他の層
と異なるため、専用設備等が必要となり、やはりコスト
アップを招く。
[Problems to be Solved by the Invention] However, conventional thick film circuit boards have had the following problems. (1) Pattern refinement is required when forming the solder resist layer 6, but since the solder resist layer 6 is formed by printing, there are limitations and this is one of the causes of a decrease in yield. (2) Since the solder resist layer 6 has a relatively large printing area and its formation conditions are different from those of other layers, the cost increases. Furthermore, since the conditions for forming the solder resist layer 6 are different from those of other layers, special equipment is required, which also increases costs.

【0005】本発明は上記事情に鑑みてなされたもので
、半田レジスト層の印刷面積を従来と比べ大きく減少さ
せてパタ−ンファイン化を実現して歩留り向上を図ると
ともに、半田レジスト層の材料の減少,専用設備を不要
にしてコスト低減を図りうる厚膜回路基板を提供するこ
とを目的とする。
The present invention has been made in view of the above circumstances, and aims to significantly reduce the printing area of the solder resist layer compared to the conventional one, achieve pattern refinement, and improve yield. The purpose of the present invention is to provide a thick film circuit board that can reduce costs by eliminating the need for specialized equipment.

【0006】[0006]

【課題を解決するための手段】本発明は、絶縁基板と、
この絶縁基板上に形成された複数の下部導体層と、この
下部導体層の一部上に半田レジスト層を介して形成され
たチップ部品と、前記半田レジスト層の周囲の前記下部
導体層を含む前記絶縁基板上に形成されたダム層と、前
記下部導体層の一部上に絶縁体層を介して形成された上
部導体層を具備し、前上部導体層及び前記ダム層は、夫
々導電性材料を含む半田濡れ性の悪い導電性ペ−ストも
しくは絶縁ペ−ストを印刷,焼成することにより得られ
る印刷層であることを特徴とする厚膜回路基板である。
[Means for Solving the Problems] The present invention provides an insulating substrate;
It includes a plurality of lower conductor layers formed on the insulating substrate, a chip component formed on a part of the lower conductor layer via a solder resist layer, and the lower conductor layer around the solder resist layer. It comprises a dam layer formed on the insulating substrate and an upper conductor layer formed on a part of the lower conductor layer with an insulator layer interposed therebetween, and the front upper conductor layer and the dam layer are each electrically conductive. This is a thick film circuit board characterized by a printed layer obtained by printing and baking a conductive paste or insulating paste containing a material with poor solder wettability.

【0007】本発明において、絶縁基板の材料としては
、例えばアルミナなどのセラミックが挙げられる。
In the present invention, examples of the material of the insulating substrate include ceramics such as alumina.

【0008】本発明において、下部導体層の材料として
は、例えば銀−パラジウム系導電性材料等が挙げられる
In the present invention, examples of the material for the lower conductor layer include silver-palladium conductive materials.

【0009】本発明において、上部導体層及びダム層の
材料としては、銀−パラジウム系等の導電性材料が挙げ
られ、この導電性材料を含む導電性ペ−ストは半田濡れ
性が悪いことが必要である。
[0009] In the present invention, conductive materials such as silver-palladium may be used as the material for the upper conductor layer and the dam layer, and a conductive paste containing this conductive material may have poor solder wettability. is necessary.

【0010】0010

【作用】本発明においては、半田レジスト層を囲むダム
層と上部導体層は同じ材料を用いて作成され、濡れ性の
悪い導電性材料を含む濡れ性の悪い導体ペ−ストを所定
の位置に印刷した後、焼成,乾燥することにより形成さ
れる。こうした導体ペ−ストを用いることにより、半田
レジスト層(ダム層)の高さと共に接続パット部以外へ
の半田の流れが防止される。
[Operation] In the present invention, the dam layer surrounding the solder resist layer and the upper conductor layer are made of the same material, and a conductive paste with poor wettability containing a conductive material with poor wettability is applied to a predetermined position. It is formed by printing, baking and drying. Use of such a conductive paste increases the height of the solder resist layer (dam layer) and prevents solder from flowing to areas other than the connection pads.

【0011】[0011]

【実施例】図1は本発明の一実施例に係る厚膜回路基板
の断面図である。図中の11は、アルミナなどの絶縁基
板である。この絶縁基板11の表面には、下部導体層1
2(12a,12b,12c,12d,12e)が形成
されている。この下部導体層12は、例えば銀−パラジ
ウム系導体ペ−ストを印刷,焼成することにより形成さ
れる。前記下部導体層12d上には、絶縁体層13が絶
縁ペ−ストを印刷,焼成することにより形成されている
。前記絶縁基板11上には、下部導体層12a,12b
にまたぐように抵抗体層14が形成されている。前記絶
縁基板11上には、一部が前記下部導体層12c,12
eと接続して絶縁体層13をまたぐように上部導体層1
5が形成されている。前記下部導体層12b,12cを
含む前記絶縁基板11上には枠状の半田レジスト層(ダ
ム層)16が形成され、このダム層16の内側に半田ペ
−スト層17が形成されている。なお、この半田ペ−ス
ト17の接続する前記下部導体層部分がチップ部品用接
続パッドとなる。この半田ペ−スト層17には段差部が
形成され、この段差部に両端がまたがるようにチップ部
品18が搭載されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of a thick film circuit board according to an embodiment of the present invention. 11 in the figure is an insulating substrate made of alumina or the like. A lower conductor layer 1 is formed on the surface of this insulating substrate 11.
2 (12a, 12b, 12c, 12d, 12e) are formed. This lower conductor layer 12 is formed, for example, by printing and baking a silver-palladium based conductor paste. An insulating layer 13 is formed on the lower conductor layer 12d by printing and baking an insulating paste. On the insulating substrate 11 are lower conductor layers 12a and 12b.
A resistor layer 14 is formed so as to straddle the area. On the insulating substrate 11, a part of the lower conductor layers 12c, 12
upper conductor layer 1 so as to connect to e and straddle the insulator layer 13.
5 is formed. A frame-shaped solder resist layer (dam layer) 16 is formed on the insulating substrate 11 including the lower conductor layers 12b and 12c, and a solder paste layer 17 is formed inside this dam layer 16. Note that the portion of the lower conductor layer to which this solder paste 17 is connected becomes a connection pad for chip components. A step portion is formed in this solder paste layer 17, and a chip component 18 is mounted so that both ends thereof straddle this step portion.

【0012】上記構成の厚膜回路基板は、次のようにし
て形成する。まず、絶縁基板11の表面に例えば銀−パ
ラジウム系導体ペ−ストを印刷,焼成して、下部導体層
12a〜12eを形成する。つづいて、下部導体層12
d上に絶縁体ペ−ストを印刷,焼成して、絶縁体層13
を形成する。次に、前記下部導体層12dをまたぐよう
に抵抗体ペ−ストを印刷・乾燥する。ひきつづき、下部
導体層12a,12bのチップ部品用接続パッドに近接
した部分に、導体ペ−ストを印刷,乾燥させ抵抗体ペ−
ストと同時に焼成し、抵抗体層14,上部導体層15及
び枠状のダム層16を形成する。更に、ダム層16の枠
内のチップ部品用接続パッドに半田ペ−スト層17を印
刷等により形成し、その半田ペ−スト形成部がチップ部
品18などの電極となるようにチップ部品18を搭載し
、リフロ−半田つけ等により半田付けし、チップ部品1
8などと接続パッドを接続し、固定させて、厚膜回路基
板を製造する。なお、前記上部導体層印刷の際には、特
に半田濡れ性の悪い導体ペ−ストを使用し、半田レジス
トの高さと共に接続パッド部以外への半田の流れを防止
する。
The thick film circuit board having the above structure is formed as follows. First, a silver-palladium-based conductive paste, for example, is printed on the surface of the insulating substrate 11 and fired to form the lower conductive layers 12a to 12e. Subsequently, the lower conductor layer 12
An insulating paste is printed on d and baked to form an insulating layer 13.
form. Next, a resistor paste is printed and dried so as to straddle the lower conductor layer 12d. Subsequently, conductor paste is printed and dried on the lower conductor layers 12a and 12b in the vicinity of the chip component connection pads, and resistor paste is applied.
The resistor layer 14, the upper conductor layer 15, and the frame-shaped dam layer 16 are formed by firing at the same time as the firing. Furthermore, a solder paste layer 17 is formed on the chip component connection pad within the frame of the dam layer 16 by printing or the like, and the chip component 18 is attached so that the solder paste formed portion becomes the electrode of the chip component 18 or the like. Mounted and soldered using reflow soldering etc., chip part 1
A thick film circuit board is manufactured by connecting connection pads such as 8 and fixing them. When printing the upper conductor layer, a conductor paste with particularly poor solder wettability is used to increase the height of the solder resist and prevent solder from flowing to areas other than the connection pads.

【0013】しかして、上記実施例によれば、以下に述
べる利点を有する。 (1) 半田レジスト層(ダム層)16をチップ部品1
8が搭載される下部導体層12b,12cを含む絶縁基
板11上にのみ選択的に設けるため、従来の半田レジス
ト層と比較して、印刷面積が大きく減少し、パタ−ンの
ファイン化を実現できる。従って、歩留りが向上すると
ともに、作業効率が向上する。
[0013] According to the above embodiment, however, there are the following advantages. (1) Solder resist layer (dam layer) 16 is attached to chip component 1
Since it is selectively provided only on the insulating substrate 11 including the lower conductor layers 12b and 12c on which the solder resist layer 8 is mounted, the printing area is greatly reduced compared to a conventional solder resist layer, and a finer pattern is realized. can. Therefore, yield is improved and work efficiency is improved.

【0014】(2) ダム層16の印刷面積が減少した
ため、材料コストを低減できる。 (3) 上部導体層15とダム層16を同時に形成でき
るため、工数の削減を図ることができ、従来の設備を共
用化できる。
(2) Since the printing area of the dam layer 16 is reduced, material costs can be reduced. (3) Since the upper conductor layer 15 and the dam layer 16 can be formed at the same time, the number of man-hours can be reduced and conventional equipment can be shared.

【0015】なお、上記実施例では、導電性ペ−ストを
使用した印刷層を形成する場合について説明したが、下
部導体層を絶縁する絶縁体,ペ−ストを印刷焼成して形
成された印刷層を使用しても良い。
[0015] In the above embodiment, a case was explained in which a printed layer was formed using a conductive paste. Layers may also be used.

【0016】[0016]

【発明の効果】以上詳述した如く本発明によれば、上部
導体層と前記ダム層をともに同じ材料で半田濡れ性の悪
い導電性材料を含む導体ペ−ストにより形成することに
より、半田レジスト層の印刷面積を大きく減少させてパ
タ−ンファイン化を実現して歩留り向上を図るとともに
、半田レジスト層の材料の減少,専用設備を不要にして
コスト低減を図りうる厚膜回路基板を提供できる。
As described in detail above, according to the present invention, the upper conductor layer and the dam layer are both made of the same material and are made of a conductive paste containing a conductive material with poor solder wettability. It is possible to provide a thick film circuit board in which the printed area of the layer is greatly reduced to achieve finer patterns and yields are improved, and the cost can be reduced by reducing the amount of material used in the solder resist layer and eliminating the need for dedicated equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例に係る厚膜回路基板の断面図
FIG. 1 is a sectional view of a thick film circuit board according to an embodiment of the present invention.

【図2】従来の厚膜回路基板の断面図。FIG. 2 is a cross-sectional view of a conventional thick film circuit board.

【符号の説明】[Explanation of symbols]

11…絶縁基板、12a〜12e…下部導体層、13…
絶縁体層、14…抵抗体層、15…上部導体層、16…
半田レジスト層(ダム層)、17…半田ペ−スト層、1
8…チップ部品。
11... Insulating substrate, 12a to 12e... Lower conductor layer, 13...
Insulator layer, 14... Resistor layer, 15... Upper conductor layer, 16...
Solder resist layer (dam layer), 17...Solder paste layer, 1
8...Chip parts.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  絶縁基板と、この絶縁基板上に形成さ
れた複数の下部導体層と、この下部導体層の一部上に半
田レジスト層を介して形成されたチップ部品と、前記半
田レジスト層の周囲の前記下部導体層を含む前記絶縁基
板上に形成されたダム層と、前記下部導体層の一部上に
絶縁体層を介して形成された上部導体層を具備し、前上
部導体層及び前記ダム層は、夫々導電性材料を含む半田
濡れ性の悪い導電性ペ−ストもしくは絶縁ペ−ストを印
刷,焼成することにより得られる印刷層であることを特
徴とする厚膜回路基板。
1. An insulating substrate, a plurality of lower conductor layers formed on the insulating substrate, a chip component formed on a portion of the lower conductor layer with a solder resist layer interposed therebetween, and the solder resist layer. a dam layer formed on the insulating substrate including the lower conductor layer around the lower conductor layer, and an upper conductor layer formed on a part of the lower conductor layer via an insulator layer, and the front upper conductor layer and a thick film circuit board, wherein the dam layer is a printed layer obtained by printing and baking a conductive paste or an insulating paste containing a conductive material and having poor solder wettability, respectively.
JP9343791A 1991-03-30 1991-03-30 Thick film circuit board Pending JPH04303989A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9343791A JPH04303989A (en) 1991-03-30 1991-03-30 Thick film circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9343791A JPH04303989A (en) 1991-03-30 1991-03-30 Thick film circuit board

Publications (1)

Publication Number Publication Date
JPH04303989A true JPH04303989A (en) 1992-10-27

Family

ID=14082296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9343791A Pending JPH04303989A (en) 1991-03-30 1991-03-30 Thick film circuit board

Country Status (1)

Country Link
JP (1) JPH04303989A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1004651C2 (en) * 1996-11-29 1998-06-03 Nedcard Method for encapsulating a chip on a support.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1004651C2 (en) * 1996-11-29 1998-06-03 Nedcard Method for encapsulating a chip on a support.
WO1998023427A1 (en) * 1996-11-29 1998-06-04 Nedcard Method for encapsulating a chip on a carrier

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