JPH05218653A - Ceramic multilayer circuit board - Google Patents
Ceramic multilayer circuit boardInfo
- Publication number
- JPH05218653A JPH05218653A JP4016661A JP1666192A JPH05218653A JP H05218653 A JPH05218653 A JP H05218653A JP 4016661 A JP4016661 A JP 4016661A JP 1666192 A JP1666192 A JP 1666192A JP H05218653 A JPH05218653 A JP H05218653A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- ceramic multilayer
- printed wiring
- multilayer circuit
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はセラミック多層回路基
板、より詳細には小型電気、通信機器に搭載されるハイ
ブリッドＩＣ等に使用されるセラミック多層回路基板に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic multi-layer circuit board, and more particularly to a ceramic multi-layer circuit board used for a hybrid IC or the like mounted on a small electric or communication device.
【０００２】[0002]
【従来の技術】近年の電子部品における軽薄短小化の流
れはセラミック多層回路基板の分野においても例外では
なく、薄板化、小型化が要求されている。2. Description of the Related Art The recent trend toward lighter, thinner, shorter and smaller electronic components is no exception in the field of ceramic multilayer circuit boards, and there is a demand for thinning and miniaturization.
【０００３】従来のセラミック多層回路基板の一例を図
５に示す。セラミック多層回路基板２１はセラミックか
らなる印刷配線層２２、２３、２４、２５が積層されて
構成され、印刷配線層２５の裏面２５ａにはセラミック
多層回路基板２１を他の回路基板に電気的に接続するた
めの端子（図示せず）が形成されている。セラミック多
層回路基板２１の側面２１ａには貫通溝２７が形成さ
れ、この貫通溝２７部分は電極導体により被覆されてい
る。また、印刷配線層２２の上面である部品搭載面２２
ａには搭載される電子部品５０を電気的に接続するため
の回路パターン２２ｂが形成されている。FIG. 5 shows an example of a conventional ceramic multilayer circuit board. The ceramic multilayer circuit board 21 is formed by stacking printed wiring layers 22, 23, 24, 25 made of ceramics, and the back surface 25a of the printed wiring layer 25 electrically connects the ceramic multilayer circuit board 21 to another circuit board. Terminals (not shown) for forming are formed. A through groove 27 is formed on the side surface 21a of the ceramic multilayer circuit board 21, and this through groove 27 portion is covered with an electrode conductor. In addition, the component mounting surface 22 that is the upper surface of the printed wiring layer 22.
A circuit pattern 22b for electrically connecting the mounted electronic component 50 is formed on a.
【０００４】通常この種の多層回路基板においては、電
子部品を搭載する側の面積が印刷配線層の内部配線、ス
ルホールが占有する面積よりも大きく、基板の形状寸法
を決める大きな要因となっている。Generally, in this type of multilayer circuit board, the area on the side where electronic components are mounted is larger than the area occupied by the internal wiring and through holes of the printed wiring layer, which is a major factor in determining the shape and size of the board. ..
【０００５】また図６は別の従来例を示したものであ
り、印刷配線層３２、３３、３４、３５が積層されてセ
ラミック多層回路基板３１が構成されており、印刷配線
層３２の上面が部品搭載面３２ａとなっており、この部
品搭載面３２ａに電子部品５０を電気的に接続するため
の回路パターン３２ｂが形成されている。また、印刷配
線層３５の裏面３５ａには図５と同様にセラミック多層
回路基板３１を他の回路基板に電気的に接続するための
端子（図示せず）が形成されている。一方、セラミック
多層回路基板３１の側面３１ａに貫通溝２７は形成され
ておらず、側面３１ａに直接的に電極３６が形成されて
いる。FIG. 6 shows another conventional example, in which printed wiring layers 32, 33, 34 and 35 are laminated to form a ceramic multilayer circuit board 31, and the upper surface of the printed wiring layer 32 is The component mounting surface 32a is formed, and a circuit pattern 32b for electrically connecting the electronic component 50 is formed on the component mounting surface 32a. Further, on the back surface 35a of the printed wiring layer 35, terminals (not shown) for electrically connecting the ceramic multilayer circuit board 31 to another circuit board are formed as in FIG. On the other hand, the through groove 27 is not formed on the side surface 31a of the ceramic multilayer circuit board 31, and the electrode 36 is directly formed on the side surface 31a.
【０００６】[0006]
【発明が解決しようとする課題】図５に示した従来例の
場合、通常、部品搭載面２２ａの大きさが縦１２ｍｍ、
横２０ｍｍ程度であるのに対し、貫通溝２７の直径が１
ｍｍ程度あり、この貫通溝２７の分だけ部品搭載面２２
ａに電子部品５０を搭載できる面積が約１割小さくな
る。このことがセラミック多層回路基板２１のさらなる
小型化を図る上での大きな障害となっていた。In the case of the conventional example shown in FIG. 5, the size of the component mounting surface 22a is normally 12 mm in the vertical direction,
While the width is about 20 mm, the diameter of the through groove 27 is 1
It is about mm, and the component mounting surface 22 is equivalent to the through groove 27.
The area where the electronic component 50 can be mounted on a is reduced by about 10%. This has been a major obstacle to further miniaturization of the ceramic multilayer circuit board 21.
【０００７】また、図６に示した従来例の場合、図７に
示すような複数個どりの親基板４０の状態では、各印刷
配線層３２、３３、３４、３５の側面に電極３６を形成
することができず、前記親基板４０を分割した後のそれ
ぞれの印刷配線層（子基板）３２、３３、３４、３５の
側面に電極３６を設ける必要があり、コストが高くなる
という課題があった。さらにセラミック多層回路基板３
１を他の回路基板の電極パターンにハンダ付けする際、
ハンダの前記端子への周り込み具合を確認することがで
きないという課題もあった。Further, in the case of the conventional example shown in FIG. 6, electrodes 36 are formed on the side surfaces of each printed wiring layer 32, 33, 34, 35 in the state of a plurality of parent substrates 40 as shown in FIG. However, since it is necessary to provide electrodes 36 on the side surfaces of the respective printed wiring layers (child boards) 32, 33, 34, 35 after the parent board 40 is divided, there is a problem that the cost becomes high. It was Further ceramic multilayer circuit board 3
When soldering 1 to the electrode pattern of another circuit board,
There is also a problem that it is not possible to confirm the degree of the solder around the terminal.
【０００８】本発明はこのような課題に鑑み発明された
ものであって、小型化を図ることができ、しかもコスト
を低く抑えることができ、さらには他の回路基板にハン
ダ付けする際のハンダの端子への周り込み具合を容易に
確認することができるセラミック多層回路基板を提供す
ることを目的としている。The present invention has been invented in view of the above problems, and it is possible to achieve downsizing, cost reduction, and soldering when soldering to another circuit board. It is an object of the present invention to provide a ceramic multi-layer circuit board in which it is possible to easily check the surrounding condition of the terminal.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するため
に本発明に係るセラミック多層回路基板は、表面には電
子部品を電気的に接続するための回路パターンが形成さ
れ、かつ、裏面には他の回路基板に電気的に接続するた
めの端子が形成されたセラミック多層回路基板におい
て、前記セラミック多層回路基板の側面に溝が基板裏面
から基板中間層まで形成され、基板表面の前記回路パタ
ーンと前記基板中間層とはスルーホールを介して電気的
に接続されていることを特徴としている。In order to achieve the above object, a ceramic multilayer circuit board according to the present invention is provided with a circuit pattern for electrically connecting electronic parts on the front surface and a back surface on the back surface. In a ceramic multilayer circuit board on which terminals for electrically connecting to another circuit board are formed, a groove is formed on the side surface of the ceramic multilayer circuit board from the board back surface to the board intermediate layer, and the circuit pattern on the board surface is formed. It is characterized in that it is electrically connected to the substrate intermediate layer through a through hole.
【００１０】[0010]
【作用】上記構成によれば、前記セラミック多層回路基
板の側面に溝が基板裏面から基板中間層まで形成され、
基板の最上層には該溝は形成されていない。基板表面の
前記回路パターンと前記基板中間層とはスルーホールを
介して電気的に接続されており、前記基板表面の部品搭
載面には前記スルーホールによる孔が存在するが、該ス
ルホールは前記回路パターン部分に形成され、部品搭載
面積を小さくすることはない。また、前記セラミック多
層回路基板の側面に溝が基板中間層までは形成されてお
り、基板側面に形成される電極は各印刷配線層に分割さ
れる前の親基板の状態で形成される。さらには前記端子
への半田の周り込み具合は前記溝の部分で確認される。According to the above structure, the grooves are formed on the side surface of the ceramic multilayer circuit board from the back surface of the board to the board intermediate layer,
The groove is not formed in the uppermost layer of the substrate. The circuit pattern on the board surface and the board intermediate layer are electrically connected to each other through a through hole, and the through hole has a hole on the component mounting surface of the board surface. It is formed in the pattern portion and does not reduce the component mounting area. Further, a groove is formed on the side surface of the ceramic multilayer circuit board up to the intermediate layer of the board, and the electrodes formed on the side surface of the board are formed in the state of the parent board before being divided into each printed wiring layer. Furthermore, the degree of the solder surrounding the terminal is confirmed in the groove portion.
【００１１】[0011]
【実施例】以下、本発明に係るセラミック多層回路基板
の実施例を図面に基づいて説明する。なお、従来例と同
一機能を有する構成部品については同一符合を付するこ
ととする。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a ceramic multilayer circuit board according to the present invention will be described below with reference to the drawings. The components having the same functions as those of the conventional example are designated by the same reference numerals.
【００１２】図１は本実施例におけるセラミック多層回
路基板１１を示した模式的斜視図であり、図２はセラミ
ック多層回路基板１１の裏面図であり、図３はセラミッ
ク多層回路基板１１の模式的断面図である。図中１１は
セラミック多層回路基板１１を示しており、セラミック
多層回路基板１１はセラミックからなる印刷配線層１
２、１３、１４、１５が積層されて構成されている。印
刷配線層１２、１３、１４、１５にはそれぞれ複数個の
スルーホール１６（径０．２〜０．３ｍｍ）が形成さ
れ、印刷配線層１４、１５の側面には平面視半円形状の
溝１７が複数個形成され、これらスルーホール１６およ
び溝１７は導電性材料で被覆されている。また印刷配線
層１５の裏面１５ａの周縁部には他の回路基板に電気的
に接続するための溝状の端子１８が複数個形成されてい
る。なお、溝１７の形状は製造工程上、半円形状のもの
が最も簡易であるが、その他に長方形または楕円形状の
ものも可能である。FIG. 1 is a schematic perspective view showing a ceramic multilayer circuit board 11 in this embodiment, FIG. 2 is a rear view of the ceramic multilayer circuit board 11, and FIG. 3 is a schematic view of the ceramic multilayer circuit board 11. FIG. In the figure, reference numeral 11 denotes a ceramic multilayer circuit board 11. The ceramic multilayer circuit board 11 is a printed wiring layer 1 made of ceramic.
It is configured by laminating 2, 13, 14, and 15. A plurality of through holes 16 (diameter 0.2 to 0.3 mm) are formed in each of the printed wiring layers 12, 13, 14, and 15, and the side surface of each of the printed wiring layers 14 and 15 has a semicircular groove in plan view. A plurality of 17 are formed, and the through holes 16 and the grooves 17 are covered with a conductive material. Further, a plurality of groove-shaped terminals 18 for electrically connecting to another circuit board are formed on the peripheral portion of the back surface 15a of the printed wiring layer 15. The shape of the groove 17 is the simplest in the manufacturing process, but it may be rectangular or elliptical.
【００１３】セラミック多層回路基板１１は下記のよう
にして製造される。まず、Ａｌ2 Ｏ3 を５０重量部、Ｓ
ｉＯ2 、ＣａＯ、ムライトを５０重量部の割合で配合
し、ポットミルで２４時間湿式混合する。次に混合した
材料を乾燥させて、粉砕した後、この粉末にバインダ、
可塑剤および溶剤を混合する。混合して得られたスラリ
ーをドクターブレード法によって薄板化し、グリーンシ
ートを形成する。つぎに、印刷配線層１２、１３、１
４、１５には銀ペーストを用いて印刷することにより配
線パターンを形成し、また印刷配線層１２、１３、１
４、１５を電気的に接続するために、スルーホール１６
を配線パターンのランド部に同じく銀ペーストを塗布し
て形成する。この後印刷配線層１４、１５の側面には平
面視半円形状の溝１７を複数個形成し、次に印刷配線層
１２、１３、１４、１５を積層して加圧成形し、溝１７
に銀パラジウムを塗布した上で焼成を行うことによりセ
ラミック多層回路基板１１を作製する。The ceramic multilayer circuit board 11 is manufactured as follows. First, 50 parts by weight of Al 2 O 3 and S
50 parts by weight of iO 2 , CaO and mullite are mixed and wet-mixed in a pot mill for 24 hours. Next, the mixed material is dried, crushed, and then a binder is added to the powder.
Mix the plasticizer and solvent. The slurry obtained by mixing is thinned by a doctor blade method to form a green sheet. Next, the printed wiring layers 12, 13, 1
Wiring patterns are formed on the printed wiring layers 4, 15 by printing with silver paste.
Through holes 16 for electrically connecting 4, 15
Is similarly formed by applying silver paste to the land portion of the wiring pattern. After that, a plurality of grooves 17 having a semicircular shape in plan view are formed on the side surfaces of the printed wiring layers 14 and 15, and then the printed wiring layers 12, 13, 14 and 15 are laminated and pressure-molded to form the grooves 17
The ceramic multilayer circuit board 11 is manufactured by applying silver palladium on the substrate and firing it.
【００１４】このようにして作製されたセラミック多層
回路基板１１の部品搭載面１２ａにコンデンサ、抵抗、
ＩＣなどの電子部品５０がハンダ付けにより搭載され
る。On the component mounting surface 12a of the ceramic multilayer circuit board 11 thus manufactured, a capacitor, a resistor,
An electronic component 50 such as an IC is mounted by soldering.
【００１５】図４は本実施例に係るセラミック多層回路
基板１１を他のプリント配線基板１９に接続した場合を
示しており、端子１８をプリント配線基板１９に構成さ
れた配線パターン１０にハンダ２０を用いて接続してい
る。FIG. 4 shows the case where the ceramic multilayer circuit board 11 according to this embodiment is connected to another printed wiring board 19, and the terminals 18 are provided with solder 20 on the wiring pattern 10 formed on the printed wiring board 19. Are connected using.
【００１６】上記セラミック多層回路基板１１にあって
は電気的には部品搭載面１２ａ上の電子部品５０と印刷
配線層１３、１４、１５の配線パターン及び端子１８と
を接続する形でスルーホール１６及び溝１７が形成され
ている。そして、スルーホール１６が部品搭載面１２ａ
上の配線パターン１２ｂにおけるランド部に形成されて
おり、またスルーホール１６の径は０．２〜０．３ｍｍ
と非常に小さいため、部品搭載面１２ａにおける実質的
な部品搭載面積を狭めることはない。従って、図５にお
ける従来のセラミック多層回路基板２１の側面に１ｍｍ
程度と大きな直径の貫通溝２７が形成された構造に較
べ、実際の部品搭載面積を大きくとることができ、セラ
ミック多層回路基板１１のさらなる小型化を図ることが
できる。In the ceramic multilayer circuit board 11, the through hole 16 is electrically connected to the electronic component 50 on the component mounting surface 12a and the wiring patterns of the printed wiring layers 13, 14 and 15 and the terminal 18. And the groove 17 is formed. The through hole 16 is the component mounting surface 12a.
It is formed in the land portion of the upper wiring pattern 12b, and the diameter of the through hole 16 is 0.2 to 0.3 mm.
Since it is very small, the substantial component mounting area on the component mounting surface 12a is not narrowed. Therefore, the side surface of the conventional ceramic multilayer circuit board 21 in FIG.
Compared with the structure in which the through groove 27 having a large diameter and a large diameter is formed, the actual component mounting area can be increased, and the ceramic multilayer circuit board 11 can be further downsized.
【００１７】また、本実施例に係るセラミック多層回路
基板１１にあっては、各印刷配線層１２、１３、１４、
１５に分割する前の親基板の状態で、スルーホール１６
や溝１７を形成することができ、図６、図７に示したよ
うに従来のセラミック多層回路基板３１のように各印刷
配線層３２、３３、３４、３５に分割した後に、それぞ
れの印刷配線層３２、３３、３４、３５（子基板）の側
面に電極を設ける必要がなく、コストアップを招くこと
もない。さらには他のプリント配線基板１９にハンダ付
けするときハンダ２０の端子１８への周り込み具合を容
易に確認することができる。In the ceramic multilayer circuit board 11 according to this embodiment, the printed wiring layers 12, 13, 14,
In the state of the parent board before dividing into 15, the through hole 16
The grooves 17 can be formed, and the printed wiring layers 32, 33, 34, and 35 are divided into the printed wiring layers 32, 33, 34, and 35 like the conventional ceramic multilayer circuit board 31 as shown in FIGS. It is not necessary to provide electrodes on the side surfaces of the layers 32, 33, 34, 35 (child substrates), and the cost does not increase. Furthermore, when soldering to another printed wiring board 19, it is possible to easily confirm how the solder 20 surrounds the terminal 18.
【００１８】さらに本実施例では図３に示したように印
刷配線層１２、１３、１４、１５のすべてにスルホール
１６が形成され、かつ端子１８と溝１７とで形成される
電極がスルホール１６により他の印刷配線層と接続され
ているが、別の実施例では、印刷配線層１４、１５にス
ルホール１６が形成されていなくても差し支えない。な
お、上記実施例ではグリーンシートの側面に溝１７を形
成した印刷配線基板１４、１５を２枚重ね、その上に切
り欠きのない印刷配線層１２、１３を２枚重ねる構成を
とっている。しかし、別の実施例ではグリーンシートの
側面に溝１７を形成したもの及び切り欠きのないグリー
ンシートは共に少なくとも１枚あれば上記実施例の場合
と同様の効果を得ることができる。Further, in this embodiment, as shown in FIG. 3, through holes 16 are formed in all of the printed wiring layers 12, 13, 14, 15 and the electrodes formed by the terminals 18 and the grooves 17 are formed by the through holes 16. Although it is connected to another printed wiring layer, in another embodiment, the through hole 16 may not be formed in the printed wiring layers 14 and 15. In the above-described embodiment, two printed wiring boards 14 and 15 each having a groove 17 formed on the side surface of the green sheet are stacked, and two printed wiring layers 12 and 13 having no cutout are stacked thereon. However, in another embodiment, the same effect as in the above embodiment can be obtained if there is at least one green sheet in which the groove 17 is formed on the side surface and one notch-free green sheet.
【００１９】また、上記実施例では配線パターンを形成
するのに銀ペーストが用いられているが、配線パターン
形成のためのペーストは銀ペーストに限定されるもので
はなく、別の実施例では銅やタングステン等のペースト
を用いても差し支えない。Further, although the silver paste is used for forming the wiring pattern in the above-mentioned embodiment, the paste for forming the wiring pattern is not limited to the silver paste, and copper or copper is used in another embodiment. It does not matter if a paste such as tungsten is used.
【００２０】[0020]
【発明の効果】以上詳述したように本発明に係るセラミ
ック多層回路基板にあっては、表面には電子部品を電気
的に接続するための回路パターンが形成され、かつ裏面
には他の回路基板に電気的に接続するための端子が形成
されたセラミック多層回路基板において、前記セラミッ
ク多層回路基板の側面に溝が基板裏面から基板中間層ま
で形成され、基板表面の前記回路パターンと前記基板中
間層とはスルーホールを介して電気的に接続されてい
る。該スルーホールは前記回路パターンのランド部に形
成されることから、従来の印刷配線層が積層された基板
の側面に、貫通溝（径は通常１ｍｍ程度）が形成された
構造に較べ、実際の部品搭載面積を大きくとることがで
き、さらなる小型化を図ることができる。また、分割す
る前の親基板の状態で前記スルーホールや基板側面に前
記溝を形成することができ、コストアップを招くことも
ない。さらには他のプリント配線基板にハンダ付けする
とき、ハンダの前記端子への周り込み具合を容易に確認
することができる。As described above in detail, in the ceramic multilayer circuit board according to the present invention, the circuit pattern for electrically connecting the electronic parts is formed on the front surface and the other circuit is formed on the back surface. In a ceramic multi-layer circuit board having terminals for electrically connecting to the board, grooves are formed on a side surface of the ceramic multi-layer circuit board from a back surface of the board to a board intermediate layer, and the circuit pattern on the board surface and the board intermediate. The layers are electrically connected through the through holes. Since the through hole is formed in the land portion of the circuit pattern, compared with the conventional structure in which the through groove (diameter is usually about 1 mm) is formed on the side surface of the substrate on which the printed wiring layer is laminated, The component mounting area can be increased, and the size can be further reduced. Further, the groove can be formed in the through hole or the side surface of the substrate in the state of the parent substrate before the division, which does not increase the cost. Furthermore, when soldering to another printed wiring board, it is possible to easily confirm the degree of surrounding of the solder into the terminals.
【図１】本発明に係るセラミック多層回路基板の実施例
を示す模式的斜視図である。FIG. 1 is a schematic perspective view showing an embodiment of a ceramic multilayer circuit board according to the present invention.
【図２】実施例に係るセラミック多層回路基板を示す図
である。FIG. 2 is a diagram showing a ceramic multilayer circuit board according to an example.
【図３】実施例に係るセラミック多層回路基板を示す模
式的断面図である。FIG. 3 is a schematic cross-sectional view showing a ceramic multilayer circuit board according to an example.
【図４】実施例に係るセラミック多層回路基板を別の他
のプリント配線基板にハンダ付けした状態を示す概略斜
視図である。FIG. 4 is a schematic perspective view showing a state in which the ceramic multilayer circuit board according to the embodiment is soldered to another printed wiring board.
【図５】従来のセラミック多層回路基板を示す模式的斜
視図である。FIG. 5 is a schematic perspective view showing a conventional ceramic multilayer circuit board.
【図６】別の従来例を示すセラミック多層回路基板の模
式的斜視図である。FIG. 6 is a schematic perspective view of a ceramic multilayer circuit board showing another conventional example.
【図７】図６における従来のセラミックス多層回路基板
の分割前の状態を示す平面図である。FIG. 7 is a plan view showing a state before division of the conventional ceramic multilayer circuit board shown in FIG.
１２ａ 部品搭載面 １５ａ 裏面 １６ スルーホール １７ 溝 １８ 端子 12a Component mounting surface 15a Rear surface 16 Through hole 17 Groove 18 Terminal
Claims (1)
めの回路パターンが形成され、かつ、裏面には他の回路
基板に電気的に接続するための端子が形成されたセラミ
ック多層回路基板において、前記セラミック多層回路基
板の側面に溝が基板裏面から基板中間層まで形成され、
基板表面の前記回路パターンと前記基板中間層とはスル
ーホールを介して電気的に接続されていることを特徴と
するセラミック多層回路基板。1. A ceramic multilayer circuit board having a circuit pattern for electrically connecting electronic components formed on a front surface thereof, and a terminal for electrically connecting another circuit board formed on a rear surface thereof. In, a groove is formed on the side surface of the ceramic multilayer circuit board from the substrate back surface to the substrate intermediate layer,
A ceramic multilayer circuit board, wherein the circuit pattern on the surface of the board and the board intermediate layer are electrically connected to each other through a through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4016661A JPH05218653A (en) | 1992-01-31 | 1992-01-31 | Ceramic multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4016661A JPH05218653A (en) | 1992-01-31 | 1992-01-31 | Ceramic multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05218653A true JPH05218653A (en) | 1993-08-27 |
Family
ID=11922522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4016661A Pending JPH05218653A (en) | 1992-01-31 | 1992-01-31 | Ceramic multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05218653A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07221462A (en) * | 1994-02-03 | 1995-08-18 | Murata Mfg Co Ltd | Composite circuit part |
| JPH10270819A (en) * | 1997-03-28 | 1998-10-09 | Ngk Spark Plug Co Ltd | Surface mounting electronic part and its manufacture |
| JP2000340698A (en) * | 1999-06-01 | 2000-12-08 | New Japan Radio Co Ltd | Substrate for leadless chip carrier and leadless chip carrier |
| JP2002164658A (en) * | 2000-11-29 | 2002-06-07 | Sharp Corp | Module board |
| JP2003008239A (en) * | 2001-06-21 | 2003-01-10 | Ibiden Co Ltd | Multilayer printed wiring board |
| GB2395605A (en) * | 2002-11-25 | 2004-05-26 | Samsung Electro Mech | Multilayer ceramic substrate with internal connection part wider than external terminal |
| JP2004342930A (en) * | 2003-05-16 | 2004-12-02 | Hitachi Aic Inc | Multilayer substrate having non-through conduction hole |
| JP2007109851A (en) * | 2005-10-13 | 2007-04-26 | Citizen Electronics Co Ltd | Photo interrupter |
| EP2015360A3 (en) * | 2000-07-06 | 2011-03-02 | Murata Manufacturing Co. Ltd. | Electronic component with side contacts |
| WO2018021209A1 (en) * | 2016-07-28 | 2018-02-01 | 京セラ株式会社 | Substrate for mounting semiconductor element and semiconductor device |
-
1992
- 1992-01-31 JP JP4016661A patent/JPH05218653A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07221462A (en) * | 1994-02-03 | 1995-08-18 | Murata Mfg Co Ltd | Composite circuit part |
| JPH10270819A (en) * | 1997-03-28 | 1998-10-09 | Ngk Spark Plug Co Ltd | Surface mounting electronic part and its manufacture |
| JP2000340698A (en) * | 1999-06-01 | 2000-12-08 | New Japan Radio Co Ltd | Substrate for leadless chip carrier and leadless chip carrier |
| EP2015360A3 (en) * | 2000-07-06 | 2011-03-02 | Murata Manufacturing Co. Ltd. | Electronic component with side contacts |
| JP2002164658A (en) * | 2000-11-29 | 2002-06-07 | Sharp Corp | Module board |
| JP2003008239A (en) * | 2001-06-21 | 2003-01-10 | Ibiden Co Ltd | Multilayer printed wiring board |
| US6987315B2 (en) | 2002-11-25 | 2006-01-17 | Samsung Electro-Mechanics Co., Ltd. | Ceramic multilayer substrate |
| GB2395605B (en) * | 2002-11-25 | 2005-11-16 | Samsung Electro Mech | Ceramic multilayer substrate and method for manufacturing the same |
| GB2395605A (en) * | 2002-11-25 | 2004-05-26 | Samsung Electro Mech | Multilayer ceramic substrate with internal connection part wider than external terminal |
| JP2004342930A (en) * | 2003-05-16 | 2004-12-02 | Hitachi Aic Inc | Multilayer substrate having non-through conduction hole |
| JP2007109851A (en) * | 2005-10-13 | 2007-04-26 | Citizen Electronics Co Ltd | Photo interrupter |
| WO2018021209A1 (en) * | 2016-07-28 | 2018-02-01 | 京セラ株式会社 | Substrate for mounting semiconductor element and semiconductor device |
| CN109478537A (en) * | 2016-07-28 | 2019-03-15 | 京瓷株式会社 | Semiconductor element mounting substrate and semiconductor device |
| JPWO2018021209A1 (en) * | 2016-07-28 | 2019-05-09 | 京セラ株式会社 | Semiconductor device mounting substrate and semiconductor device |
| EP3493252A4 (en) * | 2016-07-28 | 2020-04-15 | KYOCERA Corporation | Substrate for mounting semiconductor element and semiconductor device |
| US10777493B2 (en) | 2016-07-28 | 2020-09-15 | Kyocera Corporation | Semiconductor device mounting board and semiconductor package |
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