JP2004342930A - Multilayer substrate having non-through conduction hole - Google Patents

Multilayer substrate having non-through conduction hole Download PDF

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Publication number
JP2004342930A
JP2004342930A JP2003139327A JP2003139327A JP2004342930A JP 2004342930 A JP2004342930 A JP 2004342930A JP 2003139327 A JP2003139327 A JP 2003139327A JP 2003139327 A JP2003139327 A JP 2003139327A JP 2004342930 A JP2004342930 A JP 2004342930A
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Japan
Prior art keywords
wiring board
hole
blind via
board
electronic component
Prior art date
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JP2003139327A
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Japanese (ja)
Inventor
Satoshi Isoda
聡 磯田
Masayuki Sakurai
正幸 桜井
Ryoji Sugiura
良治 杉浦
Hiroyoshi Yokoyama
博義 横山
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Lincstech Circuit Co Ltd
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Hitachi AIC Inc
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Priority to JP2003139327A priority Critical patent/JP2004342930A/en
Publication of JP2004342930A publication Critical patent/JP2004342930A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To make realizable a small and high-density mold chip having an end electrode which exhibits highly reliable electrical connection and solder joint, even in a condition where a member for preventing entry of sealing resin into a through hole is stuck onto an upper surface side of the through hole. <P>SOLUTION: A circuit board provided with the non-through conduction hole for an end electrode on a dividing and cutting line for dicing comprises an upper circuit board having a part-connecting land for mounting an electronic part or an electronic part element thereon, a second blind via (B2) of a lower circuit board which is disposed on the dividing and cutting line, and a first blind via (B1) for electrically connecting the part-connecting land of the upper circuit board and the second blind via (B2) of the lower circuit board. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、プリント配線板に関するもので、特に端面電極を形成するモ−ルドチップ部品のベ−ス基板となる多層基板に関するものである。
【0002】
【従来の技術】
従来は基板に端面電極を形成する場合、プリント配線板の外形側面の近傍に一直線上に貫通スルーホール穴を設け、貫通スルーホール穴のほぼ中心線上で分割切断して分割した貫通スルーホール穴の内部が半円筒状で外部に露呈した端面電極を形成する。
基板に半導体集積回路素子、電子部品素子、電子部品を実装し、その後基板の配線パタ−ンや半導体集積回路素子、電子部品素子、電子部品を樹脂で樹脂モ−ルドして樹脂封止をし端面電極を有するモ−ルドチップ部品とするには、貫通スルーホール穴の内部に封止樹脂が侵入しないように貫通スルーホール穴の上面側に樹脂の侵入を阻止する部材(フィルム、テ−プ、基材など)を設けなければならない。
【0003】その一例として、特開平10−65298号公報に開示されている端面スルーホール配線板がある。
これは、スルーホール穴の一方の端縁部は開孔し、他方の端縁部は外層導体で閉鎖している非貫通導通スルーホール穴を形成した端面スルーホール配線板である。つまり、封止する樹脂の侵入を阻止する部材として外層導体を利用して貫通導通穴の上面を外層導体で塞いだものである。
この非貫通導通スルーホール穴の外層導体は、通常0.05mm以下の薄い金属膜であるため樹脂で封止する圧力が高いトランスファモ−ルド法では、高い圧力によって非貫通導通穴の薄い金属膜が陥没したり、破損する。
【0004】また、特開2002−164658号公報に開示されているモジュ−ル基板では、多層基板の表面に電子部品が実装され、外部との接続に使用する電極を多層基板の側面の中間層基板と底面層基板に導通溝が形成され、電子部品が実装される表面の層には、上記導通溝が形成されていない表面層基板を設けるモジュ−ル基板である。
このモジュ−ル基板では中間層基板と底面層基板の側面には端面電極用スルーホールが形成されているが中間層基板の上に貼り合わせる表面層基板には端面電極用スルーホールは形成されていないものである。
【0005】上記のモジュ−ル基板では表面層基板と中間層基板と底面層基板の3枚の基板を貼り合わせた3層基板であり、薄板化には問題がある。
また、中間層基板と底面層基板を貫通する端面電極用スルーホールの上に表面層基板を貼り合わせる際にプリプレグ等の接着樹脂がスルーホール内に流れ込むことやスルーホールから形成する導通溝の上面である表面層基板の裏面には導体層が形成されていない。
従って、薄板化が要求される高精細な電子部品用のベ−ス基板としては問題があり、端面電極としても、はんだ濡れ性不良が生じ易い。
【0006】
【特許文献1】
特開平10−65298号公報。
【特許文献2】
特開2002−164658号公報。
【0007】
【発明が解決しようとする課題】基板に電子部品素子、電子部品を実装し、その後実装した電子部品素子や電子部品を樹脂封止して端面電極を有するモ−ルドチップ部品とするには、基板に設けた貫通スルーホール穴の内部に封止樹脂が侵入しないように貫通スルーホール穴の上面側に樹脂の侵入を阻止する部材(絶縁基材、絶縁テ−プ、フィルム状、シ−ト状などの阻止部材)を設けなければならない。
上記の阻止部材を張り合わせる為、高密度化や端面電極の接続信頼性を低下していた。
特に、最近ではモ−ルドチップ部品の小型高密度化、端面電極の高い電気的及びはんだ接続信頼性が要求されている。
特に、薄型高密度のモ−ルド樹脂部品を高温高圧(140〜180℃、20〜30トン)で大量生産するトランスファモ−ルド法では高い信頼性が要求される。
【0008】特開平10−65298号公報に示す外層導体を利用して貫通導通穴の上面を塞ぐ非貫通導通穴構造の配線基板では、貫通導通穴の上面を塞ぐ樹脂阻止ランド、電子部品接続ランド、配線パタ−ンが同一表面層に集中し高密度実装に問題がある。
又、この非貫通導通穴の上面を塞ぐ外層導体は、通常薄い金属被膜であるためワイヤ−ボンデング用の電子部品接続ランドには不可であり、かつ樹脂で封止する圧力が高くなると、この圧力によって非貫通導通穴の金属被膜が陥没したり、破けたり、非貫通導通穴が破損する。
さらに、薄板の非貫通導通穴構造の配線基板では、電子部品素子、電子部品を実装する際に配線基板の強度不足により、そりやねじれが生じ実装不良やはんだ濡れ性不良が生じる。
【0009】特開2002−164658号公報に開示されているモジュ−ル基板とは、1つの組立体系の中での分離可能なユニット(日本プリント回路工業会発行のプリント回路用語)となる基板である。
しかし、モ−ルドチップ部品の小型高密度化、端面電極の高い電気的及びはんだ接続信頼性が要求される薄板のベ−ス基板としては問題点が多く不可となっていた。
【0010】
【課題を解決するための手段】
上記の課題を解決するため、ダイシング用の分割切断線上に端面電極用の非貫通導通穴を有する配線基板において、電子部品や電子部品素子を実装する部品接続ランドを備えた上部配線基板と、上記分割切断線上に配置する下部配線基板の第2のブラインドビア(B2)と、上記の上部配線基板の部品接続ランドと下部配線基板の第2のブラインドビア(B2)とを電気的に接続する第1のブラインドビア(B1)と、から構成される非貫通導通穴を有する多層基板とする。
【0011】また、ダイシング用の分割切断線上に端面電極用の非貫通導通穴を有する配線基板において、電子部品や電子部品素子を実装する配線基板の上面導体(L1)と、配線基板の下面導体(L3)と、配線基板の内層導体(L2)とからなる3層導体構造であって、
電子部品や電子部品素子を実装する部品接続ランドを備えた上部配線基板と、上記の分割切断線上の下部配線基板に配置する端面電極用の第2のブラインドビア(B2)と、上記の上部配線基板の部品接続ランドと下部配線基板の第2のブラインドビア(B2)とを電気的に接続する第1のブラインドビア(B1)と、からなることを特徴とする非貫通導通穴を有する多層基板とする。
【0012】
【発明の実施の形態】以下、本発明の非貫通導通穴を有する多層基板を形成する製造工程を図2を参照して説明する。
まず、図2(a)として下面の銅箔4がある片面銅張積層板の基材2側に乳液状、フィルム状、シ−ト状などの接着剤3を張り合わせ下部配線基板1とする。図2(b)接着剤を半硬化してから下部配線基板1の所定の箇所にNCドリリングマシンにより、穴明け加工を施して貫通穴9とする。次に図2(c)に示すように、下部配線基板1の所定の箇所に穴明け加工を施して貫通穴9を形成した下部配線基板1の接着剤3の上に銅箔6を積層プレスをして張り合わせる。
次に図2(d)に示すように、下部配線基板1の上面の銅箔6の所定の箇所にエッチングして内層パタ−ン(L2)を回路形成する。
【0013】図2(e)は下部配線基板1の上面の銅箔6の所定の箇所に内層パタ−ン(L2)を回路形成した上面に絶縁層7と銅箔8を積層プレスをして上部配線基板10を形成する。
次に図2(f)に示すように、上部配線基板10の所定の箇所に上面外層の銅箔8と内層パタ−ン(L2)の間だの絶縁層7を炭酸ガスレーザー加工により絶縁樹脂を除去し非貫通穴11を形成する。
その次に、図2(g)に示すように無電解銅めっきを施し、めっき層12を形成して所定の上部配線基板10の非貫通導通穴15と下部配線基板1の非貫通導通穴16を形成する。その後、所定の箇所をエッチングして上面外層パタ−ン(L1)と下面外層パタ−ン(L3)とを回路形成する。
【0014】配線基板の片側だけに開口しているビアをブラインドビアと呼ばれ、外層導体と内層導体を電気的に接続する非貫通導通穴である。上面外層パタ−ン(L1)と内層パタ−ン(L2)とを電気的に接続する上部配線基板10に形成した非貫通導通穴15を第1のブラインドビア(B1)とし、内層パタ−ン(L2)と下面外層パタ−ン(L3)とを電気的に接続する非貫通導通穴16を第2のブラインドビア(B2)とするもである。また、信頼性の向上、はんだ付性の向上、ワイヤーボンデング作業等の必要性からソルダーレジストの形成やNi−Auめっき等を行う場合もある。
【0015】本発明の非貫通導通穴を有する多層基板の構成について図1で説明する。配線基板の上面導体(L1)と、配線基板の下面導体(L3)と、配線基板の内層導体(L2)とからなる3層導体構造であって、電子部品や電子部品素子を実装する部品接続ランド17を配線基板の上面導体(L1)に設ける。分割切断線18上の下部配線基板1に配置する端面電極用の非貫通導通穴である第2のブラインドビア(B2)と、上記の上部配線基板10の部品接続ランド17と下部配線基板1の第2のブラインドビア(B2)とを電気的に接続する非貫通導通穴である上部配線基板10の第1のブラインドビア(B1)と、からなる非貫通導通穴を有する多層基板とする。
この下部配線基板1に形成する内層パタ−ン(L2)と下面外層パタ−ン(L3)とを電気的に接続する非貫通導通穴の略中央部を通る分割切断線でダイシング切断して端面電極を形成するためのブラインドビアである。
【0016】モ−ルドチップ部品の小型高密度化、端面電極の高い電気的及びはんだ接続信頼性に対応し、特に薄型高密度のチップ部品をトランスファモ−ルド法で大量生産するベ−ス基板として、上部配線基板の絶縁層の厚さ0.03〜0.200mmとする。端面電極用の非貫通導通穴を形成する下部配線基板の基材の厚さは0.20〜0.50mmとする。また、非貫通導通穴の穴径は端面電極用の第2のブラインドビア(B2)はφ0.30〜φ1.00mmが良好である。第1のブラインドビア(B1)はφ0.10〜φ0.30mmが良好である。
つまり、本発明の非貫通導通穴を有する多層基板は配線基板の上面と下面を貫通するスル−ホ−ル穴を設けないものである。
【0017】
【発明の効果】配線基板の上面と下面を貫通するスル−ホ−ル穴を設けない非貫通導通穴を有する多層基板は電気的及びはんだ接続信頼性が高い下部配線基板の端面電極用のブラインドビア(B2)が形成できる。 また、上部配線基板には端面電極用のブラインドビア(B2)は形成されなく部品接続ランドが主体であるから高密度にチップ部品を確実に実装できる。
【図面の簡単な説明】
【図1】本発明の非貫通導通穴を有する多層基板の実施例。
【図2】本発明の非貫通導通穴を有する多層基板を説明する製造工程図。
【符号の説明】
1…下部配線基板、2…基材、3…接着剤、4…下面の銅箔、
6…銅箔、7…絶縁層、8…銅箔、9…貫通穴、
10…上部配線基板、11…非貫通穴、12…めっき層、
15,16…非貫通導通穴、17…部品接続ランド、18…分割切断線。
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a printed wiring board, and more particularly, to a multilayer board serving as a base board for a mold chip component forming an end face electrode.
[0002]
[Prior art]
Conventionally, when forming an end face electrode on a substrate, a through-hole hole is provided in a straight line in the vicinity of the outer side surface of the printed wiring board, and the through-hole hole is divided and cut substantially on the center line of the through-hole hole. An end surface electrode having a semi-cylindrical inside and exposed to the outside is formed.
A semiconductor integrated circuit element, an electronic component element, and an electronic component are mounted on a substrate, and thereafter, the wiring pattern of the substrate, the semiconductor integrated circuit element, the electronic component element, and the electronic component are molded with a resin and sealed with a resin. In order to form a mold chip component having an end face electrode, a member (film, tape, tape, etc.) for preventing resin from intruding on the upper surface side of the through-hole hole so as to prevent sealing resin from entering the inside of the through-hole hole. Substrate, etc.).
As one example, there is an end face through-hole wiring board disclosed in Japanese Patent Application Laid-Open No. 10-65298.
This is an end-face through-hole wiring board in which a non-through conductive through-hole is formed in which one end of the through-hole is open and the other end is closed by an outer conductor. In other words, the upper surface of the through conduction hole is closed with the outer layer conductor using the outer layer conductor as a member for preventing the intrusion of the sealing resin.
The outer layer conductor of the non-through conductive through-hole is usually a thin metal film of 0.05 mm or less. Therefore, in the transfer molding method in which the sealing pressure with resin is high, the thin metal film of the non-through conductive hole is high due to the high pressure. Is collapsed or damaged.
In the module board disclosed in Japanese Patent Application Laid-Open No. 2002-164658, an electronic component is mounted on the surface of the multilayer board, and electrodes used for connection to the outside are provided on an intermediate layer on the side of the multilayer board. This is a module substrate in which a conductive groove is formed in a substrate and a bottom layer substrate, and a surface layer substrate in which the conductive groove is not formed is provided in a surface layer on which electronic components are mounted.
In this module substrate, through holes for end surface electrodes are formed on the side surfaces of the intermediate layer substrate and the bottom layer substrate, but through holes for end surface electrodes are formed in the surface layer substrate bonded onto the intermediate layer substrate. Not something.
The above-mentioned module substrate is a three-layer substrate in which three substrates, a surface layer substrate, an intermediate layer substrate, and a bottom layer substrate, are bonded to each other, and there is a problem in making the module thinner.
Also, when the surface layer substrate is bonded onto the through-hole for the end face electrode penetrating through the intermediate layer substrate and the bottom layer substrate, an adhesive resin such as a prepreg flows into the through-hole and the upper surface of the conductive groove formed from the through-hole. No conductor layer is formed on the back surface of the surface layer substrate.
Therefore, there is a problem as a base substrate for a high-definition electronic component required to be thinner, and poor solder wettability is likely to occur also as an end face electrode.
[0006]
[Patent Document 1]
JP-A-10-65298.
[Patent Document 2]
JP-A-2002-164658.
[0007]
In order to mount an electronic component and an electronic component on a substrate, and then seal the mounted electronic component and the electronic component with a resin to obtain a mold chip component having end electrodes, A member (insulating base material, insulating tape, film, sheet, etc.) for preventing resin from intruding on the upper surface side of the through-hole hole so that the sealing resin does not enter the inside of the through-hole hole provided in Blocking member).
The lamination of the blocking members described above has increased the density and reduced the connection reliability of the end face electrodes.
In particular, recently, miniaturization and high-density of molded chip parts and high electrical and solder connection reliability of end face electrodes are required.
In particular, high reliability is required in the transfer molding method for mass-producing thin high-density mold resin parts at high temperature and pressure (140 to 180 ° C., 20 to 30 tons).
[0008] In a wiring board having a non-through conductive hole structure in which the upper surface of a through conductive hole is closed by using an outer layer conductor disclosed in Japanese Patent Application Laid-Open No. H10-65298, a resin blocking land and an electronic component connection land that block the upper surface of the through conductive hole In addition, wiring patterns are concentrated on the same surface layer, and there is a problem in high-density mounting.
In addition, since the outer layer conductor that closes the upper surface of the non-through conductive hole is usually a thin metal film, it cannot be used as a connection land for electronic parts for wire-bonding. As a result, the metal coating of the non-through conductive hole is depressed or broken, or the non-through conductive hole is damaged.
Furthermore, in the case of a wiring board having a thin non-through conductive hole structure, warpage or twisting occurs due to insufficient strength of the wiring board when mounting electronic components and electronic components, resulting in poor mounting and poor solder wettability.
A module board disclosed in Japanese Patent Application Laid-Open No. 2002-164658 is a board that becomes a separable unit (printed circuit term issued by Japan Printed Circuit Industries Association) in one assembly system. is there.
However, there have been many problems with a thin base board which requires miniaturization and high density of a mold chip component, high electrical end face electrodes, and high reliability of solder connection.
[0010]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, in a wiring board having a non-through conductive hole for an end face electrode on a division cutting line for dicing, an upper wiring board having a component connection land for mounting an electronic component or an electronic component element, The second blind via (B2) of the lower wiring board arranged on the divisional cutting line, and the second blind via (B2) of the lower wiring board electrically connecting the component connection land of the upper wiring board and the second blind via (B2) of the lower wiring board. And a blind via (B1).
In a wiring board having a non-through conductive hole for an end face electrode on a dicing cut line, an upper conductor (L1) of the wiring board on which electronic components and electronic component elements are mounted, and a lower conductor of the wiring board (L3) and an inner layer conductor (L2) of the wiring board,
An upper wiring board provided with a component connection land for mounting an electronic component or an electronic component element, a second blind via (B2) for an end face electrode disposed on the lower wiring board on the division cutting line, and the upper wiring A first blind via (B1) for electrically connecting a component connection land of the board to a second blind via (B2) of the lower wiring board; and a multi-layer board having a non-through conductive hole. And
[0012]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a manufacturing process for forming a multilayer substrate having a non-through conductive hole according to the present invention will be described with reference to FIG.
First, as shown in FIG. 2A, an adhesive 3, such as an emulsion, a film, or a sheet, is adhered to the base material 2 side of a single-sided copper-clad laminate having a copper foil 4 on the lower surface to form a lower wiring board 1. After the adhesive is semi-cured as shown in FIG. 2B, a predetermined portion of the lower wiring substrate 1 is subjected to a drilling process by an NC drilling machine to form a through hole 9. Next, as shown in FIG. 2C, a copper foil 6 is laminated and pressed on the adhesive 3 of the lower wiring board 1 in which a predetermined portion of the lower wiring board 1 is punched and a through hole 9 is formed. And stick them together.
Next, as shown in FIG. 2D, a predetermined portion of the copper foil 6 on the upper surface of the lower wiring substrate 1 is etched to form an inner layer pattern (L2) as a circuit.
FIG. 2E shows an insulating layer 7 and a copper foil 8 laminated and pressed on the upper surface where an inner layer pattern (L2) is formed in a circuit at a predetermined location of the copper foil 6 on the upper surface of the lower wiring board 1. The upper wiring substrate 10 is formed.
Next, as shown in FIG. 2 (f), the insulating layer 7 between the upper outer layer copper foil 8 and the inner layer pattern (L2) is formed on a predetermined portion of the upper wiring board 10 by carbon dioxide laser processing. Is removed to form a non-through hole 11.
Then, as shown in FIG. 2 (g), electroless copper plating is performed to form a plating layer 12, and a predetermined non-through conductive hole 15 of the upper wiring board 10 and a predetermined non-through conductive hole 16 of the lower wiring board 1 are formed. To form Thereafter, a predetermined portion is etched to form an upper surface outer layer pattern (L1) and a lower surface outer layer pattern (L3).
A via opening only on one side of the wiring board is called a blind via, and is a non-through conductive hole for electrically connecting the outer conductor and the inner conductor. A non-through conductive hole 15 formed in the upper wiring board 10 for electrically connecting the upper outer layer pattern (L1) and the inner layer pattern (L2) is defined as a first blind via (B1), and the inner layer pattern is formed. The non-through conductive hole 16 for electrically connecting (L2) and the lower surface outer layer pattern (L3) is used as a second blind via (B2). In some cases, formation of a solder resist, Ni-Au plating, or the like is performed due to the necessity of improving reliability, improving solderability, and wire bonding work.
The structure of a multilayer substrate having a non-through conductive hole according to the present invention will be described with reference to FIG. A three-layer conductor structure including an upper conductor (L1) of the wiring board, a lower conductor (L3) of the wiring board, and an inner conductor (L2) of the wiring board, and is a component connection for mounting an electronic component or an electronic component element. The land 17 is provided on the upper surface conductor (L1) of the wiring board. A second blind via (B2), which is a non-through conductive hole for an end face electrode disposed on the lower wiring substrate 1 on the divisional cutting line 18, and the component connection lands 17 of the upper wiring substrate 10 and the lower wiring substrate 1; A multilayer substrate having a non-through conductive hole made of the first blind via (B1) of the upper wiring board 10 which is a non-through conductive hole for electrically connecting the second blind via (B2).
The dicing is performed by dicing with a cutting line that passes through a substantially central portion of a non-through conductive hole for electrically connecting an inner layer pattern (L2) formed on the lower wiring board 1 and a lower outer layer pattern (L3). It is a blind via for forming an electrode.
In response to miniaturization of high-density molded chip components and high electrical and solder connection reliability of the end face electrodes, especially as a base substrate for mass-producing thin and high-density chip components by the transfer molding method. The thickness of the insulating layer of the upper wiring board is set to 0.03 to 0.200 mm. The thickness of the base material of the lower wiring board in which the non-through conduction hole for the end face electrode is formed is 0.20 to 0.50 mm. The hole diameter of the non-through conductive hole is preferably 0.30 to 1.00 mm for the second blind via (B2) for the end face electrode. The diameter of the first blind via (B1) is preferably φ0.10 to φ0.30 mm.
That is, the multi-layer board having the non-through conduction hole of the present invention does not have the through hole penetrating the upper and lower surfaces of the wiring board.
[0017]
According to the present invention, a multi-layer board having a non-through conductive hole which does not have a through-hole penetrating the upper and lower surfaces of the wiring board has a highly reliable electrical and solder connection. Via (B2) can be formed. In addition, since the upper wiring board is not provided with the blind vias (B2) for the end face electrodes and is mainly composed of the component connection lands, the chip components can be reliably mounted at a high density.
[Brief description of the drawings]
FIG. 1 is an embodiment of a multilayer substrate having a non-through conduction hole according to the present invention.
FIG. 2 is a manufacturing process diagram illustrating a multilayer substrate having a non-through conductive hole according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Lower wiring board, 2 ... Base material, 3 ... Adhesive, 4 ... Lower surface copper foil,
6 ... copper foil, 7 ... insulating layer, 8 ... copper foil, 9 ... through hole,
10: upper wiring board, 11: non-through hole, 12: plating layer,
15, 16: non-through conduction hole, 17: component connection land, 18: division cutting line.

Claims (2)

ダイシング用の分割切断線上に端面電極用の非貫通導通穴を有する配線基板において、電子部品や電子部品素子を実装する部品接続ランドを備えた上部配線基板と、上記分割切断線上に配置する下部配線基板の第2のブラインドビア(B2)と、上記の上部配線基板の部品接続ランドと下部配線基板の第2のブラインドビア(B2)とを電気的に接続する第1のブラインドビア(B1)と、からなることを特徴とする非貫通導通穴を有する多層基板。In a wiring board having a non-through conductive hole for an end face electrode on a dicing division cutting line, an upper wiring substrate provided with a component connection land for mounting an electronic component or an electronic component element, and a lower wiring arranged on the division cutting line A second blind via (B2) of the board, and a first blind via (B1) for electrically connecting the component connection land of the upper wiring board and the second blind via (B2) of the lower wiring board. , Comprising a non-through conductive hole. ダイシング用の分割切断線上に端面電極用の非貫通導通穴を有する配線基板において、電子部品や電子部品素子を実装する配線基板の上面導体(L1)と、配線基板の下面導体(L3)と、配線基板の内層導体(L2)とからなる3層導体構造であって、
電子部品や電子部品素子を実装する部品接続ランドを備えた上部配線基板と、上記の分割切断線上の下部配線基板に配置する端面電極用の第2のブラインドビア(B2)と、上記の上部配線基板の部品接続ランドと下部配線基板の第2のブラインドビア(B2)とを電気的に接続する第1のブラインドビア(B1)と、からなることを特徴とする非貫通導通穴を有する多層基板。
An upper conductor (L1) of a wiring board on which electronic components and electronic component elements are mounted, a lower conductor (L3) of the wiring board, and a wiring board having a non-through conductive hole for an end surface electrode on a dicing division cutting line; A three-layer conductor structure comprising an inner conductor (L2) of the wiring board;
An upper wiring board provided with a component connection land for mounting an electronic component or an electronic component element, a second blind via (B2) for an end face electrode disposed on the lower wiring board on the division cutting line, and the upper wiring A first blind via (B1) for electrically connecting a component connection land of the board to a second blind via (B2) of the lower wiring board; and a multi-layer board having a non-through conductive hole. .
JP2003139327A 2003-05-16 2003-05-16 Multilayer substrate having non-through conduction hole Pending JP2004342930A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007042993A (en) * 2005-08-05 2007-02-15 Daisho Denshi:Kk Method for manufacturing multilayer substrate
JP2015177141A (en) * 2014-03-18 2015-10-05 Fdk株式会社 Substrate for electronic circuit module, multi-surface board for substrate for electronic circuit module, and method of manufacturing substrate for electronic circuit module
CN109587936A (en) * 2018-12-13 2019-04-05 广东全宝科技股份有限公司 A kind of manufacture craft of the unilateral double-deck circuit base plate

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JPH04243197A (en) * 1991-01-17 1992-08-31 Matsushita Electric Ind Co Ltd Multilayer printed wiring board
JPH05218653A (en) * 1992-01-31 1993-08-27 Sumitomo Metal Ind Ltd Ceramic multilayer circuit board
JPH10270819A (en) * 1997-03-28 1998-10-09 Ngk Spark Plug Co Ltd Surface mounting electronic part and its manufacture
JP2002164658A (en) * 2000-11-29 2002-06-07 Sharp Corp Module board
JP2002185140A (en) * 2000-12-15 2002-06-28 Hitachi Ltd Multilayer printed board and its manufacturing method

Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
JPH04243197A (en) * 1991-01-17 1992-08-31 Matsushita Electric Ind Co Ltd Multilayer printed wiring board
JPH05218653A (en) * 1992-01-31 1993-08-27 Sumitomo Metal Ind Ltd Ceramic multilayer circuit board
JPH10270819A (en) * 1997-03-28 1998-10-09 Ngk Spark Plug Co Ltd Surface mounting electronic part and its manufacture
JP2002164658A (en) * 2000-11-29 2002-06-07 Sharp Corp Module board
JP2002185140A (en) * 2000-12-15 2002-06-28 Hitachi Ltd Multilayer printed board and its manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007042993A (en) * 2005-08-05 2007-02-15 Daisho Denshi:Kk Method for manufacturing multilayer substrate
JP2015177141A (en) * 2014-03-18 2015-10-05 Fdk株式会社 Substrate for electronic circuit module, multi-surface board for substrate for electronic circuit module, and method of manufacturing substrate for electronic circuit module
CN109587936A (en) * 2018-12-13 2019-04-05 广东全宝科技股份有限公司 A kind of manufacture craft of the unilateral double-deck circuit base plate

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