JP2000340698A - Substrate for leadless chip carrier and leadless chip carrier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate for a package which can increase manufacturing yield, without using expensive inspection devices. SOLUTION: A substrate for a leadless chip carrier, which is formed with a conductor pattern 5a to mount a plurality of chips and is also formed with a through-hole 3 as an interconnection has a multilayer structure wherein an upper layer substrate 1 formed with a via hole 4 connected to the conductor pattern 5a and a lower layer substrate 2, formed with a conductor pattern 5b connected to a blind via 4 and a through-hole 3 connected to the conductor pattern 5b are stacked and joined. Through-holes 7, 10, 17 are formed so as to communicate with a frame section which does not constitute a part of the leadless chip carrier.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a leadless chip carrier (hereinafter referred to as L) having a laminated structure.
And more particularly, to a substrate capable of improving the yield.

[0002]

2. Description of the Related Art As the operating speed of a semiconductor device has been improved, there has been a demand for a package on which a semiconductor chip (hereinafter abbreviated as "chip") is mounted to reduce transmission signal loss and improve signal propagation speed. To meet such demands, a package having a land grid array (hereinafter abbreviated as LGA) structure as shown in FIG. 4 and a package having an LCC structure as shown in FIG. 5 have been provided. I have.

As shown in these figures, in the LGA structure, bump electrodes of a chip 14 and lands 15 in a grid arrangement, which are mounting electrodes, are connected by via holes 4.
In the CC structure, the bump electrode of the chip 14 is connected to the wiring 5c on the side surface via a conductor pattern on the substrate surface. Reference numeral 11 denotes a protective material such as a resin for protecting the bonding portion, which is adhered by a mold.

[0004]

However, in the LGA structure shown in FIG. 4, a plurality of substrates are laminated and formed. In some cases, the via hole and the wiring pattern of the lower substrate are displaced from each other and electrical conduction is not performed. This is particularly noticeable with fine pitch.

[0005] Furthermore, because of the structure in which the grid-like lands 15 are provided on the back surface, the lands 1 are mounted on a mounting substrate (not shown).
5 and the pattern of the mounting board cannot be visually observed,
An expensive inspection device such as a wire device is required, and the inspection cost is increased.

On the other hand, in the LCC structure shown in FIG. 5, since the substrates are not stacked, there is no problem of displacement, and the inspection of the connection state can be visually checked, so that the inspection cost can be reduced. However, when the chip is covered with the protective material 11 to protect the chip, there is a possibility that the resin may go around the back surface through the recess 13 because the recess 13 is provided on the side surface of the substrate. The illustrated recess 13 is obtained by dividing a through hole by dicing or scribing. If a part of the protective material goes around the back surface, it may be an obstacle at the time of mounting.

Also, in the LCC structure, the solder fillet may creep up on the electrode on the side surface and wet the chip mounting surface when mounting on the mounting board. Is incorrectly recognized as a part of the solder fillet, and even if the solder does not spread to the pattern on the surface of the mounting board and is not connected to the pattern, a good product may be determined.

SUMMARY OF THE INVENTION An object of the present invention is to provide a package substrate and a package which can solve the above-mentioned problems and can improve the mounting yield on a mounting substrate.

[0009]

To achieve the above object, a substrate for a leadless chip carrier according to the first aspect of the present invention includes a plurality of substrates repeatedly formed on at least an outer surface of a region for forming a leadless chip carrier. An upper layer substrate having a conductor pattern on which electronic components composed of the same pattern can be mounted, and a conductor pattern formed on the outer surface so as to correspond to the conductor pattern of the upper layer substrate and to be connectable to the mounting substrate. A leadless chip carrier substrate having a laminated structure in which a conductive pattern of the upper substrate and a conductive pattern of the lower substrate are internally conducted by internal wiring, wherein the lead of each of the upper substrate and the lower substrate is provided. A through hole communicating with each other is formed in a frame portion that does not constitute a less chip carrier, and a through hole of the upper layer substrate is formed. Substrate for leadless chip carrier, wherein the through holes of the serial underlying substrate is large.

According to a second aspect of the present invention, in the leadless chip carrier substrate, the internal wiring is for connecting a via hole or a through hole formed in the upper substrate and the lower substrate to the via hole or the through hole. A conductive pattern, a misregistration detection mark is provided around the through hole of the lower substrate, and the misregistration detection mark is entirely or partially exposed in the through hole region of the upper substrate. And

The leadless chip carrier substrate according to a third aspect of the present invention is characterized in that the misalignment detection mark is a metallized pattern that concentrically surrounds the through hole of the lower substrate.

A leadless chip carrier substrate according to a fourth aspect of the present invention is the leadless chip carrier substrate according to any one of the first to third aspects, wherein the internal wiring of the upper layer substrate includes a via hole; The internal wiring in the lower substrate includes a through hole.

According to a fifth aspect of the present invention, there is provided a substrate for a leadless chip carrier, wherein the through hole included in the lower substrate of the substrate for a leadless chip carrier according to the fourth aspect of the present invention is provided in a peripheral portion of a chip carrier forming region. It is characterized by being arranged.

According to a sixth aspect of the present invention, there is provided a leadless chip carrier substrate, wherein the through holes of the leadless chip carrier substrate according to the fifth aspect of the present invention are arranged in a line on each side of a peripheral portion of the chip carrier forming region. The through-holes of each side are shared by the adjacent chip carrier forming regions, and the through-holes formed in the frame portion of the upper layer substrate and the lower layer substrate and communicating with each other are arranged in a line. Each pair is formed so as to be aligned with the through hole with the through hole interposed therebetween.

A leadless chip carrier according to a seventh aspect of the present invention is a leadless chip carrier obtained by cutting and separating the leadless chip carrier substrate according to the fifth or sixth aspect, wherein It is characterized in that it is cut and separated along a line, which is provided in a peripheral portion and connects the approximate center of the through hole.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. It is to be noted that components denoted by the same reference numerals in a plurality of drawings indicate the same or corresponding components.

FIG. 1 is an exploded perspective view of an LCC substrate showing an embodiment of the present invention, and shows an example in which four substrates are taken. In the figure, 1 is an upper substrate, 2 is a lower substrate, 3 is a through hole, 6, 7, 10, 16, and 17 are through holes, and 8 and 9 are metallized patterns.

As shown in the drawing, the LCC substrate of the present invention is obtained by joining an upper substrate 1 and a lower substrate 2 so as to overlap each other. The prototype of each substrate is made by well-known green sheet processing or screen printing, and the integration of these is performed by superimposing and then firing.

The upper substrate 1 has via holes 4 and through holes 6, 10, and 17 which are simultaneously formed in the same mold in a green sheet state, and is formed by applying a conductive paste by screen printing thereafter. A conductor pattern 5a connected to the electrode of the semiconductor chip, a metallized pattern 8, and a conductor in the via hole 4.

The through holes 6, 10 and 17 are formed in the frame portion 19 (excess portion) of the substrates 1 and 2 which are not formed as a package after dicing. Incidentally, a portion (package forming region) configured as a package after dicing is a region surrounded by a dicing line 12 connecting substantially the centers of the through holes 3.

The dicing line 12 is a line connecting the through holes 17 in the upper substrate 1. This is because a pair of the through holes 16 is formed so as to sandwich the through holes so that the through holes 16 are further arranged in a line in each line on each side of the package forming region. Is formed.

A metallization pattern 8 is formed around the through hole 6 so as to surround the through hole 6 concentrically.
The through-hole 7 and the metallized pattern 9 of the lower substrate 2 to be superimposed later are formed in such a size that the metallized pattern 9 is sufficiently exposed.

The lower substrate 1 has through-holes 3 and through-holes 7 and 16 formed in the same mold at the same time in the green sheet state, and is formed by applying a conductive paste by screen printing thereafter. Conductor pattern 5b,
There are metallized patterns 9 and conductors in through holes 3.

The through holes 7, 16 are formed to have the same diameter as the holes of the through hole 3, and these are also formed in the frame of the substrate, like the through holes of the upper layer substrate. A metallized pattern 9 is formed around the through hole 7 so as to surround the through hole 7 concentrically.

FIG. 2 is a partial sectional view of the LCC substrate of the present invention, and 12 indicates a dicing line. As shown in the figure, the conductor pattern 5a of the LCC substrate which is superposed, fired and integrated is the brand via 4 and the conductor pattern 5b.
Through to the through hole 3. In this figure, for the sake of understanding, the cross section of the internal wiring, the cross section of the through hole and the cross section of the metallized pattern, which are not originally arranged on one cross section, are shown side by side.

With such a configuration, even if a flip chip (not shown) is face-down bonded to the conductor pattern 5a and covered with the protective material 11, no through hole is formed on the surface. This prevents the protective material 11 from entering the device and hindering mounting.

Further, by using the through hole 17 as a reference for aligning the dicing saw at the time of dicing, the through hole 17 can be cut by a line connecting substantially the center of the through hole even when the through hole is hidden by the upper layer substrate. It is possible.

After the cutting, a semiconductor device as shown in FIG. 3 can be obtained. The LCC 20 shown in this figure has a concave portion 13 formed by dividing the through hole 3 shown in FIG. 1 or FIG. 2, but the concave portion does not reach the substrate surface and is blocked by the upper substrate 1. Therefore,
This prevents solder creeping up during mounting, and prevents erroneous recognition in the inspection process.

Further, the printing deviation between the hole of the through hole 3 and the conductor or the conductor pattern 5b therein can be determined by observing the deviation between the through hole 7 and the metallized pattern 9, and
This can be exposed to the outside through the through hole 10 and visually recognized even after the substrate is integrated, and can be checked and fed back in any process after screen printing. Similarly, from the shift between the through-hole 6 of the upper layer substrate and the metallized pattern 8, the shift of the print mask between the via hole 4 and the conductor pattern 5 a can be observed even after being covered with the protective material 11.

Further, according to the amount of deviation between the through holes 16 and 17,
The amount of displacement between the upper substrate and the lower substrate can be observed.
These shift amounts can be determined to be good or bad by an image processing method such as a well-known pattern matching method.
For example, the through hole 17 is φ200 μm, and the through hole 16 is φ10
When 0 μm, the center of each hole is ± 50μ at maximum.
Although the through hole 16 is inserted into the through hole 17 in a plan view even if the distance is shifted by m, if the distance is further shifted, the circumference overlaps, so that it is possible to easily set a desired deviation tolerance using this. is there. Incidentally, when the through hole 16 is φ100 μm as described above, and when it is desired to set the deviation tolerance to ± 30 μm, the through hole 1
7 may be φ160 μm. The same applies to the relationship between the through hole and the metallization.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications can be made. For example, in the above embodiment, a single-layer substrate is used as the upper substrate, but a multi-layer substrate having two or more via holes may be used.

The diameter of the through hole 7 is the same as the diameter of the through hole 3 in order to simplify the die for drilling.
The diameters do not necessarily have to be the same.

A concentric metallization pattern is formed around the through holes 6 and 7 so as to surround the through holes 6 and 7.
Other types of detection marks may be used as long as the relative displacement between the through-hole and the conductor (paste) can be determined. However, in the embodiment, the concentric shape enables measurement of the deviation in all directions on the plane.

[0034]

As described above, by covering the through-hole with the upper layer substrate, the protective material can be applied collectively without worrying about entry into the through-hole. This allows
A large number of packages of the LCC structure can be sealed at once. Cutting can also be performed using a pair of through holes provided in the frame portions of the upper layer and the lower layer substrate as a positioning reference at the time of dicing, and obey a dicing line or a scribe line formed of a line connecting the pair of through holes. If so, it can be done reliably.

Further, when a final product is obtained as a semiconductor device, a fillet of solder can be visually observed, and the solder is prevented from creeping up on the chip mounting surface, so that an expensive inspection device is not required and the yield is improved. Can be.

In addition, it is possible to observe at any time the displacement between the substrates and the displacement between the holes of the via holes and the through holes and the conductors therein and the conductor patterns connected thereto, so that the inspection process can be flexibly arranged. It becomes possible.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view of an LCC substrate according to the present invention.

FIG. 2 is a partial cross-sectional view of the LCC substrate of the present invention.

FIG. 3 is a diagram showing a semiconductor device using the LCC of the present invention.

FIG. 4 is a diagram showing a conventional semiconductor device having an LGA structure.

FIG. 5 is a diagram showing a conventional semiconductor device having an LCC structure.

[Explanation of symbols]

1: upper layer substrate, 2: lower layer substrate, 3: through hole, 4:
Via hole, 5: conductor pattern, 6, 7, 10, 16,
17: through hole, 8, 9: metallized pattern, 11: protective material, 12: dicing line, 13: concave, 14: chip, 15: land, 19: frame, 20: LCC

Claims (7)

[Claims] An upper layer substrate having a conductor pattern on which electronic components having a plurality of identical patterns repeatedly formed on at least an outer surface of a region for forming a leadless chip carrier can be mounted. A lower layer substrate having a conductor pattern corresponding to the conductor pattern of the upper substrate and formed so as to be connectable to the mounting substrate on the surface, wherein the conductor pattern of the upper substrate and the conductor pattern of the lower substrate are internally formed by internal wiring. In the substrate for a leadless chip carrier having a laminated structure, the through-holes communicating with each other are formed in frame portions of the upper layer substrate and the lower layer substrate that do not constitute the leadless chip carrier, and the through holes of the upper layer substrate are formed. A substrate for a leadless chip carrier, wherein the substrate is larger than a through hole of the lower substrate. 2. The internal wiring comprises a via hole or a through hole formed in the upper substrate and the lower substrate, and a conductor pattern for connecting the via hole or the through hole to each other. 2. The misalignment detection mark is provided in the periphery, and the misalignment detection mark is entirely or partially exposed in a through-hole region of the upper substrate superimposed on the lower substrate. Leadless chip carrier. 3. The substrate for a leadless chip carrier according to claim 1, wherein the misregistration detection mark is a metallized pattern that concentrically surrounds the through hole of the lower substrate. 4. The leadless chip carrier substrate according to claim 1, wherein the internal wiring of the upper substrate includes a via hole, and the internal wiring of the lower substrate includes a through hole. 5. The substrate for a leadless chip carrier according to claim 4, wherein said through holes included in said lower substrate are arranged in a peripheral portion of a chip carrier forming region. 6. The upper substrate and the lower substrate, wherein the through holes are arranged in a line on each side of a peripheral portion of the chip carrier forming region, and the through holes on each side are shared by the adjacent chip carrier forming regions. The through-holes formed in the frame portion and communicating with each other are formed in a pair so that the through-holes are arranged in a line and sandwich the through-holes and are arranged in a line with the through-holes. Item 6. A substrate for a leadless chip carrier according to item 5. 7. A leadless chip carrier obtained by cutting and separating the leadless chip carrier substrate according to claim 5 or 6, wherein the through hole provided in a peripheral portion of the chip carrier forming region is provided. A leadless chip carrier which is cut and separated along a line substantially connecting the centers.