KR20010011310A - Method for manufacturing stack package - Google Patents

Abstract

PURPOSE: A method for manufacturing a laminated package is to laminate chip scale packages using a tape wiring substrate. CONSTITUTION: A method for manufacturing a laminated package comprises the steps of: preparing a tape wiring substrate(120) formed with a wiring pattern having beam leads on one surface of a polyimide tape; attaching the first semiconductor chips(110a) on a surface of the wiring substrate; attaching the second semiconductor chips(110b) on the surface of the substrate, the chips being spaced apart from the first semiconductor chips; joining the first and second semiconductor chips and the beam leads; sealing the joined portion of the chips and the beam leads to form a resin sealing; forming an adhering layer(160) on a bottom surface of the first semiconductor chips; bending the tape wiring substrate to opposite the bottom surface of the first semiconductor chips to a bottom surface of the second semiconductor chips, and adhering the adhering layer with the bottom surface of the second semiconductor chips; and forming an exterior connecting terminal on a surface of the substrate.

Description

Method for manufacturing stack package {Method for manufacturing stack package}

The present invention relates to a method for manufacturing a laminated package, and more particularly, to a method for manufacturing a laminated package in which a chip scale package using a tape wiring board is laminated.

The trend in today's electronics industry is to make products that are lighter, smaller, faster, more versatile, more powerful and more reliable. One of the important technologies that enables the goal setting of such a product design is a package technology, and thus a chip scale package (CSP) in a package developed in recent years.

Chip scale packages are manufactured to the size of semiconductor chips. In recent years, several types have been introduced from dozens of companies in the United States, Japan, Korea, etc., and development is being actively conducted. One of the representative chip scale packages is a micro-ball grid array (μ-BGA) package developed by Tessera's. Printed circuit boards applied to μ-BGA packages are tape wiring boards such as flexible and flexible circuit boards. In addition, one of the characteristics of the µ-BGA package is that beam lead is collectively bonded to the electrode pad of the semiconductor chip through a window formed in the tape wiring board.

1 is a cross-sectional view illustrating an example of a T-cera micro-BGA package as a typical chip scale package 100 including a tape wiring board 20. Referring to FIG. 1, a wiring pattern 23 formed on a polyimide tape 21 constitutes a tape wiring board 20, and an elastomer 30 includes a tape wiring board 20 and a semiconductor chip. It is interposed between (10). The beam lead 25 of the wiring pattern is collectively bonded to the electrode pad 12 of the semiconductor chip, and is connected to the connection hole 29 through the connection hole 29 formed in the polyimide tape 21. Solder bumps 70 are connected to the solder bump pads 124 of the wiring patterns exposed through them. The junction between the electrode pad 12 and the beam lead 25 and the outer portion of the semiconductor chip 10 are sealed with a molding resin to form a resin encapsulation 50. On the other hand, the semiconductor chip 10 is a center pad type semiconductor chip in which the electrode pad 12 is formed along the center line on the active surface, and the window 27 of the tape wiring board is the electrode pad 12 and the beam. The lead 25 is formed into a long hole along the portion where the electrode pad 11 is formed so that the lead 25 can be connected.

In addition to the chip scale package for packaging one semiconductor chip as described above, various methods have been proposed to reduce the size of a package, for example, a packaging technology in which a plurality of semiconductor chips or packages are three-dimensionally stacked. Packages implemented by this layered packaging technology are commonly referred to as stack packages.

However, the chip scale package as described above can only be mounted on a printed circuit board in a planar manner, and thus it is not easy to implement the stacked package. That is, since the solder bumps that can be utilized as external connection terminals of the chip scale package are formed on the surface opposite to the surface of the tape wiring board on which the semiconductor chip is mounted, and do not have other connection means, the existing chip scale package It is not easy to three-dimensionally stack a plurality of chip scale packages with the structure of.

Accordingly, an object of the present invention is to provide a method of manufacturing a laminated package in which a chip scale package using a tape wiring board is laminated.

Another object of the present invention is to provide a method of manufacturing a laminated package that can be implemented while utilizing the manufacturing process of a chip scale package using a tape wiring board as it is.

1 is a cross-sectional view showing an example of a tesla-BGA package of a typical chip scale package including a tape wiring board.

2 to 5 are views showing a manufacturing step of a laminated package using a tape wiring board according to an embodiment of the present invention,

2 is a plan view showing a state in which semiconductor chips are attached to a tape wiring board in two rows by n rows;

3 is a cross-sectional view taken along line 3-3 of FIG. 2, showing a state in which a resin suture is formed;

4 is a cross-sectional view showing a state in which an outer portion of the tape wiring board is well formed and an adhesive layer is formed on a lower surface of the first semiconductor chip;

5 is a cross-sectional view illustrating a state in which a bottom surface of a second semiconductor chip is attached to a bottom surface of a first semiconductor chip by folding a tape wiring board;

6 is a cross-sectional view showing a state in which solder bumps are formed;

7 is a cross-sectional view showing a state in which the tape wiring board is cut and separated into individual stacked packages;

8 is a cross-sectional view illustrating a state in which the stack package of FIG. 7 is stacked in two stages according to another embodiment of the present invention.

Description of the main parts of the drawing

110a, 110b: semiconductor chip 112a, 112b: electrode pad

120, 220: tape wiring board 123b: shared wiring pattern

130: elastomer 140, 240: solder bump

150: resin sealing portion 160: adhesive layer

170: cutting means 200, 200a, 200b: laminated package

300: two layer laminated package

In order to achieve the above object, the present invention relates to a laminated package using a tape wiring board, (A) preparing a tape wiring board having a wiring pattern including a plurality of beam leads on one surface of a flexible polyimide tape Wow; (B) attaching the first semiconductor chips to one surface of the tape wiring board in a row at predetermined intervals; (C) attaching second semiconductor chips to one surface of the tape wiring board in a row at predetermined intervals corresponding to the first semiconductor chips; (D) bonding the first and second semiconductor chips with the beam lead; (E) sealing each of the outer and outer portions of the first and second semiconductor chips to which the beam lead is connected to form a resin encapsulation unit; (F) forming an adhesive layer on a lower surface of the first semiconductor chip; (G) Fold the tape wiring board so that the bottom surface of the first semiconductor chip and the bottom surface of the second semiconductor chip face each other, and then the bottom surface of the second semiconductor chip on the adhesive layer of the bottom surface of the first semiconductor chip. Attaching each of them; And (H) forming an external connection terminal on a surface of the tape wiring board under the first semiconductor chip.

After step (E) according to the manufacturing method of the present invention, the method further includes cutting the tape wiring board including the resin encapsulation outside the first and second semiconductor chips.

Further, after the step (H) according to the manufacturing method of the present invention, the method further includes a step of cutting the tape wiring board portion between the first semiconductor chips in order to separate into individual stacked packages.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 to 7 are views illustrating a manufacturing step of a laminated package using a tape wiring board according to an embodiment of the present invention. The manufacturing steps of the laminated package according to the present invention will be described with reference to FIGS. 2 to 7. In addition, the same reference numerals represent the same components throughout the drawings.

First, as shown in FIGS. 2 and 3, the resin encapsulation unit 150 is formed by a conventional chip scale package manufacturing process using the tape wiring board 120.

First, a tape wiring board 120 including a polyimide tape 121 and a wiring pattern 123 formed by photolithography on one surface of the polyimide tape 121 is prepared. That is, the copper thin film is patterned by photolithography in a state where a copper foil is attached to one surface of the polyimide tape 121 to form a wiring pattern 123 including the beam lead 125. The window 127 is formed to expose the beam lid 125 at the central portion of the polyimide tape 121. A connection hole 129 is formed through the polyimide tape 121 so that a portion of the wiring pattern 123, that is, a disk shaped solder bump pad 124 on which solder bumps are to be exposed, is exposed. In addition, a gold (Au) plated film is formed on the exposed beam lead 125.

The tape wiring board 120 includes a window 127 including a wiring pattern 123 for mounting the semiconductor chips 110a and 110b in two rows by n columns (n: natural numbers), and the windows 127 in each column. Wiring patterns 123a (hereinafter, referred to as "shared wiring patterns") are formed to be shared. In FIG. 2, the semiconductor chips 110a and 110b are attached in two rows by three rows.

Next, the semiconductor chips 110a and 110b are attached in two rows by n rows on one surface of the tape wiring board 120 with the elastomer 130 interposed therebetween. 2, the semiconductor chip 110a in the upper row is referred to as a first semiconductor chip, and the semiconductor chip 110b in the lower row is referred to as a second semiconductor chip. The first and second semiconductor chips 110a and 110b are center pad type semiconductor chips in which the electrode pads 112a and 112b are formed along the center line of the active surface, and the window 127 of the tape wiring board is an electrode. Long holes are formed along portions where the electrode pads 112a and 112b are formed so that the pads 112a and 112b and the beam leads 125 can be connected.

Next, the electrode pads 112a and 112b of the first and second semiconductor chips and the beam leads 125 corresponding thereto are collectively bonded, and the bonded portion and the first and second semiconductor chips 110a and 110b are combined. The outer edge of the seal is sealed by the molding resin of the liquid to form a resin seal 150.

On the other hand, the process as described above proceeded in the same manner as the manufacturing process of the chip scale package using a conventional tape wiring board. However, the shared wiring pattern 123a is formed to implement the stack package, and the first and second semiconductor chips 110a and 110b are spaced at predetermined intervals so that the tape wiring board 120 can be folded in a process to be performed later. Spaced apart. The detailed description will be made in each subsequent process.

Next, as shown in FIG. 4, an adhesive layer 160 is formed on the lower surface of the first semiconductor chip 110a. As the material for forming the adhesive layer 160, both conductive or non-conductive adhesives may be used, or a polyimide tape having double-sided adhesiveness may be used. Meanwhile, in the embodiment of the present invention, although the adhesive layer 160 is formed on the bottom surface of the first semiconductor chip 110a, the adhesive layer is formed on the bottom surface of the second semiconductor chip 110b or the first and second semiconductor chips are formed. An adhesive layer may be formed on both lower surfaces of the 110a and 110b.

In addition, a portion of the resin encapsulation unit 150 outside the first and second semiconductor chips 110a and 110b may be included before or after the process of forming the adhesive layer 160 to minimize the size of the laminated package to be manufactured. The step of cutting the outer edge of the tape wiring board 120, that is, the tape wiring board 120 is performed. Reference numeral 151 denotes a cut surface of the outer portion of the tape wiring board 120 including the resin sealing portion 150.

Next, as shown in FIG. 5, a process of attaching the bottom surface of the second semiconductor chip 110b to the bottom surface of the first semiconductor chip 110a is performed. That is, the first semiconductor chip 110a and the second semiconductor chip 110b with the first semiconductor chip 110a and the second semiconductor chip 110b as the center of one surface of the tape wiring board 120 corresponding to the center. The bottom surface of the second semiconductor chip 110b is attached to the bottom surface of the first semiconductor chip 110a on which the adhesive layer 160 is formed by folding the tape wiring board 120 so that the bottom surfaces thereof face each other. At this time, the tape wiring board between the first semiconductor chip 110a and the second semiconductor chip 110b such that the lower surface of the second semiconductor chip 110b is positioned on the lower surface of the first semiconductor chip 110a. It is desirable to secure the portion 120.

Next, as shown in FIG. 6, metal bumps such as solder bumps 140 are formed in the connection holes 129 of the tape wiring board 120 on the first semiconductor chip 110a. That is, the flux is applied to the solder bump pads 124 exposed through the connection holes 129 and then connected to the solder bump pads 124 by raising and reflowing spherical solder balls. To form the solder bumps 140. Instead of the solder bumps 140, metal bumps such as nickel (Ni) or gold (Au) plating bumps may be formed.

In the exemplary embodiment of the present invention, the solder bumps 140 are formed on the first semiconductor chip 110a, but the solder bumps may be formed on the second semiconductor chip 110b. The first semiconductor chip 110a and the second semiconductor chip 110b have terminals electrically connected to each other by the shared wiring pattern 123a.

Finally, as shown in FIG. 7, the separating into individual stack packages 200 is performed. That is, the tape wiring board 120 between the first semiconductor chip 110a and the first semiconductor chip 110a in a state where the tape wiring board 120 is disposed so that the surface on which the solder bumps 140 are formed is facing upward. To cut by the cutting means 170 to separate the individual laminated package 200. At this time, in order to minimize the size of the stack package 200, it is necessary to cut the tape wiring board 120 including a part of the resin encapsulation unit 150 outside the first and second semiconductor chips 110a and 110b. desirable.

In FIG. 7, the tape wiring board 120 is illustrated in the row direction in order to show a state in which the tape wiring board 120 is well aligned in the column direction. In order to stack the stack package 200 on a printed circuit board, the solder bumps 140 may be connected to face down.

Meanwhile, in the exemplary embodiment of the present invention, the solder bump 140 is formed on one surface of the tape wiring board 120 on which two semiconductor chips 110a and 110b are mounted in the tape-shaped wiring board 120 having a zigzag shape. ) Is formed as a stack package 200, but as shown in FIG. 8, the stack package 200 may be implemented as a two-layer stack package 300 in which the stack packages 200a and 200b of FIG. 7 are stacked in two layers. In this case, the upper stack package 200b is referred to as an upper stack package, and the lower stack package 200a is referred to as a lower stack package. That is, the upper and lower laminated packages 200a are aligned in a state in which the solder bumps 240 of the upper laminated packages 200b are brought into the connection holes 129 of the tape wiring board 120 on the lower laminated packages 200a. It is possible to reflow the solder bumps 240 between and 200b to stack the upper and lower laminated packages 200a and 200b in two layers.

Alternatively, the solder balls are raised to the connection holes 129 of the tape wiring board on the lower laminated package 200a, and the connection holes of the tape wiring board 220 under the upper laminated package 200b on which the solder balls are not formed. The solder ball 240 may be reflowed in the state where the 229 is aligned to form the solder bumps 240 connected to the upper and lower connection holes 129 and 229, thereby implementing the two-layer stack package 300.

In FIG. 8, the multilayer package 300 is implemented in two layers, but it is obvious to those skilled in the art that the multilayer package 300 may be implemented in three or more layers.

Accordingly, according to the structure of the present invention, it is possible to implement a stack package in which a chip scale package using a tape wiring board is stacked. In addition, since the multilayer package can be implemented while using the manufacturing process of the chip scale package using the tape wiring board, additional cost can be reduced.

In the case of using a tape wiring board capable of mounting two rows by n rows of semiconductor chips, there is also an advantage in that n stacked packages can be simultaneously obtained.

Claims (3)

Regarding a laminated package using a tape wiring board, (A) preparing a tape wiring board having a wiring pattern including a plurality of beam leads on one surface of the flexible polyimide tape; (B) attaching the first semiconductor chips to one surface of the tape wiring board in a row at predetermined intervals; (C) attaching second semiconductor chips to one surface of the tape wiring board in a row at predetermined intervals corresponding to the first semiconductor chips; (D) bonding the first and second semiconductor chips with the beam lead; (E) sealing each of the outer and outer portions of the first and second semiconductor chips to which the beam lead is connected to form a resin encapsulation unit; (F) forming an adhesive layer on a lower surface of the first semiconductor chip; (G) Fold the tape wiring board so that the bottom surface of the first semiconductor chip and the bottom surface of the second semiconductor chip face each other, and then the bottom surface of the second semiconductor chip on the adhesive layer of the bottom surface of the first semiconductor chip. Attaching each of them; And (H) forming an external connection terminal on a surface of the tape wiring board under the first semiconductor chip. The method of claim 1, further comprising, after the step (E), cutting the tape wiring board including the resin encapsulation outside the first and second semiconductor chips. The method of claim 1, further comprising, after step (H), cutting out the tape wiring board portion between the first semiconductor chips to separate into individual stacked packages.