JPS582066Y2 - multilayer wiring board - Google Patents
multilayer wiring boardInfo
- Publication number
- JPS582066Y2 JPS582066Y2 JP1976100786U JP10078676U JPS582066Y2 JP S582066 Y2 JPS582066 Y2 JP S582066Y2 JP 1976100786 U JP1976100786 U JP 1976100786U JP 10078676 U JP10078676 U JP 10078676U JP S582066 Y2 JPS582066 Y2 JP S582066Y2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- conductor
- layer
- multilayer wiring
- conductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005476 soldering Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Description
【考案の詳細な説明】 本考案は多層厚膜配線板に関するものである。[Detailed explanation of the idea] The present invention relates to a multilayer thick film wiring board.
従来の多層厚膜1配線板は第1図及び第2図に示される
ように導電体回路の面積が多い層を一層目に設けてなる
ものが通常であり、各層間には絶縁層4を介して構成さ
れ、この場合半田付部分1、マウント部分2及びボンデ
ィング部分3を一層目に印刷した場合、二層目、三層目
と絶縁層及び各導体層を形成する場合の乾燥及び焼成工
程で高温にさらされる為、導電体部分の酸化が著しくな
り半田付性、マウント性、及びボンディング性が悪くな
るという問題が発生していた。Conventional multilayer thick film 1 wiring boards are usually formed by providing a layer with a large area of conductor circuits as the first layer, as shown in FIGS. 1 and 2, and an insulating layer 4 is provided between each layer. In this case, if the soldering part 1, the mounting part 2, and the bonding part 3 are printed on the first layer, the second and third layers, and the drying and baking process when forming the insulating layer and each conductor layer. Because they are exposed to high temperatures, the conductor portions are significantly oxidized, resulting in poor solderability, mountability, and bonding properties.
これらの理由から半田付部分1、マウント部分2及びポ
ンチ゛イング部分3の接着強度が低下し、品質低下の原
因になったり、酸化膜除去工程を設けて余分な工数をか
けて、原価を上げる原因になっていた。For these reasons, the adhesive strength of the soldering part 1, mount part 2, and punching part 3 decreases, causing quality deterioration, and adding an oxide film removal process, which requires extra man-hours and increases cost. It had become.
本考案は上述した問題を取り除き半田付性、マウント性
及びポンチ゛イング性を向上させ、高品質を提供し得る
多層厚膜配線板を提供することを目的とするものである
。The object of the present invention is to provide a multilayer thick film wiring board that can eliminate the above-mentioned problems, improve solderability, mounting performance, and punching performance, and provide high quality.
すなわち、本考案では半田付、マウント、ポンチ゛イン
グを行う導電体部分のみを導電体印刷工程の最終工程に
もってくることによって、すなわち最上層め導体層とし
て設けることにより乾燥炉、焼成炉にさらされる時間を
極力避けて酸化の影響を受けることなく半田付性、マウ
ント性及びボンディング性を向上させるものである。That is, in the present invention, by bringing only the conductor portion to be soldered, mounted, and punched to the final step of the conductor printing process, that is, by providing it as the topmost conductor layer, the time exposed to the drying oven and firing oven is reduced. The purpose is to improve solderability, mountability, and bonding properties without being affected by oxidation by avoiding oxidation as much as possible.
従って半田付、マウント及びボンディングを行う導電体
部分が乾燥炉及び焼成炉にさらされる時間が通常の一層
厚膜配線板と同しである為半田付性、マウント性及びボ
ンディング性をそこなうことなく、あるいは酸化膜除去
工程を設けることなく、品質を低下させることなくでき
、且つ原価的にも安いものができるものである。Therefore, the conductor parts that are soldered, mounted, and bonded are exposed to the drying oven and firing oven for the same amount of time as normal thick film wiring boards, so the soldering, mounting, and bonding properties are not impaired. Alternatively, it can be done without providing an oxide film removal process, without deteriorating quality, and at a low cost.
次に本考案の実施例について、第3図及び第4図を用い
て説明する。Next, an embodiment of the present invention will be described using FIGS. 3 and 4.
第3図は本考案によるセラミック基板10上に形成され
た2層の導体層からなる場合の多層厚膜配線板で半田付
導体部1.マウント導体部2及びボンディング導体部3
はガラスペーストの焼成により形成された絶縁層4を介
して2層目の導体層として設けられているものである。FIG. 3 shows a multilayer thick film wiring board consisting of two conductor layers formed on a ceramic substrate 10 according to the present invention, with soldered conductor portions 1. Mount conductor part 2 and bonding conductor part 3
is provided as a second conductor layer with an insulating layer 4 formed by firing glass paste interposed therebetween.
次に第4図により、かかる多層厚膜配線板の製造手順を
説明する。Next, the manufacturing procedure of such a multilayer thick film wiring board will be explained with reference to FIG.
まず、セラミック基板10上に導電性ペーストを半田付
部、ポンチ゛イング部、マウント部とは無関係なパター
ンのみについて塗布し、焼成することにより第1層の導
体層を形成する。First, a conductive paste is applied onto the ceramic substrate 10 only in a pattern unrelated to the soldering portion, punching portion, and mounting portion, and is fired to form a first conductive layer.
続いて、第2層の導体と交差する第1目層の導体層上に
ガラスペーストを塗布、焼成して絶縁層を形成する。Subsequently, a glass paste is applied onto the first layer conductor layer intersecting with the second layer conductor and baked to form an insulating layer.
(図示せず、第3図の4に対応。(Not shown, corresponds to 4 in Figure 3.
)次に半田付部1.マウント部2.ボンディング部3を
含む配線導体層を、導電性ペーストの塗布焼成により形
成し、更に抵抗体5を印刷することにより第3図に示し
た配線板は形成される。) Next, solder part 1. Mount part 2. The wiring board shown in FIG. 3 is formed by forming a wiring conductor layer including bonding portions 3 by applying and baking a conductive paste, and then printing resistors 5.
このようにして形成された配線板の半田付部1マウント
部2、ボンディング部3は製造工程における熱的影響、
等を受けていないので優れた接続性信゛頼性を有するも
のである。The soldering part 1 mount part 2 and bonding part 3 of the wiring board formed in this way are affected by thermal effects during the manufacturing process.
It has excellent connectivity reliability as it is not subject to
なお、本考案は上述した実施例に限定されるものではな
く、任意に形状、材質を変更し得るものであり、また3
層以上の導体層が形成されている場合にも有効である。Note that the present invention is not limited to the above-mentioned embodiments, and the shape and material may be changed as desired.
This method is also effective when more than one conductor layer is formed.
第1図は従来の多層厚膜基板の上平面図を示し第2図は
その主要部製造手順を説明する平面図である。
第3図は本考案による多層厚膜配線板の上平面図であり
、第4図は・その主要製造工程を説明する平面図である
。
図中の符号 10・・・・・・セラミック基板、1・・
・・・・半田付導体部、2・・・・・・マウント導体部
、3・、・・・・・ボンディング導体部、4・・・・・
・絶縁層、5・・・・・・抵抗体。FIG. 1 is a top plan view of a conventional multilayer thick film substrate, and FIG. 2 is a plan view illustrating the manufacturing procedure of its main parts. FIG. 3 is a top plan view of the multilayer thick film wiring board according to the present invention, and FIG. 4 is a plan view illustrating its main manufacturing process. Codes in the diagram 10...Ceramic substrate, 1...
...Soldering conductor part, 2...Mount conductor part, 3...Bonding conductor part, 4...
- Insulating layer, 5...Resistor.
Claims (1)
うち、上層の導体層と交差する部分は絶縁膜で覆われ、
該交差部分を除く大部分は該絶縁膜で覆われることなく
露出している多層配線板であって、該多層配線板上に搭
載される搭載部品と接続される部分の導体層が最上層の
導体層として形成されていることを特徴とする多層配線
板。A multilayer conductor layer is formed on the substrate, and the portion of the lower conductor layer that intersects with the upper conductor layer is covered with an insulating film.
Most of the multilayer wiring board except for the intersections is exposed without being covered with the insulating film, and the conductor layer in the part connected to the mounted components mounted on the multilayer wiring board is the uppermost layer. A multilayer wiring board characterized in that it is formed as a conductor layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1976100786U JPS582066Y2 (en) | 1976-07-27 | 1976-07-27 | multilayer wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1976100786U JPS582066Y2 (en) | 1976-07-27 | 1976-07-27 | multilayer wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5318566U JPS5318566U (en) | 1978-02-17 |
JPS582066Y2 true JPS582066Y2 (en) | 1983-01-13 |
Family
ID=28711026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1976100786U Expired JPS582066Y2 (en) | 1976-07-27 | 1976-07-27 | multilayer wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS582066Y2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4945909A (en) * | 1972-08-04 | 1974-05-02 | ||
JPS5065869A (en) * | 1973-10-17 | 1975-06-03 |
-
1976
- 1976-07-27 JP JP1976100786U patent/JPS582066Y2/en not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4945909A (en) * | 1972-08-04 | 1974-05-02 | ||
JPS5065869A (en) * | 1973-10-17 | 1975-06-03 |
Also Published As
Publication number | Publication date |
---|---|
JPS5318566U (en) | 1978-02-17 |
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