JPH02122594A - Circuit board device - Google Patents
Circuit board deviceInfo
- Publication number
- JPH02122594A JPH02122594A JP27662988A JP27662988A JPH02122594A JP H02122594 A JPH02122594 A JP H02122594A JP 27662988 A JP27662988 A JP 27662988A JP 27662988 A JP27662988 A JP 27662988A JP H02122594 A JPH02122594 A JP H02122594A
- Authority
- JP
- Japan
- Prior art keywords
- electrode land
- groove
- circuit board
- solder
- land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 abstract description 16
- 239000012212 insulator Substances 0.000 abstract description 10
- 239000004020 conductor Substances 0.000 abstract description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 2
- 239000006071 cream Substances 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 abstract 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、回路基板上に複数の電子部品を隣接して実装
する混成集積回路装置等の回路基板装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit board device such as a hybrid integrated circuit device in which a plurality of electronic components are mounted adjacently on a circuit board.
[従来の技術]
従来の混成集積回路装置は第4図及び第5図に示すよう
に、セラミックス等の絶縁性回路基板1の上に配線導体
2を設けると共に電極ランド3.4.5を設け、電子部
品6.7を半田8で固着することによって構成されてい
る。なお、2つの電子部品6.7は実装密度を高めるた
めに共通の電極ランド4に装着されている。第4図では
共通の電極ランド4が第1及び第2の部分4a、4bに
分割され、別々の電極ランドのように見えるが、半田流
れ止めのために設けた絶縁体9の下で第1及び第2の部
分4a、4bは相互に接続されている。斜線を付して示
す分離用絶縁体9はガラス等の被覆絶縁体10と同時に
印刷された部分である。[Prior Art] As shown in FIGS. 4 and 5, a conventional hybrid integrated circuit device has a wiring conductor 2 provided on an insulating circuit board 1 made of ceramic or the like, and electrode lands 3, 4, 5. , by fixing electronic components 6 and 7 with solder 8. Note that the two electronic components 6.7 are mounted on a common electrode land 4 in order to increase the mounting density. In FIG. 4, the common electrode land 4 is divided into first and second parts 4a and 4b, and although they look like separate electrode lands, the first part is separated under the insulator 9 provided to prevent solder flow. and the second portions 4a, 4b are interconnected. The isolation insulator 9 shown with diagonal lines is a portion printed at the same time as the covering insulator 10 such as glass.
もし、共通電極ランド4が絶縁体9で第1及び第2の部
分に分離されていなければ、一方の電子部品6の半田8
ど他方の電子部品7の半田8とがつながってしまい、富
士の裾野状に半田8を電子部品6.7に付着させること
が困雑になり、温度サイクル試験などを行うと電子部品
6.7に応力がかかり、クラック等の不良が発生する恐
れがある。If the common electrode land 4 is not separated into the first and second parts by the insulator 9, the solder 8 of one electronic component 6
The solder 8 of the other electronic component 7 will be connected, making it difficult to attach the solder 8 to the electronic component 6.7 in the shape of the foot of Fuji, and when a temperature cycle test etc. is performed, the electronic component 6.7 There is a risk that stress will be applied to the product and defects such as cracks will occur.
第4図及び第5図の分離絶縁体9を設ける代りに第1及
び第2の部分4a、4bの一部のみを接続し、残部をス
リットで分離する方法も知られている。Instead of providing the separating insulator 9 of FIGS. 4 and 5, a method is also known in which only a portion of the first and second portions 4a, 4b is connected and the remaining portion is separated by a slit.
[発明が解決しようとする課題]
ところで、回路基板装置の一層の小型化が要求されてい
る。第4図及び第5図に示すように絶縁体9をスクリー
ン印刷で量産的に設ける場合には、絶縁体9の幅を0.
411!l程度よりも小さくすることが困難であった。[Problems to be Solved by the Invention] By the way, there is a demand for further miniaturization of circuit board devices. When the insulator 9 is mass-produced by screen printing as shown in FIGS. 4 and 5, the width of the insulator 9 is set to 0.
411! It was difficult to make it smaller than about 1.
即ち、スクリーンの幅を0゜21としても両側に0.1
1Wl程度のダレが生じ、結局0.41程度の幅になっ
た。In other words, even if the width of the screen is 0°21, 0.1
A sag of about 1 Wl occurred, and the width ended up being about 0.41.
また、スリットによって第1及び第2の部分4a、4b
を分離する方法においても0.11!1111程度のス
リット幅が必要になった。また、第1及び第2の部分4
a、4bが一部で接続されるため半田の完全な分離が不
可能であった。In addition, the first and second portions 4a, 4b are formed by slits.
Even in the method of separating the slits, a slit width of about 0.11!1111 is required. In addition, the first and second parts 4
Since a and 4b were partially connected, it was impossible to completely separate the solder.
そこで、本発明の目的は高密度化が可能な回路基板装置
を提供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a circuit board device capable of increasing density.
[課題を解決するための手段]
上記目的を達成するための本発明は、複数の電子部品を
隣接して実装する為に前記複数の電子部品で共用する電
極ランドを有している回路基板装置において、前記共用
する電極ランドの厚さよりも浅い溝をレーザー光によっ
て設け、この清によって前記共用する電極ランドを前記
複数の電子部品に対応するように区画したことを特徴と
する回路基板装置に係わるものである。[Means for Solving the Problems] To achieve the above object, the present invention provides a circuit board device having an electrode land shared by a plurality of electronic components in order to mount the plurality of electronic components adjacent to each other. In the circuit board device, a groove shallower than the thickness of the shared electrode land is provided by a laser beam, and the shared electrode land is divided so as to correspond to the plurality of electronic components by this groove. It is something.
[作 用]
本発明の溝は電極ランドの厚さよりも浅く形成されてい
る。従って、溝の幅は全部を切断する場合に比べて小さ
くなり、例えば50μm〜100μmにすることができ
る。また、レーザービームによる渭であるので、熱によ
って電極ランドの材料の酸化膜が表面に形成される。清
の働きと酸化膜の働きとによって半田の流れを阻止する
ことができる。[Function] The groove of the present invention is formed to be shallower than the thickness of the electrode land. Therefore, the width of the groove is smaller than when cutting the entire groove, and can be, for example, 50 μm to 100 μm. Furthermore, since the laser beam is applied, an oxide film of the material of the electrode land is formed on the surface due to heat. The flow of solder can be prevented by the action of the oxidizer and the action of the oxide film.
[実施例]
次に、第1図〜第3図を参照して本発明の一実施例に係
わる回路基板装置を説明する。[Embodiment] Next, a circuit board device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3.
この回路基板装置を製造する際は、従来と同様にアルミ
ナ回路基板上にAQ−Pdペーストを印刷し、乾燥し、
焼成して配線導体2及び@極うンド3.4.5を形成す
る。When manufacturing this circuit board device, AQ-Pd paste is printed on an alumina circuit board, dried, and
The wiring conductor 2 and the electrode mold 3.4.5 are formed by firing.
次に、酸化ルテニウム(Ru 02 )系ペーストを印
刷し、乾燥し、焼成して抵抗体(図示せず)を形成した
ち、ガラスペーストを印刷し、乾燥し、焼成することに
よって第1図で斜線を付して示ず被覆絶縁体10を形成
する。Next, a ruthenium oxide (Ru 02 )-based paste is printed, dried, and fired to form a resistor (not shown), and a glass paste is printed, dried, and fired to form a resistor (see FIG. 1). The covered insulator 10 is not shown with diagonal lines.
次に、YAGレーザーを用いて、パワー1.5W、スピ
ード100 nn/sec 、パルス周波数10にHz
という条件でレーザーカット溝11を共通電極ランド4
の中央に形成し、第1及び第2の部分4a、4bに区画
する。渭11は第1図(B)に示すように共通電極ラン
ド4の一方の@縁から他方の端縁に至るように形成する
。この例では共通電極ランド4の膜厚が12μmであり
、?1111の深さ約10μmである。従って、第3図
に拡大して示すように第1の部分4aと第2の部分4b
とは渭11の下で相互に接続されている。レーザービー
ムを電極ランド4に投射すると、熱によって酸化され、
?ll!11の表面に第3図に示すように電極ランド4
の材料の酸化M!11 aが形成され、消11と酸化膜
11aが共用して半田流れ止め作用を発揮する。Next, using a YAG laser, the power was 1.5 W, the speed was 100 nn/sec, and the pulse frequency was 10 Hz.
Under these conditions, the laser cut groove 11 is connected to the common electrode land 4.
It is formed at the center of and divided into first and second parts 4a and 4b. The arm 11 is formed from one edge of the common electrode land 4 to the other edge as shown in FIG. 1(B). In this example, the film thickness of the common electrode land 4 is 12 μm, and ? The depth of 1111 is approximately 10 μm. Therefore, as shown enlarged in FIG. 3, the first portion 4a and the second portion 4b
and are interconnected under the river 11. When a laser beam is projected onto the electrode land 4, it is oxidized by heat,
? ll! As shown in FIG.
Oxidation of the material M! 11a is formed, and the eraser 11 and the oxide film 11a share a function of preventing solder flow.
次に、クリーム半田を電極ランド3.5及び電極ランド
4の第1及び第2の部分4a、4bに厚さ0.2nnに
塗布し、この上に積層コンデンサから成る電子部品6.
7を配置し、230℃でリフローを行い、第2図に示す
ように半田8による接続を達成する。Next, cream solder is applied to the electrode land 3.5 and the first and second portions 4a and 4b of the electrode land 4 to a thickness of 0.2 nn, and an electronic component 6.
7 is placed and reflowed at 230° C. to achieve connection by solder 8 as shown in FIG.
なお、独立の電極ランド3.5の寸法はllllX21
1Mであり、共通電極ランド4の寸法は211+1X2
101である。共通電極ランド4は7!411で区画さ
れるが湧11の幅は50〜100μm程度と極めて狭い
ので、第1及び第2の部分4a、4bは独立の電極ラン
ド3.5とほぼ同一の寸法となり、第2図に示すように
電子部品6.7の両端面及び端面近傍外周にキャップ状
に設けられた電@6a、6b、7a、7bは互いにほぼ
同一形状の富士の裾野状半田8により安定的に接続され
る。In addition, the dimensions of the independent electrode land 3.5 are llllx21
1M, and the dimensions of the common electrode land 4 are 211+1X2
It is 101. The common electrode land 4 is divided by 7!411, but the width of the spring 11 is extremely narrow, about 50 to 100 μm, so the first and second portions 4a, 4b have almost the same dimensions as the independent electrode land 3.5. As shown in FIG. 2, the cap-like cap-shaped caps 6a, 6b, 7a, and 7b on both end faces and the outer periphery of the electronic component 6.7 are connected by Fuji's foot-shaped solder 8, which has almost the same shape as each other. Connected stably.
[発明の効果]
上述から明らかなように本発明によれば、極めて幅の狭
い溝によって共通の電極ランドを区画し、半田の流れを
阻止することができる。従って、高密度実装及び小型化
が可能になる。[Effects of the Invention] As is clear from the above, according to the present invention, common electrode lands can be divided by extremely narrow grooves and the flow of solder can be prevented. Therefore, high-density packaging and miniaturization are possible.
第1図は消を設ける前の回路基板と溝を設けた後の回路
基板の一部を示す平面図、
第2図は第1図(B)の■−■線に相当する部分の電子
部品装着後の状態を示す断面図、第3図は第1図(B)
の■−■線の拡大断面図、第4図は従来の回路基板の一
部を示す平面図、第5図は第4図の回路基板に電子部品
を装着した後の断面図である。
1・・・回路基板、2・・・配線導体、3,4.5・・
・電極ランド、6.7・・・電子部品、8・・・半田、
10・・・被覆絶縁体、11・・・清。Figure 1 is a plan view showing a part of the circuit board before the eraser is provided and after the groove is provided, and Figure 2 is the electronic component in the part corresponding to the line ■-■ in Figure 1 (B). A sectional view showing the state after installation, Figure 3 is Figure 1 (B)
FIG. 4 is a plan view showing a part of a conventional circuit board, and FIG. 5 is a sectional view of the circuit board shown in FIG. 4 after electronic components are mounted thereon. 1... Circuit board, 2... Wiring conductor, 3, 4.5...
・Electrode land, 6.7...Electronic component, 8...Solder,
10...Covered insulator, 11...Clear.
Claims (1)
子部品で共用する電極ランドを有している回路基板装置
において、 前記共用する電極ランドの厚さよりも浅い溝をレーザ
ー光によって設け、この溝によって前記共用する電極ラ
ンドを前記複数の電子部品に対応するように区画したこ
とを特徴とする回路基板装置。[Claims] In a circuit board device having an electrode land shared by the plurality of electronic parts in order to mount a plurality of electronic parts adjacent to each other, a groove shallower than the thickness of the shared electrode land is formed. A circuit board device, characterized in that the shared electrode land is divided by the groove formed by a laser beam so as to correspond to the plurality of electronic components.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27662988A JPH02122594A (en) | 1988-10-31 | 1988-10-31 | Circuit board device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27662988A JPH02122594A (en) | 1988-10-31 | 1988-10-31 | Circuit board device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02122594A true JPH02122594A (en) | 1990-05-10 |
Family
ID=17572105
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27662988A Pending JPH02122594A (en) | 1988-10-31 | 1988-10-31 | Circuit board device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02122594A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008207207A (en) * | 2007-02-26 | 2008-09-11 | Fuji Electric Device Technology Co Ltd | Method for solder joining, and method for manufacturing semiconductor device using the same |
JP2009004612A (en) * | 2007-06-22 | 2009-01-08 | Nippon Seiki Co Ltd | Printed wiring board |
US10999927B2 (en) | 2016-11-11 | 2021-05-04 | Murata Manufacturing Co., Ltd. | Ceramic substrate and method for manufacturing ceramic substrate |
-
1988
- 1988-10-31 JP JP27662988A patent/JPH02122594A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008207207A (en) * | 2007-02-26 | 2008-09-11 | Fuji Electric Device Technology Co Ltd | Method for solder joining, and method for manufacturing semiconductor device using the same |
US8273644B2 (en) | 2007-02-26 | 2012-09-25 | Fuji Electric Co., Ltd. | Soldering method and method of manufacturing semiconductor device including soldering method |
JP2009004612A (en) * | 2007-06-22 | 2009-01-08 | Nippon Seiki Co Ltd | Printed wiring board |
US10999927B2 (en) | 2016-11-11 | 2021-05-04 | Murata Manufacturing Co., Ltd. | Ceramic substrate and method for manufacturing ceramic substrate |
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