JPH118157A - Manufacture of laminated electronic component - Google Patents
Manufacture of laminated electronic componentInfo
- Publication number
- JPH118157A JPH118157A JP9160009A JP16000997A JPH118157A JP H118157 A JPH118157 A JP H118157A JP 9160009 A JP9160009 A JP 9160009A JP 16000997 A JP16000997 A JP 16000997A JP H118157 A JPH118157 A JP H118157A
- Authority
- JP
- Japan
- Prior art keywords
- laminated
- electronic component
- conductive material
- sheets
- aggregate board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004020 conductor Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000005520 cutting process Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 40
- 238000010030 laminating Methods 0.000 claims description 2
- 239000002648 laminated material Substances 0.000 abstract 4
- 239000012212 insulator Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 238000007606 doctor blade method Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 235000019219 chocolate Nutrition 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Manufacturing Cores, Coils, And Magnets (AREA)
- Coils Or Transformers For Communication (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、回路要素を内部に
配置した積層電子部品の製造方法に関し、特に、積層電
子部品の外部電極の製造方法の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer electronic component having circuit elements arranged therein, and more particularly to an improvement in a method for manufacturing external electrodes of the multilayer electronic component.
【0002】[0002]
【従来の技術】図7に、従来の積層電子部品の斜視図を
示す。例えば、積層コンデンサ、積層インダクタ、多層
回路基板、多層複合電子部品で代表される積層電子部品
50は、図示したチップ状の形態で適宜の回路基板上に
実装されるが、図7では、このような回路基板側に向け
られる面を上方に向けた状態で、積層電子部品50が図
示されている。積層電子部品50は、内部回路要素(図
示せず)を介在させた状態で複数の絶縁性シートが積層
されてなる積層体51を備える。積層体51の4つの側
面の各々には、積層体51の外表面に露出する外部電極
52が形成される。これらの外部電極52は、絶縁体シ
ートに設けられ、かつ導電材が充填されたビアホールの
少なくとも側部を絶縁体シートの切断によって露出する
ことによって形成されるとともに、図示しないが、内部
回路要素に電気的に接続される。また、積層体51の4
つの側面の各々には、段差53が形成される。2. Description of the Related Art FIG. 7 is a perspective view of a conventional laminated electronic component. For example, a multilayer electronic component 50 typified by a multilayer capacitor, a multilayer inductor, a multilayer circuit board, and a multilayer composite electronic component is mounted on an appropriate circuit board in the form of a chip as shown in FIG. The laminated electronic component 50 is illustrated with the surface facing the circuit board side facing upward. The laminated electronic component 50 includes a laminated body 51 in which a plurality of insulating sheets are laminated with an internal circuit element (not shown) interposed. On each of the four side surfaces of the multilayer body 51, an external electrode 52 exposed on the outer surface of the multilayer body 51 is formed. These external electrodes 52 are formed by exposing at least side portions of the via holes filled with the conductive material by cutting the insulator sheet, and formed on the insulator sheet. Electrically connected. In addition, 4 of the laminate 51
A step 53 is formed on each of the two side surfaces.
【0003】上述のような積層電子部品50を得るため
に以下のような工程が実施される。まず、ドクターブレ
ード法などにより、シート成形を行い、マザー絶縁性シ
ートを得る。これらマザー絶縁性シートの特定のものに
は、シートを厚み方向に貫通するビアホールがパンチン
グ等により形成される。次いで、マザー絶縁性シートの
特定のものの上には、内部回路要素となるべき導電膜、
抵抗膜等が印刷される。このとき、すでに形成されたビ
アホール内に、導電材が充填される。次いで、これらの
マザー絶縁性シートが積み重ねられ、プレスされること
により、集合基板が得られる。次いで、この集合基板に
は、少なくともビアホールが分断されるように、切断線
に沿って溝がダイシングソーによって形成される。この
溝によって、溝の内側にビアホール内の導電材が露出す
ることとなる。次いで、集合基板は、マザー絶縁性シー
トを焼結させるため、焼成され、その後、集合基板は溝
に沿って完全に切断される。このようにして、溝の内側
にビアホール内の導電材が露出することにより形成され
た外部電極52を備える積層電子部品50(図7)が得
られる。なお、段差53は、前述した溝の形成の結果も
たらされたものである。In order to obtain the above-described laminated electronic component 50, the following steps are performed. First, a sheet is formed by a doctor blade method or the like to obtain a mother insulating sheet. In certain of these mother insulating sheets, via holes penetrating the sheet in the thickness direction are formed by punching or the like. Next, on a specific one of the mother insulating sheets, a conductive film to be an internal circuit element,
A resistive film or the like is printed. At this time, the conductive material is filled in the via holes already formed. Next, these mother insulating sheets are stacked and pressed to obtain a collective substrate. Next, a groove is formed in the assembly substrate along a cutting line by a dicing saw so that at least the via hole is divided. With this groove, the conductive material in the via hole is exposed inside the groove. Next, the collective substrate is fired to sinter the mother insulating sheet, and thereafter, the collective substrate is completely cut along the grooves. In this way, a multilayer electronic component 50 (FIG. 7) including the external electrode 52 formed by exposing the conductive material in the via hole inside the groove is obtained. Note that the step 53 is obtained as a result of the formation of the groove described above.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、上述し
た積層電子部品においては、積層電子部品を構成する集
合基板の厚みが低背化の要求により、1.0mm以下の
ものが主流であり、その際の溝の深さは0.2〜0.5
mmである。したがって、残り代が0.5〜0.8mm
程度しかなく、集合基板の状態で、溝形成後の工程、例
えば表面上に配線パターンを印刷する工程、印刷抵抗を
印刷、トリミングする工程などを実施すると、集合基板
が割れてしまうという問題があった。However, in the above-mentioned multilayer electronic component, the thickness of an aggregate substrate constituting the multilayer electronic component is 1.0 mm or less due to a demand for a reduction in height. Groove depth is 0.2 ~ 0.5
mm. Therefore, the remaining allowance is 0.5 to 0.8 mm
In the state of the collective substrate, if a process after forming a groove, for example, a process of printing a wiring pattern on the surface, a process of printing a print resistor, or a process of trimming, is performed, there is a problem that the collective substrate is broken. Was.
【0005】また、集合基板の溝は、ダイシングソーを
用いて焼成前に形成されるが、その際にダイシングソー
の焼き付き防止のため、集合基板に水をかける。したが
って、焼成前の集合基板が水分を含むため、集合基板を
構成するマザー絶縁性シートが剥がれたり、内部回路要
素を構成する導電材が酸化してしまうという問題もあっ
た。The grooves of the collective substrate are formed before firing using a dicing saw. At this time, water is applied to the collective substrate to prevent seizure of the dicing saw. Therefore, since the collective substrate before firing contains moisture, there has been a problem that the mother insulating sheet forming the collective substrate is peeled off or the conductive material forming the internal circuit element is oxidized.
【0006】本発明は、このような問題点を解消するた
めになされたものであり、集合基板の状態で工程ライン
に流す際に、集合基板に割れが生じない積層電子部品の
製造方法を提供することを目的とする。The present invention has been made to solve such a problem, and provides a method of manufacturing a laminated electronic component in which a crack is not generated in a collective substrate when the collective substrate is caused to flow through a process line in a state of the collective substrate. The purpose is to do.
【0007】[0007]
【課題を解決するための手段】上述の問題点を解決する
ため本発明の積層電子部品の製造方法は、所定の切断線
によって区画される各領域に設けられる積層電子部品の
製造方法であって、複数のマザー絶縁性シートを用意す
る工程と、前記複数のマザー絶縁性シートの所定の位置
にビアホールを形成する工程と、前記複数のマザー絶縁
性シート上に導電材を印刷して前記各領域に内部回路要
素を形成する工程と、前記ビアホールに外部電極となる
導電材を付与する工程と、前記ビアホールの少なくとも
側部が露出するように前記複数のマザー絶縁性シートに
打ち抜き部を形成する工程と、前記複数のマザー絶縁性
シートを積層、圧着して集合基板を形成する工程と、前
記集合基板を前記切断線に沿って切断する工程とを備え
ることを特徴とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a method of manufacturing a multilayer electronic component according to the present invention is a method of manufacturing a multilayer electronic component provided in each area defined by a predetermined cutting line. Preparing a plurality of mother insulating sheets, forming via holes at predetermined positions of the plurality of mother insulating sheets, and printing a conductive material on the plurality of mother insulating sheets to form the respective regions. Forming an internal circuit element, providing a conductive material to be an external electrode to the via hole, and forming a punched portion in the plurality of mother insulating sheets so that at least a side portion of the via hole is exposed. And laminating and pressing the plurality of mother insulating sheets to form an aggregate substrate; and cutting the aggregate substrate along the cutting line. .
【0008】本発明の積層電子部品の製造方法によれ
ば、外部電極が設けられる打ち抜き部が、集合基板にお
いて、断続的あるいは部分的に存在するため、打ち抜き
部を深くして残り代を少なくしても、集合基板で製造工
程を流す際に集合基板に割れが生じない。According to the method of manufacturing a laminated electronic component of the present invention, since the punched portion provided with the external electrode is intermittent or partially present in the collective substrate, the punched portion is deepened to reduce the remaining margin. Even when the manufacturing process is performed on the collective substrate, no crack occurs in the collective substrate.
【0009】[0009]
【発明の実施の形態】以下、図面を参照して本発明の実
施例を説明する。図1に、本発明に係る積層電子部品の
一実施例の斜視図を示す。積層電子部品10は、図示し
たチップ状の形態で適宜の回路基板上に実装されるが、
図1では、積層電子部品10の下面、すなわちこのよう
な回路基板側に向けられる面を上方に向けた状態で、図
示されている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a perspective view of one embodiment of a laminated electronic component according to the present invention. The multilayer electronic component 10 is mounted on an appropriate circuit board in the illustrated chip shape.
FIG. 1 illustrates a state in which the lower surface of the multilayer electronic component 10, that is, the surface directed toward the circuit board, faces upward.
【0010】積層電子部品10は、回路要素(図示せ
ず)を内部に介在させた状態で複数の絶縁性シートが積
層されてなる積層体11を備える。積層体11の例えば
4つの側面の各々には、段差12が設けられ、その段差
12の側面12aに露出するように、積層体11の一方
主面111で略半円状になる外部電極13が形成され
る。これら外部電極13は、図示しないが、内部回路要
素に電気的に接続される。The laminated electronic component 10 includes a laminated body 11 in which a plurality of insulating sheets are laminated with a circuit element (not shown) interposed therebetween. For example, a step 12 is provided on each of the four side surfaces of the laminated body 11, and an external electrode 13 which is formed in a substantially semicircular shape on one main surface 111 of the laminated body 11 so as to be exposed on the side surface 12 a of the step 12 It is formed. Although not shown, these external electrodes 13 are electrically connected to internal circuit elements.
【0011】上述したような、積層電子部品10を得る
ための製造方法を図2を用いて説明する。まず、ドクタ
ーブレード法などによりシート成形を行い、複数のマザ
ー絶縁性シート14a〜14eを用意する(図2
(a))。A manufacturing method for obtaining the laminated electronic component 10 as described above will be described with reference to FIG. First, a sheet is formed by a doctor blade method or the like to prepare a plurality of mother insulating sheets 14a to 14e (FIG. 2).
(A)).
【0012】次いで、これら複数のマザー絶縁性シート
14a〜14eの内、マザー絶縁性シート14b〜14
eの所定の位置に、シートの厚み方向に貫通するビアホ
ール15、16がパンチングなどにより形成される(図
2(b))。なお、ビアホール15は内部回路要素を接
続するためのものであり、ビアホール16は外部電極1
3となるためのものである。Next, of the plurality of mother insulating sheets 14a to 14e, the mother insulating sheets 14b to 14e are provided.
Via holes 15 and 16 penetrating in the thickness direction of the sheet are formed at predetermined positions e by punching or the like (FIG. 2B). The via hole 15 is for connecting internal circuit elements, and the via hole 16 is for connecting the external electrode 1.
It is to become 3.
【0013】次いで、複数のマザー絶縁性シート14a
〜14eの内、マザー絶縁性シート14b〜14c上
に、導電材を印刷して、内部回路要素となる導電膜17
が形成され、マザー絶縁体シート14b〜14eのビア
ホール15、16内に導電材が充填される(図2
(c))。Next, a plurality of mother insulating sheets 14a are provided.
Conductive material 17 is printed on mother insulating sheets 14b to 14c to form an internal circuit element.
Are formed, and the via holes 15 and 16 of the mother insulator sheets 14b to 14e are filled with a conductive material (FIG. 2).
(C)).
【0014】次いで、マザー絶縁性シート14d、14
eに形成されるとともに、内部に導電材が充填されたビ
アホール16の側部16aが露出するように、シートの
厚み方向に貫通した打ち抜き部18がパンチングなどに
より形成される(図2(d))。Then, the mother insulating sheets 14d, 14
e, and a punched portion 18 is formed by punching or the like so as to expose the side portion 16a of the via hole 16 filled with the conductive material therein so as to be exposed in the thickness direction of the sheet (FIG. 2D). ).
【0015】次いで、複数のマザー絶縁性シート14a
〜14eが積み重ねられ、プレスされる。これによっ
て、集合基板19が形成される(図2(e))。Next, a plurality of mother insulating sheets 14a are provided.
-14e are stacked and pressed. Thus, the collective substrate 19 is formed (FIG. 2E).
【0016】そして、図3に示すように、機械的に独立
した複数の積層電子部品10を得るために、集合基板1
9は、切断線20に沿って集合基板19の表面及び裏面
に設けられたスリット21、22を利用して完全に分割
される。この分割は、チョコレートを割るように、集合
基板19を切断線20に沿って割ることにより容易に達
成される。なお、一般的に、集合基板19から分割され
た後、積層回路基板10の状態で焼成されるが、集合基
板19の状態で焼成した後、積層回路基板10に分割し
てもよい。Then, as shown in FIG. 3, in order to obtain a plurality of mechanically independent laminated electronic components 10, the collective substrate 1
9 is completely divided along slits 20 using slits 21 and 22 provided on the front and back surfaces of the collective substrate 19. This division is easily achieved by breaking the aggregate substrate 19 along the cutting line 20 like breaking a chocolate. In addition, generally, after being divided from the collective substrate 19, it is baked in the state of the laminated circuit board 10, but may be baked in the state of the collective substrate 19 and then divided into the laminated circuit board 10.
【0017】以上述べた製造方法からもわかるように、
段差12は前述した打ち抜き部18を形成した(図2
(d))結果もたらされたものである。また、外部電極
13は、内部に導電材が充填されたビアホール16の側
部16aが露出するように、打ち抜き部18を設けた
(図2(d))結果もたらされたものである。As can be seen from the manufacturing method described above,
The step 12 formed the punched portion 18 described above (FIG. 2).
(D)) resulting. The external electrode 13 is obtained as a result of providing the punched portion 18 so that the side portion 16a of the via hole 16 filled with the conductive material is exposed (FIG. 2D).
【0018】上述の実施例によれば、外部電極が設けら
れる打ち抜き部が、集合基板において、断続的あるいは
部分的に存在するため、打ち抜き部を深くして残り代を
少なくしても、集合基板の状態で工程ラインに流す際
に、集合基板に割れが生じない。したがって、集合基板
を薄くすることができ、その結果、積層電子部品の低背
化が可能となる。According to the above-described embodiment, since the punched portion provided with the external electrode is intermittent or partially present in the collective substrate, even if the punched portion is deepened to reduce the remaining margin, the collective substrate When flowing into the process line in the state of (1), no crack occurs in the collective substrate. Therefore, the thickness of the collective substrate can be reduced, and as a result, the height of the multilayer electronic component can be reduced.
【0019】また、ダイシングソーを用いて集合基板に
溝を設けることがないので、製造工程中において、水を
使用する必要がなく、その結果、集合基板を構成するマ
ザー絶縁性シートの剥がれや、内部回路要素を構成する
導電材の酸化を防止することができる。Further, since no groove is formed in the collective substrate using a dicing saw, it is not necessary to use water during the manufacturing process, and as a result, the mother insulating sheet constituting the collective substrate may be peeled off, Oxidation of the conductive material forming the internal circuit element can be prevented.
【0020】さらに、外部電極となるべき導電材が充填
されたビアホールがマザー絶縁性シートにすでに設けら
れ、このマザー絶縁シートに打ち抜き部を設けることに
より、導電材が露出して外部電極となるため、外部電極
を設けるための特別な工程が不要となる。Further, a via hole filled with a conductive material to be an external electrode is already provided in the mother insulating sheet, and by providing a punched portion in the mother insulating sheet, the conductive material is exposed and becomes an external electrode. In addition, a special process for providing an external electrode is not required.
【0021】なお、本発明を図1及び図2に示した実施
例に関して説明したが、本発明の範囲内において、その
他いくつかの変形例が可能である。Although the present invention has been described with reference to the embodiment shown in FIGS. 1 and 2, some other modifications are possible within the scope of the present invention.
【0022】例えば、図4に示す積層電子部品10aの
ように、積層体11の一方主面111で略U字状になる
外部電極13aを備えていてもよい。この外部電極13
aは、略円形状のビアホールの側壁に導電材を塗布し、
そのビアホールの側部が露出するように打ち抜き部を設
けることにより形成される。For example, like a laminated electronic component 10a shown in FIG. 4, an external electrode 13a which is substantially U-shaped on one main surface 111 of the laminated body 11 may be provided. This external electrode 13
a, a conductive material is applied to the side wall of the substantially circular via hole,
It is formed by providing a punched portion so that the side portion of the via hole is exposed.
【0023】また、図5に示す積層電子部品10bのよ
うに、積層体11の一方主面111で略矩形状になる外
部電極13bを備えていてもよい。この外部電極13b
は、略矩形状のビアホールに導電材を充填し、そのビア
ホールの側部が露出するように打ち抜き部を設けること
により形成される。Further, like a laminated electronic component 10b shown in FIG. 5, an external electrode 13b having a substantially rectangular shape on one main surface 111 of the laminated body 11 may be provided. This external electrode 13b
Is formed by filling a substantially rectangular via hole with a conductive material and providing a punched portion so that a side portion of the via hole is exposed.
【0024】さらに、図6に示す積層電子部品10cの
ように、1つの段差12cごとに1つの外部電極13が
設けられてもよい。この構造は、略円形状のビアホール
に導電材を充填し、そのビアホール1つ1つに対して、
打ち抜き部を1つ1つ設けることにより形成される。こ
の場合には、はんだを用いて回路基板上に実装する際
に、はんだが段差12cからはみ出さないため、外部電
極の間隔を狭めることができる。その結果、積層電子部
品10cが小型化する。Further, as in a laminated electronic component 10c shown in FIG. 6, one external electrode 13 may be provided for each step 12c. In this structure, a substantially circular via hole is filled with a conductive material, and each of the via holes is filled with a conductive material.
It is formed by providing one punched portion one by one. In this case, since the solder does not protrude from the step 12c when mounted on the circuit board using the solder, the interval between the external electrodes can be reduced. As a result, the size of the multilayer electronic component 10c is reduced.
【0025】[0025]
【発明の効果】本発明の積層電子部品の製造方法によれ
ば、外部電極が設けられる打ち抜き部が、集合基板にお
いて、断続的あるいは部分的に存在するため、打ち抜き
部を深くして残り代を少なくしても、集合基板の状態で
工程ラインに流す際に、集合基板に割れが生じない。し
たがって、集合基板を薄くすることができ、その結果、
積層電子部品の低背化が可能となる。According to the method of manufacturing a multilayer electronic component of the present invention, the punched portion provided with the external electrode is intermittent or partially present in the collective substrate. Even if the number is reduced, no crack occurs in the collective substrate when flowing the process line in the state of the collective substrate. Therefore, the collective substrate can be made thin, and as a result,
The height of the laminated electronic component can be reduced.
【0026】また、ダイシングソーを用いて集合基板に
溝を設けることがないので、製造工程中において、水を
使用しないため、集合基板を構成するマザー絶縁性シー
トの剥がれや、内部回路要素を構成する導電材の酸化を
防止することができる。Further, since no groove is formed in the collective substrate using a dicing saw, no water is used during the manufacturing process, so that the mother insulating sheet constituting the collective substrate may be peeled off or the internal circuit elements may not be formed. Oxidation of the conductive material can be prevented.
【0027】さらに、外部電極となるべき導電材が充填
されたビアホールがマザー絶縁性シートにすでに設けら
れ、このマザー絶縁シートに打ち抜き部を設けることに
より、導電材が露出して外部電極となるため、外部電極
を設けるための特別な工程が不要となる。Further, a via hole filled with a conductive material to be an external electrode is already provided in the mother insulating sheet, and a punched portion is provided in the mother insulating sheet, so that the conductive material is exposed and becomes an external electrode. In addition, a special process for providing an external electrode is not required.
【図1】本発明に係る積層電子部品の一実施例を示す斜
視図である。FIG. 1 is a perspective view showing one embodiment of a laminated electronic component according to the present invention.
【図2】図1に示した積層電子部品を得るための製造工
程を示す断面図である。FIG. 2 is a cross-sectional view showing a manufacturing process for obtaining the multilayer electronic component shown in FIG.
【図3】図2(e)に示した集合基板を示す拡大斜視図
である。FIG. 3 is an enlarged perspective view showing the collective substrate shown in FIG.
【図4】図1に示した積層電子部品の変形例を示す斜視
図である。FIG. 4 is a perspective view showing a modification of the multilayer electronic component shown in FIG.
【図5】図1に示した積層電子部品の別の変形例を示す
斜視図である。FIG. 5 is a perspective view showing another modified example of the multilayer electronic component shown in FIG.
【図6】図1に示した積層電子部品のさらに別の変形例
を示す斜視図である。FIG. 6 is a perspective view showing still another modification of the multilayer electronic component shown in FIG.
【図7】従来の積層電子部品を示す斜視図である。FIG. 7 is a perspective view showing a conventional laminated electronic component.
10、10a、10b、10c 積層電子部品 13 外部電極 14a〜14e マザー絶縁性シート 16 ビアホール 16a 側部 17 内部回路要素(導電膜) 18 打ち抜き部 19 集合基板 20 切断線 DESCRIPTION OF SYMBOLS 10, 10a, 10b, 10c Multilayer electronic component 13 External electrode 14a-14e Mother insulating sheet 16 Via hole 16a Side part 17 Internal circuit element (conductive film) 18 Punched part 19 Assembly board 20 Cutting line
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 FI H01G 4/12 364 H01F 15/10 C H05K 3/46 H01G 1/14 V ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification code FI H01G 4/12 364 H01F 15/10 C H05K 3/46 H01G 1/14 V
Claims (1)
に設けられる積層電子部品の製造方法であって、 複数のマザー絶縁性シートを用意する工程と、前記複数
のマザー絶縁性シートの所定の位置にビアホールを形成
する工程と、前記複数のマザー絶縁性シート上に導電材
を印刷して前記各領域に内部回路要素を形成する工程
と、前記ビアホールに外部電極となる導電材を付与する
工程と、前記ビアホールの少なくとも側部が露出するよ
うに前記複数のマザー絶縁性シートに打ち抜き部を形成
する工程と、前記複数のマザー絶縁性シートを積層、圧
着して集合基板を形成する工程と、前記集合基板を前記
切断線に沿って切断する工程とを備えることを特徴とす
る積層電子部品の製造方法。1. A method for manufacturing a laminated electronic component provided in each area defined by a predetermined cutting line, comprising: providing a plurality of mother insulating sheets; Forming a via hole at a position, printing a conductive material on the plurality of mother insulating sheets to form an internal circuit element in each of the regions, and providing a conductive material serving as an external electrode to the via hole Forming a punched portion in the plurality of mother insulating sheets so that at least side portions of the via holes are exposed, and laminating and bonding the plurality of mother insulating sheets to form a collective substrate, and Cutting the collective substrate along the cutting line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16000997A JP3425711B2 (en) | 1997-06-17 | 1997-06-17 | Manufacturing method of laminated electronic components |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16000997A JP3425711B2 (en) | 1997-06-17 | 1997-06-17 | Manufacturing method of laminated electronic components |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH118157A true JPH118157A (en) | 1999-01-12 |
JP3425711B2 JP3425711B2 (en) | 2003-07-14 |
Family
ID=15706012
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16000997A Expired - Lifetime JP3425711B2 (en) | 1997-06-17 | 1997-06-17 | Manufacturing method of laminated electronic components |
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JP (1) | JP3425711B2 (en) |
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US6751101B2 (en) | 2000-11-02 | 2004-06-15 | Murata Manufacturing Co., Ltd. | Electronic component and method of producing the same |
US6760227B2 (en) | 2000-11-02 | 2004-07-06 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component and manufacturing method thereof |
CN102300384A (en) * | 2010-06-23 | 2011-12-28 | 环旭电子股份有限公司 | Multi-layer printed circuit board |
JP2012174713A (en) * | 2011-02-17 | 2012-09-10 | Kyocera Corp | Electronic component housing package, and electronic equipment including the same |
WO2015033788A1 (en) * | 2013-09-04 | 2015-03-12 | 株式会社 村田製作所 | Method for manufacturing laminated electronic component |
JP2016006846A (en) * | 2014-05-27 | 2016-01-14 | 京セラ株式会社 | Wiring board and electronic apparatus |
WO2017217308A1 (en) * | 2016-06-17 | 2017-12-21 | 株式会社村田製作所 | Electronic component, vibration plate, electronic device, and method for manufacturing electronic components |
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1997
- 1997-06-17 JP JP16000997A patent/JP3425711B2/en not_active Expired - Lifetime
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US6751101B2 (en) | 2000-11-02 | 2004-06-15 | Murata Manufacturing Co., Ltd. | Electronic component and method of producing the same |
US6760227B2 (en) | 2000-11-02 | 2004-07-06 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component and manufacturing method thereof |
CN102300384A (en) * | 2010-06-23 | 2011-12-28 | 环旭电子股份有限公司 | Multi-layer printed circuit board |
JP2012174713A (en) * | 2011-02-17 | 2012-09-10 | Kyocera Corp | Electronic component housing package, and electronic equipment including the same |
WO2015033788A1 (en) * | 2013-09-04 | 2015-03-12 | 株式会社 村田製作所 | Method for manufacturing laminated electronic component |
JPWO2015033788A1 (en) * | 2013-09-04 | 2017-03-02 | 株式会社村田製作所 | Manufacturing method of laminated electronic component |
JP2016006846A (en) * | 2014-05-27 | 2016-01-14 | 京セラ株式会社 | Wiring board and electronic apparatus |
WO2017217308A1 (en) * | 2016-06-17 | 2017-12-21 | 株式会社村田製作所 | Electronic component, vibration plate, electronic device, and method for manufacturing electronic components |
US10770215B2 (en) | 2016-06-17 | 2020-09-08 | Murata Manufacturing Co., Ltd. | Electronic component, diaphragm, electronic device, and electronic component manufacturing method |
Also Published As
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JP3425711B2 (en) | 2003-07-14 |
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