JPH0362927A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0362927A JPH0362927A JP19979989A JP19979989A JPH0362927A JP H0362927 A JPH0362927 A JP H0362927A JP 19979989 A JP19979989 A JP 19979989A JP 19979989 A JP19979989 A JP 19979989A JP H0362927 A JPH0362927 A JP H0362927A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor element
- protruding electrode
- wiring board
- protruding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 105
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004020 conductor Substances 0.000 claims abstract description 42
- 229920005989 resin Polymers 0.000 claims abstract description 35
- 239000011347 resin Substances 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000012212 insulator Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 6
- 238000003825 pressing Methods 0.000 claims description 5
- 238000011084 recovery Methods 0.000 abstract 1
- 238000001723 curing Methods 0.000 description 5
- 230000005489 elastic deformation Effects 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 239000004945 silicone rubber Substances 0.000 description 2
- 239000005062 Polybutadiene Substances 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000016 photochemical curing Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000088 plastic resin Substances 0.000 description 1
- 229920002857 polybutadiene Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置およびその製造方法に関し、特
にマイクロコンピュータや、ゲートアレイ等の多電極、
狭ピンチのＬＳＩチップ（半導体素子）の実装に関する
ものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a semiconductor device and a method for manufacturing the same.
This relates to the mounting of LSI chips (semiconductor elements) in a narrow pinch.
半導体装置の典型的な従来の技術を第３図とともに説明
する。A typical conventional technique for a semiconductor device will be explained with reference to FIG.
まず、第３図（ａｌに示すように、セラξ７り、ガラス
等よりなる絶縁性の配線基板１４の導体配線１５を有す
る面の半導体素子接続部位に、絶縁性樹脂１３を塗布す
る。導体配線１５は、Ｃｒ−Ａｕ、Ａｆｆｉ、ＩＴＯ等
であり、絶縁性樹脂１３は熱硬化あるいは紫外線硬化の
エポキシ、アクリル等である。First, as shown in FIG. 3 (al), an insulating resin 13 is applied to the semiconductor element connecting portion on the surface having the conductor wiring 15 of the insulating wiring board 14 made of glass or the like. 15 is Cr-Au, Affi, ITO, etc., and the insulating resin 13 is thermosetting or ultraviolet curing epoxy, acrylic, etc.
つぎに、第３図（ｂｌに示すように、Ａｕ等よりなる突
起電極１２を有したＬＳＩチップ等の半導体素子１）を
、突起電極１２と導体配線１５が整合するように配線基
板１４の絶縁性樹脂１３が塗布された領域に設置し、加
圧ツール１６にて半導体素子１）を配線基板１４に対し
て加圧する。このとき、半導体素子１）の突起電極１２
は金属であるため塑性変形し、絶縁性樹脂１３は周囲に
押し出され、半導体素子１）の突起電極１２と導体配線
１５とは電気的に接触する。Next, the semiconductor element 1 such as an LSI chip having a protruding electrode 12 made of Au or the like as shown in FIG. The semiconductor element 1) is placed in the area coated with the adhesive resin 13, and the semiconductor element 1) is pressed against the wiring board 14 using the pressure tool 16. At this time, the protruding electrode 12 of the semiconductor element 1)
Since it is metal, it deforms plastically, the insulating resin 13 is pushed out to the periphery, and the protruding electrode 12 of the semiconductor element 1) and the conductor wiring 15 come into electrical contact.
つぎに、加圧ツール１６で半導体素子１）を配線基板１
４に対して加圧した状態で、絶縁性樹脂１３を硬化させ
、その後第３図（Ｃ１に示すように、加圧ツール１６を
除去する。このとき、半導体素子１）は配線基板１４に
絶縁性樹脂１３により固着されるとともに、半導体素子
１）の塑性変形された突起電極１２と導体配線１５は接
触により電気的に接続される。Next, the semiconductor element 1) is pressed onto the wiring board 1 using the pressure tool 16.
4, the insulating resin 13 is cured, and then the pressure tool 16 is removed as shown in FIG. The protruding electrodes 12 of the semiconductor element 1), which are fixed by the plastic resin 13 and are plastically deformed, and the conductive wiring 15 are electrically connected through contact.
前述した従来の技術では、半導体素子１）の突起電極１
２を塑性変形させているため、半導体素子１）を固着し
ている絶縁性樹脂１３が熱膨張した際に、突起電極１２
と導体配＆１ｌ１５との間に隙間が生じて電気的な接続
不良が生し、耐熱性の低いものである。In the conventional technology described above, the protruding electrode 1 of the semiconductor element 1)
2 is plastically deformed, when the insulating resin 13 fixing the semiconductor element 1) thermally expands, the protruding electrode 12
A gap is created between the conductor arrangement &1l15, resulting in poor electrical connection, and the heat resistance is low.
また、金属製の突起電極１２の変形を極力小さくして弾
性変形にとどめておき、絶縁性樹脂１３の熱膨張に突起
電極１２の変形を追従させる方法もあるが、変形量が非
常に小さいため、突起電極１２の高さのばらつきや、配
線基板１４の平面度の影響により接続歩留りが非常に低
いものである。Alternatively, there is a method in which the deformation of the metal protruding electrode 12 is kept to an elastic deformation by minimizing the deformation, and the deformation of the protruding electrode 12 follows the thermal expansion of the insulating resin 13, but since the amount of deformation is very small, The connection yield is extremely low due to variations in the height of the protruding electrodes 12 and the flatness of the wiring board 14.
請求項（１）記載の半導体装置は、半導体素子の表面の
配線上の一部に設けられた突起電極を、弾性を有する突
起状の絶縁体からなる突起電極核と、突起電極核の上面
から半導体素子の配線に及び配線に電気的に接続された
金属層とで構成している（第１図ｆｄｌおよび第２図（
Ｃ１参照）。In the semiconductor device according to claim (1), the protruding electrode provided on a part of the wiring on the surface of the semiconductor element is connected to the protruding electrode core made of an elastic protruding insulator and the protruding electrode core from the upper surface of the protruding electrode core. It consists of the wiring of the semiconductor element and a metal layer electrically connected to the wiring (Fig. 1 fdl and Fig. 2 (
(See C1).
請求項（２）記載の半導体装置の製造方法では、請求項
（１）記載の半導体装置の突起電極を以下の工程で作成
している（第１図参照）。In the method for manufacturing a semiconductor device according to claim (2), the protruding electrodes of the semiconductor device according to claim (1) are produced in the following steps (see FIG. 1).
■ 配線が形成された半導体ウェハの表面に弾性を有す
る絶縁性樹脂を塗布して硬化させる工程■ 絶縁性樹脂
の不要部を除去して弾性を有する突起状の絶縁体からな
る突起電極核を配線上の一部に形成する工程
■ 半導体ウェハおよび突起電極核の表面に金属膜を形
成する工程
■ 金属膜の不要部を除去して突起電極核の上面から配
線に及び配線に電気的に接続された金属層を形成するこ
とにより突起電極を得る工程請求項（３）の半導体装置
は、導体配線を有する絶縁性の配ｖＡ基板と、
弾性を有する突起状の絶縁体からなる突起電極核と突起
電極核の上面から半導体素子の配線に及び配線に電気的
に接続された金属層とで構成される突起電極を配線の一
部に有し、突起電極と配線基板の導体配線とが整合する
ように配線基板の導体配線を有する面上に位置決めした
半導体素子と、配線基板の導体配線を有する面に付着さ
れて突起電極核を弾性変形させて金属層を導体配線に電
気的に弾性接触させた状態で半導体素子を配線基板に固
定する絶縁性樹脂とを備えている（第２図（Ｃ１参照）
。■ Process of applying elastic insulating resin to the surface of the semiconductor wafer on which wiring has been formed and curing it ■ Removing unnecessary parts of the insulating resin and wiring protruding electrode cores made of elastic protruding insulators ■ Step of forming a metal film on the surface of the semiconductor wafer and the protruding electrode core ■ A process of forming a metal film on the surface of the semiconductor wafer and the protruding electrode core ■ Removing unnecessary parts of the metal film and connecting it electrically to the wiring from the upper surface of the protruding electrode core. The semiconductor device according to claim (3), which is a step of obtaining a protruding electrode by forming a metal layer, comprises: an insulating distribution substrate having a conductor wiring; a protruding electrode core and a protrusion made of an elastic protruding insulator; A part of the wiring has a protruding electrode formed from the upper surface of the electrode nucleus to the wiring of the semiconductor element and a metal layer electrically connected to the wiring, so that the protruding electrode and the conductor wiring of the wiring board are aligned. A semiconductor element is positioned on a surface of a wiring board having conductor wiring, and a protruding electrode core attached to the surface of a wiring board having conductor wiring is elastically deformed to bring a metal layer into electrical elastic contact with the conductor wiring. (See Figure 2 (C1)).
.
請求項（４）記載の半導体装置の製造方法は、以下の工
程で半導体装置を製造する（第２図参照）。In the method for manufacturing a semiconductor device according to claim (4), the semiconductor device is manufactured by the following steps (see FIG. 2).
■ 絶縁性の配線基板の導体配線を有する面の半導体素
子接続部位に絶縁性樹脂を塗布する工程■ 弾性を有す
る突起状の絶縁体からなる突起電極核と突起電極核の上
面から半導体素子の配線に及び配線に電気的に接続され
た金属層とで構成される突起電極を配線の一部に有する
半導体素子を、突起電極と配線基板の導体配線とが整合
するように配線基板の導体配線を有する面上に位置決め
する工程
■ 突起電極核を弾性変形させて金属層が導体配線に電
気的に弾性接触するように半導体素子を配線基板に対し
て加圧する工程
■ 半導体素子を加圧した状態で絶縁性樹脂を硬化させ
て半導体素子を配′ｆａ基板に固着する工程〔作用〕
この発明によれば、半導体素子の突起電極が弾性を有す
る突起状の絶縁体からなる突起電極核と、突起電極核の
上面から半導体素子の配線に及び配線に電気的に接続さ
れた金属層とで構成しているので、突起電極の弾性変形
量を十分に大きくすることができる。■ Process of applying insulating resin to the semiconductor element connection area on the surface of the insulating wiring board with conductor wiring ■ Protruding electrode core made of an elastic protruding insulator and semiconductor element wiring from the top surface of the protruding electrode nucleus A semiconductor element having a protruding electrode as a part of the wiring, which is composed of a metal layer electrically connected to the wiring, is connected to the conductor wiring of the wiring board so that the protruding electrode and the conductor wiring of the wiring board are aligned. A process of positioning the semiconductor element against the wiring board by elastically deforming the protruding electrode core so that the metal layer comes into electrical elastic contact with the conductor wiring.■ With the semiconductor element being pressurized, According to the present invention, the protruding electrode of the semiconductor element has a protruding electrode core made of an elastic protruding insulator, and a protruding electrode. Since it is constructed from the upper surface of the nucleus to the wiring of the semiconductor element and the metal layer electrically connected to the wiring, the amount of elastic deformation of the protruding electrode can be made sufficiently large.
したがって、配ｖＡ基板の半導体素子を固定して、半導
体素子の突起電極と配線基板の導体配線の電気的接続を
得る場合において、半導体素子を配線基板に対して加圧
した状態で絶縁性樹脂を硬化させることで、突起電極の
突起電極核が弾性変形して金属層が配線基板の導体配線
に弾性接触した状態になる。Therefore, when fixing the semiconductor element on the VA board to obtain an electrical connection between the protruding electrode of the semiconductor element and the conductor wiring of the wiring board, the insulating resin is applied while the semiconductor element is pressurized against the wiring board. By hardening, the protruding electrode core of the protruding electrode is elastically deformed, and the metal layer comes into elastic contact with the conductor wiring of the wiring board.
このため、仮に半導体素子固定用の絶縁性樹脂が膨張し
、絶縁性樹脂の寸法変化が生じても突起電極の弾性復元
により、導体配線と突起電極は常に接触した状態を保持
するものである。Therefore, even if the insulating resin for fixing the semiconductor element expands and the dimensions of the insulating resin change, the conductor wiring and the protruding electrode always remain in contact with each other due to the elastic restoration of the protruding electrode.
また、突起電極の変形量を大きくした場合でも、弾性変
形状態を保っているため、高い接続歩留りを得ることが
できるものである。Further, even when the amount of deformation of the protruding electrode is increased, the elastically deformed state is maintained, so that a high connection yield can be obtained.
この発明の一実施例を第１図および第２図を参照して説
明する。第１図で突起電極の形成方法をについて述べ、
第２図でこの発明の突起電極を有する半導体素子の配線
基板への接続方法について述べる。An embodiment of the invention will be described with reference to FIGS. 1 and 2. Fig. 1 describes the method of forming protruding electrodes,
With reference to FIG. 2, a method for connecting a semiconductor element having protruding electrodes according to the present invention to a wiring board will be described.
最初に、第１図に基づいて半導体素子への突起電極の形
成方法について説明する（請求項（２）に対応する）。First, a method for forming protruding electrodes on a semiconductor element will be described based on FIG. 1 (corresponding to claim (2)).
まず、第１図０１）に示すように、配線を構成するＡ１
電極２３および保護膜２１が形成された半導体ウェハ２
０に、シリコンゴム、ブタジェンゴム等の硬化後に弾性
体となる絶縁性樹脂２２を塗布し、硬化させる。絶縁性
樹脂２２の塗布厚は５〜１５μｍ程度である。硬化の方
法は、熱硬化あるいは紫外線硬化を用いる。First, as shown in Fig. 101), A1 that constitutes the wiring
Semiconductor wafer 2 on which electrodes 23 and protective film 21 are formed
0 is coated with an insulating resin 22 that becomes an elastic body after hardening, such as silicone rubber or butadiene rubber, and is hardened. The coating thickness of the insulating resin 22 is approximately 5 to 15 μm. The curing method uses heat curing or ultraviolet curing.
つぎに第１図０１）に示すように、Ａ６電極２３上の一
部の絶縁性樹脂２２を残し、他の領域の絶縁性樹脂２２
は除去することで、弾性を有する突起状の絶縁体からな
る突起電極核２４を得る。絶縁性樹脂２２の除去は、フ
ォトリソ技術を用い、フォトレジストでパターンニング
した後、ドライエツチング等により除去する。また、絶
縁性樹脂２２に感光性のシリコンゴム等を用いることに
より、直接絶縁性樹脂２２にフォトマスクを介して露光
し、現像することにより、簡単な工程で突起電極核２４
を得ることができる。Next, as shown in FIG.
By removing these, a protruding electrode core 24 made of an elastic protruding insulator is obtained. The insulating resin 22 is removed by dry etching or the like after patterning with a photoresist using a photolithography technique. In addition, by using photosensitive silicone rubber or the like as the insulating resin 22, the protruding electrode core 20 can be formed in a simple process by directly exposing the insulating resin 22 through a photomask and developing it.
can be obtained.
つぎに、第１図（Ｃ）に示すように、半導体ウェハ２０
上に、Ｃｒ−Ａｕ、Ｔｉ−Ｐｄ−Ａｕ等からなる金属膜
２５′を、蒸着あるいはスパッタリング等により表面全
面に形成する。Next, as shown in FIG. 1(C), the semiconductor wafer 20
A metal film 25' made of Cr--Au, Ti--Pd--Au, etc. is formed thereon over the entire surface by vapor deposition or sputtering.
つぎに、フォトリソ技術を用い、第１図ｆｄｌに示すよ
うに、不要部の金属膜２５′を除去し、金属層２５を突
起電極核２４の上面からＡＩ電極に渡る範囲で残して突
起電極２６を得る。この場合、金属層２５は、Ａ１電極
２３に電気的に接続されている。Next, using a photolithography technique, as shown in FIG. get. In this case, the metal layer 25 is electrically connected to the A1 electrode 23.
なお、以上のようにして突起電極２６が形成された半導
体ウェハ２０を各区画毎に切断して分離すると、各々Ｌ
ＳＩチップなどの半導体素子となり、これが配線基板に
搭載される。Note that when the semiconductor wafer 20 on which the protruding electrodes 26 are formed as described above is cut and separated into sections, each section has a length of L.
This becomes a semiconductor element such as an SI chip, which is mounted on a wiring board.
つぎに第２図を用い、前述した突起電極２６を有した半
導体素子の配線基板への接続方法について説明する（請
求項（４）に対応する〉。Next, referring to FIG. 2, a method for connecting a semiconductor element having the above-mentioned protruding electrodes 26 to a wiring board will be described (corresponding to claim (4)).
まず、第２図（ａｌに示すように、ガラス、セラミック
等よりなり、導体配線２９を有した絶縁性の配線基板３
０の導体配線２９を含む領域（半導体素子接続部位）に
絶縁性樹脂２８を塗布する。配線基板３０の厚みは、０
．１〜２． Ｑ ａｍ程度である。First, as shown in FIG.
An insulating resin 28 is applied to a region including the zero conductor wiring 29 (semiconductor element connection site). The thickness of the wiring board 30 is 0.
．． 1-2. It is about Q am.
導体配線２９は、Ｃｒ−Ａｕ、ＡＣＩＴＯ等であり、そ
の厚みは０．１−１０μｍ程度である。絶縁性樹脂２８
は例えばアクリル、エポキシ等の光硬化型であり、塗布
はデイスペンサ、印刷等を用いる。The conductor wiring 29 is made of Cr-Au, ACITO, etc., and has a thickness of about 0.1-10 μm. Insulating resin 28
is a photocuring type such as acrylic or epoxy, and is applied using a dispenser, printing, etc.
つぎに、第２図（ｂｌに示すように、前述した弾性を有
する突起電極核２４と金属層２５とからなる突起電極２
６を有した半導体素子２７を、突起電極２６と導体配線
２９が整合するように配線基板３０の絶縁性樹脂２８が
塗布された領域に設置する。突起電極２６の厚みは５〜
１５μｍ程度であり、その寸法は３μｍロ〜５０μｍロ
程度である。Next, as shown in FIG.
A semiconductor element 27 having a semiconductor element 27 having a diameter of 6 is placed in an area coated with an insulating resin 28 of a wiring board 30 so that the protruding electrodes 26 and the conductor wiring 29 are aligned. The thickness of the protruding electrode 26 is 5~
It is about 15 μm, and its dimensions are about 3 μm to 50 μm.
ついで、突起電極２６が弾性変形状態になるように、加
圧ツール３１にて半導体素子２７を配線基板３０に対し
て加圧する。加圧力は、０．５ｇ／電極〜５ｇ／電極程
度である。このとき、絶縁性樹脂２８は周囲に押し出さ
れ、半導体素子２７の突起電極２６の金属層２５と導体
配線２９は電気的に弾性接触する。Next, the semiconductor element 27 is pressed against the wiring board 30 using the pressing tool 31 so that the protruding electrode 26 is elastically deformed. The pressing force is approximately 0.5 g/electrode to 5 g/electrode. At this time, the insulating resin 28 is pushed out to the periphery, and the metal layer 25 of the protruding electrode 26 of the semiconductor element 27 and the conductor wiring 29 come into electrical elastic contact.
この時、突起電極２６は、ゴム状の弾性体である突起電
極核２４を有しているため、小さい加圧力で容易に変形
し、その弾性変形量が大きく、突起電極２６の厚みのば
らつきや、配線基板３０の平面度を吸収し、半導体素子
２７の全ての突起電極２６を導体配線２９に容易にかつ
確実に接触させることができる。At this time, since the protruding electrode 26 has the protruding electrode core 24 which is a rubber-like elastic body, it is easily deformed by a small pressing force, and the amount of elastic deformation is large. , it is possible to absorb the flatness of the wiring board 30 and bring all the protruding electrodes 26 of the semiconductor element 27 into contact with the conductor wiring 29 easily and reliably.
つぎに、半導体素子２７を加圧した状態で、絶縁性樹脂
２８を硬化させる。硬化の方法は、例えば配線基板３０
がガラス等の透明基板の場合は、配線基板３０の裏面よ
り紫外線３１を矢印の方向に照射する。また、セラミッ
ク等の不透明基板の場合は、半導体素子２７の側面より
紫外線を照射する。Next, the insulating resin 28 is cured while the semiconductor element 27 is pressurized. For example, the curing method can be applied to the wiring board 30.
If the wiring board 30 is a transparent substrate such as glass, ultraviolet rays 31 are irradiated from the back side of the wiring board 30 in the direction of the arrow. Further, in the case of an opaque substrate such as ceramic, ultraviolet rays are irradiated from the side surface of the semiconductor element 27.
つぎに、第２図ｆｃ）に示すように、加圧ツール３１に
よる加圧を解除する。このとき、半導体素子２７は配線
基板３０に固着されると同時に、突起電極２６と導体配
線２９とは接触により電気的に接続され、その状態が保
持される。Next, as shown in FIG. 2 fc), the pressure applied by the pressure tool 31 is released. At this time, the semiconductor element 27 is fixed to the wiring board 30, and at the same time, the protruding electrode 26 and the conductor wiring 29 are electrically connected through contact, and this state is maintained.
以上のような製造方法にて、半導体装置が製造される。A semiconductor device is manufactured by the manufacturing method described above.
この請求項（１）に記載した半導体装置は、半導体素子
２７の表面の配線であるＡＩ電極２３上の一部に設けら
れた突起電極２６を、弾性を有する突起状の絶縁体から
なる突起電極核２４と突起電極核２４の上面から半導体
素子２７のＡＮ電極２３に及びＡ１電極２３に電気的に
接続された金属層２５とで構成している。In the semiconductor device according to claim (1), the protruding electrode 26 provided on a part of the AI electrode 23 which is the wiring on the surface of the semiconductor element 27 is replaced with a protruding electrode made of an elastic protruding insulator. It is composed of a core 24 and a metal layer 25 electrically connected from the upper surface of the protruding electrode core 24 to the AN electrode 23 of the semiconductor element 27 and to the A1 electrode 23.
また、請求項（３）に記載した半導体装置は、導体配線
２９を有する絶縁性の配線基板３０と、弾性を有する突
起状の絶縁体からなる突起電極核２４と突起電極核２４
の上面から半導体素子２７のＡ１電極２３に及びＡ１電
極２３に電気的に接続された金属層２５とで構成される
突起電極２６をＡｌ電極２３の一部に有し、突起電極２
６と配線基板３０の導体配線２９とが整合するように配
線基板３０の導体配線２９を有する面上に位置決めした
半導体素子２７と、
配線基板３０の導体配線２つを有する面に付着されて突
起電極核２４を弾性変形させて金属層２５を導体配線２
つに電気的に弾性接触させた状態で半導体素子２７を配
線基板３０に固定する絶縁他樹脂２８とからなる。Further, the semiconductor device according to claim (3) includes an insulating wiring board 30 having a conductor wiring 29, a protruding electrode core 24 made of an elastic protruding insulator, and a protruding electrode core 24 made of an elastic protruding insulator.
A part of the Al electrode 23 has a protruding electrode 26 composed of the A1 electrode 23 of the semiconductor element 27 and the metal layer 25 electrically connected to the A1 electrode 23 from the upper surface.
The semiconductor element 27 is positioned on the surface of the wiring board 30 having the conductor wiring 29 so that the conductor wiring 29 of the wiring board 30 is aligned with the conductor wiring 29 of the wiring board 30; The electrode core 24 is elastically deformed to form the metal layer 25 into the conductor wiring 2.
The semiconductor element 27 is made of an insulating material 28 and a resin 28 for fixing the semiconductor element 27 to the wiring board 30 while being in electrically elastic contact with the wiring board 30.
〔発明の効果〕
この発明では、半導体素子の突起電極が弾性を有する突
起状の絶縁体からなる突起電極核とその上面から半導体
素子の配線にわたって形成された金属層とにより構成さ
れ、突起電極が弾性変形状態で配線基板の導体配線に接
触しているため、つぎに示す効果がある。[Effects of the Invention] In the present invention, the protruding electrode of a semiconductor element is composed of a protruding electrode core made of an elastic protruding insulator and a metal layer formed from the upper surface of the protruding electrode core to the wiring of the semiconductor element. Since it is in contact with the conductor wiring of the wiring board in an elastically deformed state, it has the following effects.
（１） 半導体素子を配線基板に接続した後に、半導
体素子の固着に用いた絶縁性樹脂が熱膨張しても、突起
電極は容易に弾性復元し、突起電極と配線基板の導体配
線は常に接触した状態を保ち、耐熱性が高く、信頼性つ
ぐ高い。(1) Even if the insulating resin used to fix the semiconductor element expands thermally after the semiconductor element is connected to the wiring board, the protruding electrode easily recovers its elasticity, and the protruding electrode and the conductor wiring of the wiring board are always in contact. It maintains its temperature, has high heat resistance, and is highly reliable.
（２） 突起電極の変形量を大きくしても、弾性変形
状態を保つことができるため、突起電極の厚みのばらつ
きが大きい場合や、配線基板の平面度が無い場合でも、
歩留りよく接続することができる。(2) Even if the amount of deformation of the protruding electrodes is increased, the elastic deformation state can be maintained, so even if the protruding electrodes have large variations in thickness or the wiring board is not flat,
Connections can be made with good yield.
（３） 非常に小さい加圧力で、接続を行うことがで
きるため、半導体素子の加圧時における半導体素子のそ
りや歪の発生がなく、半導体素子の特性変動がなく高品
質の半導体装置を得ることができる。(3) Since connections can be made with extremely small pressure, there is no warping or distortion of the semiconductor element when pressure is applied to the semiconductor element, and there is no change in the characteristics of the semiconductor element, resulting in a high-quality semiconductor device. be able to.
第１図はこの発明の半導体装置の製造方法の一実施例を
示す工程順断面図、第２図は第１図の半導体装置の基板
への接続方法の一例を示す工程順断面図、第３図は従来
例における半導体装置の基板への接続方法を示す工程順
断面図である。
２０・・・半導体ウェハ、２１・・・保護膜、２２・・
・絶縁性樹脂、２３・・・Ａ１電極、２４・・・突起電
極核、２５・・・金属層、２６・・・突起電極、２７・
・・半導体素子、２８・・・絶縁性樹脂、２９・・・導
体配線、３０・・・配線基板、３１・・・加圧ツール
第
（ｂ：
（Ｃ：
（ｄ）
図
〉
−
）
Ｋ斐ζ
ｌ二
にゼ２
）1 is a step-by-step sectional view showing an embodiment of the method for manufacturing a semiconductor device of the present invention; FIG. 2 is a step-by-step sectional view showing an example of a method for connecting the semiconductor device of FIG. 1 to a substrate; The figures are step-by-step sectional views showing a conventional method for connecting a semiconductor device to a substrate. 20... Semiconductor wafer, 21... Protective film, 22...
- Insulating resin, 23... A1 electrode, 24... Protruding electrode core, 25... Metal layer, 26... Protruding electrode, 27.
... Semiconductor element, 28 ... Insulating resin, 29 ... Conductor wiring, 30 ... Wiring board, 31 ... Pressure tool No. (b: (C: (d) Fig. - ) K ζ l2nize2)
Claims (4)
けた半導体装置において、 前記突起電極を、弾性を有する突起状の絶縁体からなる
突起電極核と、前記突起電極核の上面から前記半導体素
子の配線に及び前記配線に電気的に接続された金属層と
で構成したことを特徴とする半導体装置。(1) In a semiconductor device in which a protruding electrode is provided on a part of the wiring on the surface of a semiconductor element, the protruding electrode is connected to a protruding electrode core made of an elastic protruding insulator, and a protruding electrode core is formed from the upper surface of the protruding electrode nucleus. A semiconductor device comprising a wiring of the semiconductor element and a metal layer electrically connected to the wiring.
するに当たって、 配線が形成された半導体ウェハの表面に弾性を有する絶
縁性樹脂を塗布して硬化させる工程と、前記絶縁性樹脂
の不要部を除去して弾性を有する突起状の絶縁体からな
る突起電極核を前記配線上の一部に形成する工程と、 前記半導体ウェハおよび前記突起電極核の表面に金属膜
を形成する工程と、 前記金属膜の不要部を除去して前記突起電極核の上面か
ら前記配線に及び前記配線に電気的に接続された金属層
を形成することにより突起電極を得る工程とを含む半導
体装置の製造方法。(2) In producing the protruding electrode of the semiconductor device according to claim (1), there are a step of applying and curing an elastic insulating resin on the surface of the semiconductor wafer on which wiring is formed, and curing the insulating resin. forming a protruding electrode core made of an elastic protruding insulator on a part of the wiring by removing unnecessary parts; and forming a metal film on the surfaces of the semiconductor wafer and the protruding electrode core. , removing unnecessary parts of the metal film and forming a metal layer from the upper surface of the protruding electrode core to the wiring and electrically connected to the wiring to obtain a protruding electrode. Method.
する突起状の絶縁体からなる突起電極核と前記突起電極
核の上面から前記半導体素子の配線に及び前記配線に電
気的に接続された金属層とで構成される突起電極を配線
の一部に有し、前記突起電極と前記配線基板の導体配線
とが整合するように前記配線基板の前記導体配線を有す
る面上に位置決めした半導体素子と、 前記配線基板の前記導体配線を有する面に付着されて前
記突起電極核を弾性変形させて前記金属層を前記導体配
線に電気的に弾性接触させた状態で前記半導体素子を前
記配線基板に固定する絶縁性樹脂とを備えた半導体装置
。(3) an insulating wiring board having conductor wiring, a protruding electrode core made of an elastic protruding insulator, and an upper surface of the protruding electrode nucleus electrically connected to the wiring of the semiconductor element and to the wiring; A semiconductor having a protruding electrode formed of a metal layer on a part of the wiring, and positioned on the surface of the wiring board having the conductor wiring so that the protruding electrode and the conductor wiring of the wiring board are aligned. and the semiconductor element is attached to the surface of the wiring board having the conductor wiring to elastically deform the protruding electrode core to bring the metal layer into electrical elastic contact with the conductor wiring, and then the semiconductor element is attached to the wiring board. and an insulating resin fixed to the semiconductor device.
素子接続部位に絶縁性樹脂を塗布する工程と、 弾性を有する突起状の絶縁体からなる突起電極核と前記
突起電極核の上面から前記半導体素子の配線に及び前記
配線に電気的に接続された金属層とで構成される突起電
極を配線の一部に有する半導体素子を、前記突起電極と
前記配線基板の導体配線とが整合するように前記配線基
板の前記導体配線を有する面上に位置決めする工程と、 前記突起電極核を弾性変形させて前記金属層が前記導体
配線に電気的に弾性接触するように前記半導体素子を前
記配線基板に対して加圧する工程と、 前記半導体素子を加圧した状態で前記絶縁性樹脂を硬化
させて前記半導体素子を前記配線基板に固着する工程と
を含む半導体装置の製造方法。(4) a step of applying insulating resin to the semiconductor element connection portion of the surface having the conductor wiring of the insulating wiring board; and a step of applying an insulating resin to the semiconductor element connecting portion on the surface having the conductor wiring of the insulating wiring board, and applying a protruding electrode core made of an elastic protruding insulator and the upper surface of the protruding electrode nucleus. A semiconductor element having a protruding electrode as a part of the wiring, which is composed of the wiring of the semiconductor element and a metal layer electrically connected to the wiring, is aligned with the protruding electrode and the conductor wiring of the wiring board. positioning the semiconductor element on the surface of the wiring board having the conductor wiring so as to elastically deform the protruding electrode nucleus so that the metal layer comes into electrical elastic contact with the conductor wiring; A method for manufacturing a semiconductor device, comprising: applying pressure to a substrate; and curing the insulating resin while applying pressure to the semiconductor element to fix the semiconductor element to the wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1199799A JP2744476B2 (en) | 1989-07-31 | 1989-07-31 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1199799A JP2744476B2 (en) | 1989-07-31 | 1989-07-31 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0362927A true JPH0362927A (en) | 1991-03-19 |
| JP2744476B2 JP2744476B2 (en) | 1998-04-28 |
Family
ID=16413818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1199799A Expired - Fee Related JP2744476B2 (en) | 1989-07-31 | 1989-07-31 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2744476B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5749997A (en) * | 1995-12-27 | 1998-05-12 | Industrial Technology Research Institute | Composite bump tape automated bonding method and bonded structure |
| US5861661A (en) * | 1995-12-27 | 1999-01-19 | Industrial Technology Research Institute | Composite bump tape automated bonded structure |
| US6008072A (en) * | 1995-12-27 | 1999-12-28 | Industrial Technology Research Institute | Tape automated bonding method |
| US6194780B1 (en) | 1995-12-27 | 2001-02-27 | Industrial Technology Research Institute | Tape automated bonding method and bonded structure |
| US6365500B1 (en) * | 1994-05-06 | 2002-04-02 | Industrial Technology Research Institute | Composite bump bonding |
| US6881611B1 (en) | 1996-07-12 | 2005-04-19 | Fujitsu Limited | Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device |
| JP2010093674A (en) * | 2008-10-10 | 2010-04-22 | Epson Toyocom Corp | Piezoelectric device, and method for manufacturing piezoelectric substrate |
| US7994638B2 (en) | 2007-05-11 | 2011-08-09 | Panasonic Corporation | Semiconductor chip and semiconductor device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4572376B2 (en) | 2007-07-30 | 2010-11-04 | セイコーエプソン株式会社 | Semiconductor device manufacturing method and electronic device manufacturing method |
| JP5003592B2 (en) * | 2008-05-21 | 2012-08-15 | セイコーエプソン株式会社 | Thermal head and thermal printer |
| KR101381644B1 (en) * | 2011-09-29 | 2014-04-14 | 한국과학기술원 | Bump electrode structure of semiconductor device and method for manufacturing therof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61259548A (en) * | 1985-05-14 | 1986-11-17 | Citizen Watch Co Ltd | Semiconductor device |
| JPS63252447A (en) * | 1987-04-09 | 1988-10-19 | Matsushita Electric Ind Co Ltd | Formation of bump of semiconductor element |
| JPH02272737A (en) * | 1989-04-14 | 1990-11-07 | Citizen Watch Co Ltd | Projecting electrode structure of semiconductor and formation of projecting electrode |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61259548A (en) * | 1985-05-14 | 1986-11-17 | Citizen Watch Co Ltd | Semiconductor device |
| JPS63252447A (en) * | 1987-04-09 | 1988-10-19 | Matsushita Electric Ind Co Ltd | Formation of bump of semiconductor element |
| JPH02272737A (en) * | 1989-04-14 | 1990-11-07 | Citizen Watch Co Ltd | Projecting electrode structure of semiconductor and formation of projecting electrode |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6365500B1 (en) * | 1994-05-06 | 2002-04-02 | Industrial Technology Research Institute | Composite bump bonding |
| US5749997A (en) * | 1995-12-27 | 1998-05-12 | Industrial Technology Research Institute | Composite bump tape automated bonding method and bonded structure |
| US5861661A (en) * | 1995-12-27 | 1999-01-19 | Industrial Technology Research Institute | Composite bump tape automated bonded structure |
| US6008072A (en) * | 1995-12-27 | 1999-12-28 | Industrial Technology Research Institute | Tape automated bonding method |
| US6194780B1 (en) | 1995-12-27 | 2001-02-27 | Industrial Technology Research Institute | Tape automated bonding method and bonded structure |
| US6881611B1 (en) | 1996-07-12 | 2005-04-19 | Fujitsu Limited | Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device |
| US7994638B2 (en) | 2007-05-11 | 2011-08-09 | Panasonic Corporation | Semiconductor chip and semiconductor device |
| JP2010093674A (en) * | 2008-10-10 | 2010-04-22 | Epson Toyocom Corp | Piezoelectric device, and method for manufacturing piezoelectric substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2744476B2 (en) | 1998-04-28 |
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