JP3999222B2 - Flip chip mounting method and flip chip mounting structure - Google Patents

Flip chip mounting method and flip chip mounting structure Download PDF

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JP3999222B2
JP3999222B2 JP2004273680A JP2004273680A JP3999222B2 JP 3999222 B2 JP3999222 B2 JP 3999222B2 JP 2004273680 A JP2004273680 A JP 2004273680A JP 2004273680 A JP2004273680 A JP 2004273680A JP 3999222 B2 JP3999222 B2 JP 3999222B2
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flip chip
wiring board
printed wiring
bump
chip mounting
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JP2004356662A (en
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直人 中谷
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Nippon Avionics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability of electrical connection when used in a wide temperature range. <P>SOLUTION: (a) A resin layer 216 having the coefficient of thermal expansion greater than a bump 222 is formed in at least a fixed region of a flip chip 220 of a printed circuit board 200 excepting a conductor pad 218.(b) A thermosetting non-conductive adhesive 224 is supplied to a flip chip mounting position of the printed circuit board. (c) The bump 222 of the flip chip 220 is aligned with the conductor pad 218 of the printed circuit board 200, to thereby hold the flip chip 220 by pressing it to the print circuit board 200 with a prescribed pressure. (d) The printed circuit board 200 is heated and the thermosetting non-conductive adhesive 224 is hardened. (e) The printed circuit board 200 is cooled.(f) Pressing force of the flip chip 220 is removed. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

この発明は、半導体チップに設けた突起（バンプ）をプリント配線板の電極パッドに直接接続するフリップチップ実装方法と、プリント配線板とに関するものである。   The present invention relates to a flip chip mounting method in which protrusions (bumps) provided on a semiconductor chip are directly connected to electrode pads of a printed wiring board, and a printed wiring board.

半導体チップ（ＩＣチップ）をプリント配線板に実装する方法として、フリップチップ法が知られている。この方法は、突起電極（バンプという）を形成した半導体チップ（フリップチップ）を用い、これらのバンプをプリント配線板の導体パッドに押圧した状態でＩＣチップを絶縁樹脂で固める方法である（例えば特許文献１）。   As a method for mounting a semiconductor chip (IC chip) on a printed wiring board, a flip chip method is known. This method uses a semiconductor chip (flip chip) on which protruding electrodes (referred to as bumps) are formed, and the IC chip is hardened with an insulating resin while these bumps are pressed against the conductor pads of the printed wiring board (for example, patents). Reference 1).

特開平１１−１３５５６８号JP-A-11-135568

例えばＩＣチップに金バンプ（Ａｕバンプ）を設け、このバンプを直接配線板の電極パッド（導体パッド）に押圧してＡｕバンプを若干押しつぶした状態でチップ周辺をＵＶ硬化タイプなどの絶縁樹脂で固める。この場合樹脂はあらかじめ配線板の電極パッドに適量塗布しておき、上からチップを位置合わせして加圧しながらＵＶ照射し常温硬化させる。   For example, an IC chip is provided with gold bumps (Au bumps), and the bumps are pressed directly onto the electrode pads (conductor pads) of the wiring board, and the Au bumps are slightly crushed, and the periphery of the chip is hardened with an insulating resin such as a UV curable type. . In this case, an appropriate amount of resin is applied in advance to the electrode pads of the wiring board, and the chip is aligned from above and UV-irradiated while being pressed and cured at room temperature.

この従来の方法では、Ａｕバンプと電極パッドとの電気的接続はＡｕバンプと電極パッドとの単なる機械的な接触（メカニカルコンタクト）で得られる。このため接続の信頼性は、チップを配線板に固着する樹脂の硬化収縮応力と、少しつぶされたＡｕバンプの復元力に依存している。   In this conventional method, the electrical connection between the Au bump and the electrode pad can be obtained by simple mechanical contact (mechanical contact) between the Au bump and the electrode pad. For this reason, the reliability of connection depends on the curing shrinkage stress of the resin that fixes the chip to the wiring board and the restoring force of the Au bumps that have been slightly crushed.

しかしながら広い温度範囲での温度サイクル試験を行った場合には、絶縁樹脂とＡｕバンプとの熱膨張率の差により電気的接続の信頼性が低下するという問題があった。   However, when a temperature cycle test is performed in a wide temperature range, there is a problem that reliability of electrical connection is lowered due to a difference in thermal expansion coefficient between the insulating resin and the Au bump.

この発明はこのような事情に鑑みなされたものであり、広い温度範囲で使用する場合に電気的接続の信頼性を向上させることができるフリップチップ実装方法を提供することを第１の目的とする。またこの方法を用いたフリップチップ実装構造を提供することを第２の目的とする。 The present invention has been made in view of such circumstances, and a first object thereof is to provide a flip chip mounting method capable of improving the reliability of electrical connection when used in a wide temperature range. . A second object is to provide a flip chip mounting structure using this method.

本発明によればこの第１の目的は、フリップチップのバンプをプリント配線板の導体パッドに位置合わせしてフリップチップを熱硬化型非導電性接着剤で固定するフリップチップ実装方法において、ａ）導体パッドを除いて前記プリント配線板の少なくとも前記フリップチップの固定領域に、前記バンプよりも熱膨張率が大きく、かつ前記バンプの高さ（ｈ）と導体パッドの厚さ（ｔ）との和（ｈ＋ｔ）よりも僅かに薄い樹脂層を形成する；ｂ）前記プリント配線板のフリップチップ実装位置に熱硬化型非導電性接着剤を供給する；ｃ）フリップチップのバンプをプリント配線板の導体パッドに位置合わせし、フリップチップを所定の圧力でプリント配線板に押圧して保持する；ｄ）プリント配線板を加熱し前記熱硬化型非導電性接着剤を硬化させる；ｅ）冷却する；ｆ）フリップチップの押圧力を除く；以上の各工程を順次行うフリップチップ実装方法、によって達成できる。ここに工程ｅ)とｆ)の順番を逆にしても同一目的が達成できる。 According to the present invention, the first object is to provide a flip chip mounting method in which a flip chip bump is aligned with a conductor pad of a printed wiring board and the flip chip is fixed with a thermosetting non-conductive adhesive. at least a fixed area of the flip chip of the printed circuit board with the exception of contact pads, wherein the thermal expansion coefficient much larger than the bump and the height of the bump (h) and thickness of the conductor pad (t) A resin layer slightly thinner than the sum (h + t) is formed; b) a thermosetting non-conductive adhesive is supplied to the flip chip mounting position of the printed wiring board; c) bumps of the flip chip are formed on the printed wiring board. Align to the conductor pad and hold the flip chip against the printed wiring board with a predetermined pressure; d) Heat the printed wiring board to harden the thermosetting non-conductive adhesive Causes; e) cooling; f) except the pressing force of the flip chip; flip chip mounting method sequentially performing the above steps, the achievable. Even if the order of steps e) and f) is reversed, the same purpose can be achieved.

第２の目的は、フリップチップのバンプをプリント配線板の導体パッドに位置合わせしてフリップチップを熱硬化型非導電性接着剤で固定したフリップチップ実装構造において、導体パッドを除いて前記プリント配線板の少なくとも前記フリップチップの固定領域に前記バンプよりも熱膨張率が大きくかつ前記バンプの高さ（ｈ）と導体パッドの厚さ（ｔ）との和（ｈ＋ｔ）よりも僅かに薄い樹脂層と、前記プリント配線板とフリップチップとの間に供給され硬化された熱硬化型非導電性接着剤と、を備え、前記樹脂層の収縮量とバンプの収縮量との差によってバンプとパッドとの間に接触圧を発生させたことを特徴とするフリップチップ実装構造、によって達成可能である。 The second object is to provide a flip-chip mounting structure in which flip-chip bumps are aligned with conductor pads of a printed wiring board and the flip chip is fixed with a thermosetting non-conductive adhesive. Resin layer having a coefficient of thermal expansion larger than that of the bump and slightly thinner than the sum (h + t) of the height (h) of the bump and the thickness (t) of the conductor pad in at least the flip chip fixing region of the plate And a thermosetting non-conductive adhesive that is supplied and cured between the printed wiring board and the flip chip, and the bumps and the pads depending on the difference between the shrinkage amount of the resin layer and the shrinkage amount of the bumps. This can be achieved by a flip chip mounting structure characterized in that a contact pressure is generated between the two.

第１の発明は以上のように、導体パッドを除き少なくともフリップチップの実装領域にバンプよりも熱膨張率が大きくかつバンプの高さ（ｈ）と導体パッドの厚さ（ｔ）との和（ｈ＋ｔ）よりも僅かに薄い樹脂層を形成し、熱硬化型非導電性接着剤を挟んで半導体チップを押圧しつつ接着剤を硬化させるから、押圧力を解除しても樹脂層の収縮量とバンプの収縮量の差によってバンプとパッドとの間に十分な接触圧を発生させることができ、電気的接続の信頼性を向上させることができる。 As in the first invention above, the sum of the thermal expansion than the bump in the mounting region of at least the flip chip except conductor pad size KuKatsu height of the bump (h) and thickness of the conductor pad (t) (h + t) thin not to form a resin layer slightly above, since the adhesive is cured while pressing the semiconductor chip across the thermosetting non-conductive adhesive, even by releasing the pressing force of the resin layer contracts A sufficient contact pressure can be generated between the bump and the pad due to the difference between the amount and the shrinkage amount of the bump, and the reliability of electrical connection can be improved.

第２の発明によれば請求項１の方法を用いたフリップチップ実装構造が得られる。 According to the second invention, a flip chip mounting structure using the method of claim 1 is obtained.

工程ａ）で形成する樹脂層は、感光性樹脂であってもよいが（請求項２）、エポキシ系樹脂でもよい（請求項３）。エポキシ系樹脂はガラス転移温度を境にして低温側では熱膨張率が小さく、高温側で熱膨張率が大きくなるから、このエポキシ系樹脂を用いる場合にはこのガラス転移温度が接着剤の硬化温度よりも低いエポキシ系樹脂を用いるのが望ましい。このようにすれば接着剤硬化温度で樹脂層の熱膨張率が大きくなるため、接着剤の硬化後に常温に冷却した状態でＡｕバンプとパッドとの間に大きな収縮応力を発生させることができる。   The resin layer formed in step a) may be a photosensitive resin (Claim 2) or an epoxy resin (Claim 3). Epoxy resins have a low coefficient of thermal expansion on the low temperature side and a high coefficient of thermal expansion on the high temperature side, with the glass transition temperature as a boundary.When this epoxy resin is used, this glass transition temperature is the curing temperature of the adhesive. It is desirable to use a lower epoxy resin. In this way, since the thermal expansion coefficient of the resin layer increases at the adhesive curing temperature, a large shrinkage stress can be generated between the Au bump and the pad in a state of cooling to room temperature after the adhesive is cured.

バンプはワイヤーボンディングによる金バンプが適し、この場合は導体パッドの表面に金めっきを施しておくのがよい（請求項４）。工程ｃ）の加圧（押圧）と工程ｄ）の加熱硬化は同時に行ってもよい（請求項５）。また工程ｅ）とｆ）とは逆に行ってもよい（請求項６）。 As the bump, a gold bump by wire bonding is suitable, and in this case, the surface of the conductor pad is preferably plated with gold (Claim 4). The pressurization (pressing) in step c) and the heat curing in step d) may be performed simultaneously (Claim 5). Further, steps e) and f) may be performed in reverse (claim 6).

基板はビルドアップ法で作られた多層基板とすることができる。樹脂層は、有機系樹脂をスクリーン印刷、カーテンコート、スプレーコートなどの方法を用いてフリップチップの少なくとも固定領域に形成することができる。樹脂層は基板全面に形成してもよいが、フリップチップの固定領域より僅かに広い領域だけに形成してもよい。この樹脂層の厚さ（Ｈ）は、フリップチップの実装後のバンプ高さ（ｈ）と導体パッド厚さ（ｔ）との和（ｈ＋ｔ）よりも僅かに薄い程度が望ましく、通常２０〜４０μｍの厚さがよい。   The substrate can be a multilayer substrate made by a build-up method. The resin layer can be formed on at least the fixed region of the flip chip by using an organic resin such as screen printing, curtain coating, spray coating, or the like. The resin layer may be formed on the entire surface of the substrate, but may be formed only in a region slightly wider than the fixed region of the flip chip. The thickness (H) of the resin layer is preferably slightly smaller than the sum (h + t) of the bump height (h) after mounting the flip chip and the conductor pad thickness (t), and is usually 20 to 40 μm. The thickness of is good.

樹脂層には基板の導体パッド上に開口を形成しておく。この開口は、樹脂層に感光性樹脂を用いる場合にはフォトリソグラフィプロセスによって形成することができる。すなわちフォトマスクを重ねて露光し現像することによって導体パッド上に開口を有する樹脂層を形成することができる。熱硬化型樹脂を用いる場合には、基板に樹脂を均一に塗布し硬化した後、ＣＯ2レーザを用いて開口を加工することができる。なお導体パッド表面に金メッキを施す場合は、樹脂層を形成する前に金めっきしてもよいし、樹脂層に開口を形成した後に金めっきしてもよい。 An opening is formed in the resin layer on the conductor pad of the substrate. This opening can be formed by a photolithography process when a photosensitive resin is used for the resin layer. That is, a resin layer having an opening on the conductor pad can be formed by exposing and developing a photomask in an overlapping manner. When a thermosetting resin is used, the opening can be processed using a CO 2 laser after the resin is uniformly applied to the substrate and cured. In addition, when performing gold plating on the surface of the conductor pad, gold plating may be performed before the resin layer is formed, or gold plating may be performed after the opening is formed in the resin layer.

図１は実施例の実装工程を示す断面図、図２はその実装工程の流れ図である。この実施例では、バンプの熱膨張率とプリント配線板の少なくともフリップチップの固定領域に形成される樹脂層の熱膨張率の差を利用してバンプと導体パッドとの間の常温における接触圧を得るものである。   FIG. 1 is a sectional view showing a mounting process of the embodiment, and FIG. 2 is a flowchart of the mounting process. In this embodiment, the contact pressure at normal temperature between the bump and the conductor pad is calculated using the difference between the thermal expansion coefficient of the bump and the thermal expansion coefficient of the resin layer formed at least in the fixed area of the flip chip of the printed wiring board. To get.

図１において２００はベース基板（プリント配線板）であり、例えばビルドアップ法で作られた多層基板である。この基板２００の表面には導体パッド（フリップチップ用パッド）２１８が形成され、その表面には金めっきを施しておく（図２のステップＳ３００）。この基板２００には、導体パッド２１８を除いて樹脂層２１６が形成される。   In FIG. 1, reference numeral 200 denotes a base substrate (printed wiring board), for example, a multilayer substrate made by a build-up method. Conductive pads (flip chip pads) 218 are formed on the surface of the substrate 200, and gold plating is applied to the surface (step S300 in FIG. 2). A resin layer 216 is formed on the substrate 200 except for the conductor pads 218.

この樹脂層２１６は半導体チップ２２０の金バンプ２２２の熱膨張率よりも大きな熱膨張率を持った樹脂で形成され、例えば感光性樹脂が用いられる。この樹脂層２１６は導体パッド２１８を除いて、半導体チップ２２０の実装領域よりも僅かに広い領域に形成される（ステップＳ３０２）。この樹脂層２１６は例えばフォトリソグラフィの方法を用いて形成すればよい。   This resin layer 216 is formed of a resin having a thermal expansion coefficient larger than that of the gold bump 222 of the semiconductor chip 220, and for example, a photosensitive resin is used. The resin layer 216 is formed in a region slightly wider than the mounting region of the semiconductor chip 220 except for the conductor pads 218 (step S302). The resin layer 216 may be formed using, for example, a photolithography method.

樹脂層２１６は、その熱膨張率と共にその厚さが重要になる。この樹脂層２１６の厚さＨは図１の（Ｃ）に示すように、導体パッド２１８の厚さｔと、実装後の金バンプ２２２の高さｈとの和（ｔ＋ｈ）よりも僅かに小さい。すなわちＨ＜（ｔ＋ｈ）となるようにすることが必要である。通常Ｈは２０〜４０μｍにするのがよい。   The thickness of the resin layer 216 is important along with its coefficient of thermal expansion. As shown in FIG. 1C, the thickness H of the resin layer 216 is slightly smaller than the sum (t + h) of the thickness t of the conductor pad 218 and the height h of the gold bump 222 after mounting. . That is, it is necessary to satisfy H <(t + h). Usually, H is preferably 20 to 40 μm.

次に半導体チップ２２０を実装する基板２００上の領域にディスペンサなどで所定量の熱硬化型接着剤２２４を供給する（ステップＳ３０４）。そして半導体チップ（フリップチップ）２２０の金バンプ２２２を導体パッド２１８に位置合わせして押圧し保持する（Ｓ３０６）。この状態で接着剤２２４を加熱し硬化させれば、図１（Ｃ）に示すように金バンプ２２２が所定量つぶれて導体パッド２１８に密着する（Ｓ３０８）。   Next, a predetermined amount of the thermosetting adhesive 224 is supplied to the region on the substrate 200 on which the semiconductor chip 220 is mounted using a dispenser or the like (step S304). Then, the gold bump 222 of the semiconductor chip (flip chip) 220 is aligned with the conductor pad 218 and pressed and held (S306). When the adhesive 224 is heated and cured in this state, the gold bumps 222 are crushed by a predetermined amount as shown in FIG. 1C and are in close contact with the conductor pads 218 (S308).

この状態で常温まで冷却し（Ｓ３１０）、押圧力を解除すればよい（Ｓ３１２）。なお接着剤２２４はステップＳ３０８の加熱によってすでに硬化しているから、ステップＳ３１０とＳ３１２とを同時あるいは逆にしてもよい。   In this state, it is cooled to room temperature (S310), and the pressing force may be released (S312). Since the adhesive 224 has already been cured by heating in step S308, steps S310 and S312 may be performed simultaneously or in reverse.

この結果、常温まで冷える時には、金バンプ２２２の厚さ方向の熱収縮量よりも樹脂層２１６の厚さ方向の熱収縮量の方が大きくなるから、両者の厚さ方向の収縮量の差によって金バンプ２２２と導体パッド２１８との間に圧縮応力が発生する。このため金バンプ２２２と導体パッド２１８との接触圧が常に一定以上に保たれ、電気的接続の信頼性が向上する。なお厳密に検討すれば、導体パッド２１８の熱膨張率（あるいは厚さ方向の熱収縮量）も考慮すべきであるが、通常は導体パッド２１８の厚さは樹脂層２１６の厚さＨや金バンプ２２２の高さｈよりも十分に小さいので、これを省くことができる。   As a result, when cooling to room temperature, the thermal shrinkage in the thickness direction of the resin layer 216 is larger than the thermal shrinkage in the thickness direction of the gold bump 222. A compressive stress is generated between the gold bump 222 and the conductor pad 218. For this reason, the contact pressure between the gold bump 222 and the conductor pad 218 is always kept above a certain level, and the reliability of electrical connection is improved. If strictly examined, the coefficient of thermal expansion (or the amount of thermal shrinkage in the thickness direction) of the conductor pad 218 should be taken into consideration, but the thickness of the conductor pad 218 is usually set to the thickness H of the resin layer 216 or gold. Since it is sufficiently smaller than the height h of the bump 222, it can be omitted.

本発明の一実施例を示す断面図Sectional drawing which shows one Example of this invention 実施工程の流れ図Flow chart of implementation process

符号の説明Explanation of symbols

２００ ベース基板（プリント配線板）
２１６ 樹脂層
２１８ 導体パッド
２２０ 半導体チップ（フリップチップ）
２２２ 金バンプ
２２４ 接着剤 200 Base board (printed wiring board)
216 Resin layer 218 Conductor pad 220 Semiconductor chip (flip chip)
222 Gold bump 224 Adhesive

Claims (7)

フリップチップのバンプをプリント配線板の導体パッドに位置合わせしてフリップチップを熱硬化型非導電性接着剤で固定するフリップチップ実装方法において、
ａ）導体パッドを除いて前記プリント配線板の少なくとも前記フリップチップの固定領域に、前記バンプよりも熱膨張率が大きく、かつ前記バンプの高さ（ｈ）と導体パッドの厚さ（ｔ）との和（ｈ＋ｔ）よりも僅かに薄い樹脂層を形成する；
ｂ）前記プリント配線板のフリップチップ実装位置に熱硬化型非導電性接着剤を供給する；
ｃ）フリップチップのバンプをプリント配線板の導体パッドに位置合わせし、フリップチップを所定の圧力でプリント配線板に押圧して保持する；
ｄ）プリント配線板を加熱し前記熱硬化型非導電性接着剤を硬化させる；
ｅ）冷却する；
ｆ）フリップチップの押圧力を除く；
以上の各工程を順次行うフリップチップ実装方法。 In the flip chip mounting method of aligning the flip chip bumps with the conductor pads of the printed wiring board and fixing the flip chip with a thermosetting non-conductive adhesive,
at least a fixed area of the flip chip of the printed wiring board except for a) conductive pads, the thermal expansion coefficient much larger than the bump and the height of the bump (h) and the conductor pad thickness (t) A slightly thinner resin layer than the sum of (h + t) ;
b) supplying a thermosetting non-conductive adhesive to the flip chip mounting position of the printed wiring board;
c) Align the flip chip bumps with the conductor pads of the printed wiring board and press and hold the flip chip against the printed wiring board with a predetermined pressure;
d) heating the printed wiring board to cure the thermosetting non-conductive adhesive;
e) cool;
f) Exclude the flip chip pressing force;
A flip chip mounting method in which the above steps are sequentially performed . 工程ａ）で形成する樹脂層は感光性樹脂である請求項１のフリップチップ実装方法。 2. The flip chip mounting method according to claim 1, wherein the resin layer formed in step a) is a photosensitive resin. 工程ａ）で形成する樹脂層は、ガラス転移温度が接着剤の硬化温度よりも低いエポキシ系樹脂である請求項１のフリップチップ実装方法。 2. The flip chip mounting method according to claim 1, wherein the resin layer formed in step a) is an epoxy resin having a glass transition temperature lower than the curing temperature of the adhesive. フリップチップのバンプはワイヤーボンディングにより形成された金バンプである請求項１〜３のいずれかのフリップチップ実装方法。 4. The flip chip mounting method according to claim 1, wherein the flip chip bumps are gold bumps formed by wire bonding. 請求項１〜４のいずれかにおいて、工程ｃ）と工程ｄ）を同時に行うフリップチップ実装方法。 5. The flip chip mounting method according to claim 1, wherein the step c) and the step d) are performed simultaneously. フリップチップのバンプをプリント配線板の導体パッドに位置合わせしてフリップチップを熱硬化型非導電性接着剤で固定するフリップチップ実装方法において、
ａ）導体パッドを除いて前記プリント配線板の少なくとも前記フリップチップの固定領域に前記バンプよりも熱膨張率が大きく、かつ前記バンプの高さ（ｈ）と導体パッドの厚さ（ｔ）との和（ｈ＋ｔ）よりも僅かに薄い樹脂層を形成する；
ｂ）前記プリント配線板のフリップチップ実装位置に熱硬化型非導電性接着剤を供給する；
ｃ）フリップチップのバンプをプリント配線板の導体パッドに位置合わせし、フリップチップを所定の圧力でプリント配線板に押圧して保持する；
ｄ）プリント配線板を加熱し前記熱硬化型非導電性接着剤を硬化させる；
ｅ′）フリップチップの押圧力を除く；
ｆ′）冷却する；
以上の各工程を順次行うフリップチップ実装方法。 In the flip chip mounting method of aligning the flip chip bumps with the conductor pads of the printed wiring board and fixing the flip chip with a thermosetting non-conductive adhesive,
a) Except for the conductor pad, at least the flip chip fixing region of the printed wiring board has a coefficient of thermal expansion greater than that of the bump, and the height (h) of the bump and the thickness (t) of the conductor pad Forming a resin layer slightly thinner than the sum (h + t);
b) supplying a thermosetting non-conductive adhesive to the flip chip mounting position of the printed wiring board;
c) Align the flip chip bumps with the conductor pads of the printed wiring board and hold the flip chip against the printed wiring board with a predetermined pressure;
d) heating the printed wiring board to cure the thermosetting non-conductive adhesive;
e ′) remove the flip chip pressing force;
f ′) cool;
A flip chip mounting method in which the above steps are sequentially performed . フリップチップのバンプをプリント配線板の導体パッドに位置合わせしてフリップチップを熱硬化型非導電性接着剤で固定したフリップチップ実装構造において、In the flip chip mounting structure in which the flip chip bumps are aligned with the conductor pads of the printed wiring board and the flip chip is fixed with a thermosetting non-conductive adhesive,
導体パッドを除いて前記プリント配線板の少なくとも前記フリップチップの固定領域に前記バンプよりも熱膨張率が大きくかつ前記バンプの高さ（ｈ）と導体パッドの厚さ（ｔ）との和（ｈ＋ｔ）よりも僅かに薄く形成された樹脂層と、前記プリント配線板とフリップチップとの間に供給され硬化された熱硬化型非導電性接着剤と、を備え、  Except for the conductor pads, at least the flip chip fixing region of the printed wiring board has a coefficient of thermal expansion greater than that of the bumps, and the sum of the bump height (h) and the thickness (t) of the conductor pads (h + t) And a thermosetting non-conductive adhesive that is supplied and cured between the printed wiring board and the flip chip.
前記樹脂層の収縮量と前記バンプの収縮量との差によって前記バンプと前記導体パッドとの間に接触圧を発生させたことを特徴とするフリップチップ実装構造。  A flip chip mounting structure, wherein a contact pressure is generated between the bump and the conductor pad by a difference between a shrinkage amount of the resin layer and a shrinkage amount of the bump.
JP2004273680A 2000-05-31 2004-09-21 Flip chip mounting method and flip chip mounting structure Expired - Lifetime JP3999222B2 (en)

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