JPH1022334A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH1022334A
JPH1022334A JP8191621A JP19162196A JPH1022334A JP H1022334 A JPH1022334 A JP H1022334A JP 8191621 A JP8191621 A JP 8191621A JP 19162196 A JP19162196 A JP 19162196A JP H1022334 A JPH1022334 A JP H1022334A
Authority
JP
Japan
Prior art keywords
film substrate
resin
semiconductor chip
bump
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8191621A
Other languages
Japanese (ja)
Other versions
JP3269390B2 (en
Inventor
Tetsuya Hiraishi
哲也 平石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=16277692&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JPH1022334(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP19162196A priority Critical patent/JP3269390B2/en
Publication of JPH1022334A publication Critical patent/JPH1022334A/en
Application granted granted Critical
Publication of JP3269390B2 publication Critical patent/JP3269390B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent junction failure with good high frequency characteristics. SOLUTION: Bump electrodes 26 of a semiconductor chip 25 is eutectically bonded to a connection electrode 23 of a film substrate 22, and the semiconductor chip 25 is bonded to the film substrate 22 with resin 24 disposed therebetween. Accordingly, the electrical resistance of a junction part between the bump and connection electrodes 26 and 23 can be lowered and high frequency characteristics can be improved. Further, residual stress takes place in the interior of the film substrate 22 due to heat. Even when the residual stress causes the film substrate 22 to return to its original state, the resin 24 can prevent it and also prevent peeling off of a junction part between the bump and connection electrodes 26 and 23, that is, a junction failure.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は半導体装置に関す
る。
[0001] The present invention relates to a semiconductor device.

【0002】[0002]

【従来の技術】半導体装置には、ICチップやLSIチ
ップなどの半導体チップをフィルム基板上に搭載したも
のがある。図6はこのような半導体装置の一例を示した
ものである。この場合、フィルム基板1の接続電極2は
接続電極本体2aとこの接続電極本体2aの表面に形成
されたスズメッキ層2bとからなっており、半導体チッ
プ3の金からなるバンプ電極4をフィルム基板1の接続
電極2に位置合わせを行って載置し、加熱しながら加圧
することにより、半導体チップ3のバンプ電極4をフィ
ルム基板1の接続電極2に共晶接合している。
2. Description of the Related Art Some semiconductor devices have a semiconductor chip such as an IC chip or an LSI chip mounted on a film substrate. FIG. 6 shows an example of such a semiconductor device. In this case, the connection electrode 2 of the film substrate 1 includes a connection electrode body 2a and a tin plating layer 2b formed on the surface of the connection electrode body 2a. The bump electrodes 4 of the semiconductor chip 3 are eutectic-bonded to the connection electrodes 2 of the film substrate 1 by positioning and placing the connection electrodes 2 on the connection electrodes 2 and pressing them while heating.

【0003】ところで、従来のこのような半導体装置で
は、半導体チップ3のバンプ電極4をフィルム基板1の
接続電極2に金−スズ合金による共晶接合をする場合、
半導体チップ3やフィルム基板1も加熱されるので、半
導体チップ3やフィルム基板1が常温に戻ると、半導体
チップ3とフィルム基板1との熱膨張率の差によってフ
ィルム基板1の内部に残留応力が生じる。すると、スプ
リングバック、つまり残留応力によりフィルム基板1が
元の状態に戻ろうとする現象によって、図7に示すよう
に、バンプ電極4と接続電極2との接合部分が剥がれ、
接合不良が生じることがあるという問題があった。そこ
で、このような問題を解決するために、半導体チップや
フィルム基板を加熱しない接合方法が提案されている。
図8はこのような接合方法を適用した半導体装置の一例
を示したものである。この場合、半導体チップ11とフ
ィルム基板12との間に光硬化性樹脂13を介在させた
状態で半導体チップ11のバンプ電極14をフィルム基
板12の接続電極15に位置合わせを行って載置し、加
圧しながら紫外線を照射することにより、バンプ電極1
4を接続電極15に圧接した状態で光硬化性樹脂13を
硬化し、硬化した光硬化性樹脂13によって半導体チッ
プ11とフィルム基板12とを接着している。
In such a conventional semiconductor device, when the bump electrode 4 of the semiconductor chip 3 is connected to the connection electrode 2 of the film substrate 1 by eutectic bonding using a gold-tin alloy,
Since the semiconductor chip 3 and the film substrate 1 are also heated, when the semiconductor chip 3 and the film substrate 1 return to room temperature, residual stress is generated inside the film substrate 1 due to a difference in coefficient of thermal expansion between the semiconductor chip 3 and the film substrate 1. Occurs. Then, due to springback, that is, a phenomenon in which the film substrate 1 tries to return to the original state due to residual stress, as shown in FIG. 7, the joint between the bump electrode 4 and the connection electrode 2 is peeled off,
There has been a problem that poor joining may occur. Therefore, in order to solve such a problem, a bonding method that does not heat a semiconductor chip or a film substrate has been proposed.
FIG. 8 shows an example of a semiconductor device to which such a bonding method is applied. In this case, the bump electrode 14 of the semiconductor chip 11 is positioned and placed on the connection electrode 15 of the film substrate 12 in a state where the photocurable resin 13 is interposed between the semiconductor chip 11 and the film substrate 12. By irradiating ultraviolet rays while applying pressure, the bump electrodes 1
The photocurable resin 13 is cured in a state where 4 is pressed against the connection electrode 15, and the semiconductor chip 11 and the film substrate 12 are bonded by the cured photocurable resin 13.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、従来の
このような半導体装置では、半導体チップ11のバンプ
電極14とフィルム基板12の接続電極15とは単に圧
接しているだけなので、共晶接合の場合と比較するとバ
ンプ電極14と接続電極15との接合部分の電気抵抗が
高くなり、高周波特性が悪いという問題があった。この
発明の課題は、高周波特性が良好な状態で接合不良が生
じないようにすることである。
However, in such a conventional semiconductor device, the bump electrode 14 of the semiconductor chip 11 and the connection electrode 15 of the film substrate 12 are simply pressed against each other. In comparison with the above, there is a problem that the electrical resistance at the junction between the bump electrode 14 and the connection electrode 15 is increased, and the high-frequency characteristics are poor. SUMMARY OF THE INVENTION An object of the present invention is to prevent a bonding defect from occurring in a state in which high-frequency characteristics are good.

【0005】[0005]

【課題を解決するための手段】この発明は、半導体チッ
プのバンプ電極と回路基板の接続電極とが共晶接合され
ているとともに、前記半導体チップと前記回路基板とが
その間に介在された樹脂によって接着されているもので
ある。
According to the present invention, a bump electrode of a semiconductor chip and a connection electrode of a circuit board are eutectic-bonded, and the semiconductor chip and the circuit board are formed by a resin interposed therebetween. It is the one that is glued.

【0006】この発明によれば、半導体チップのバンプ
電極と回路基板の接続電極とが共晶接合されているの
で、バンプ電極と接続電極との接合部分の電気抵抗を低
くすることができ、高周波特性を良くすることができ
る。また、半導体チップと回路基板とがその間に介在さ
れた樹脂によって接着されているので、回路基板の内部
に加熱による残留応力が生じ、この残留応力によって回
路基板が元の状態に戻ろうとしても樹脂がそれを防ぎ、
バンプ電極と接続電極との接合部分が剥がれるのを防止
し、接合不良が生じないようにすることができる。
According to this invention, since the bump electrode of the semiconductor chip and the connection electrode of the circuit board are eutectic bonded, the electrical resistance at the junction between the bump electrode and the connection electrode can be reduced, and the high frequency The characteristics can be improved. In addition, since the semiconductor chip and the circuit board are bonded by the resin interposed therebetween, residual stress due to heating is generated inside the circuit board, and even if the circuit board attempts to return to the original state due to the residual stress. Prevent it,
It is possible to prevent the joint between the bump electrode and the connection electrode from peeling off, and to prevent a joint failure from occurring.

【0007】[0007]

【発明の実施の形態】図1および図2はそれぞれこの発
明の一実施形態における半導体装置の製造工程を示した
ものである。そこで、これらの図を順に参照しながら、
この実施形態における半導体装置の構造についてその製
造方法と併せて説明する。
1 and 2 show a manufacturing process of a semiconductor device according to an embodiment of the present invention. Therefore, referring to these figures in order,
The structure of the semiconductor device according to this embodiment will be described together with its manufacturing method.

【0008】まず、図1に示すように、熱圧着装置(図
示せず)におけるステージ21の上面にフィルム基板2
2を位置決めした状態で載置する。この場合、フィルム
基板22の上面には複数の接続電極23が設けられてい
る。この接続電極23は銅などからなる接続電極本体2
3aとこの接続電極本体23aの表面に形成されたメッ
キ層23bとからなっている。メッキ層23bはスズ、
半田、金などからなり、その膜厚は1μm程度となって
いる。次に、フィルム基板22の上面における接続電極
23が形成されていない所定の箇所にポリイミド樹脂、
シリコーン樹脂などの熱可塑性樹脂からなる樹脂24を
印刷方法、ニードルディスペンス方法、転写方法などに
よって塗布する。次に、フィルム基板22の上方に半導
体チップ25を、樹脂24と対向するように位置決めし
た状態で配置する。この場合、半導体チップ25の下面
には金、半田などからなるバンプ電極26が高さ15〜
30μm程度に設けられている。
First, as shown in FIG. 1, a film substrate 2 is placed on the upper surface of a stage 21 in a thermocompression bonding apparatus (not shown).
2 is positioned and positioned. In this case, a plurality of connection electrodes 23 are provided on the upper surface of the film substrate 22. The connection electrode 23 is a connection electrode body 2 made of copper or the like.
3a and a plating layer 23b formed on the surface of the connection electrode body 23a. The plating layer 23b is made of tin,
It is made of solder, gold, or the like, and has a thickness of about 1 μm. Next, a polyimide resin is provided at a predetermined position on the upper surface of the film substrate 22 where the connection electrode 23 is not formed.
A resin 24 made of a thermoplastic resin such as a silicone resin is applied by a printing method, a needle dispensing method, a transfer method, or the like. Next, the semiconductor chip 25 is arranged above the film substrate 22 in a state of being positioned so as to face the resin 24. In this case, a bump electrode 26 made of gold, solder, or the like has a height of 15 to
The thickness is set to about 30 μm.

【0009】次に、図2に示すように、フィルム基板2
2と半導体チップ25との間に樹脂24を介在させた状
態で、半導体チップ25のバンプ電極26をフィルム基
板22の対応する接続電極23に位置合わせを行って載
置する。次に、半導体チップ25の上から図示しない熱
圧着ヘッドを押し付けて加熱しながら加圧すると、半導
体チップ25のバンプ電極26とフィルム基板22の接
続電極23とが、双方の構成金属の合金によって共晶接
合される。この場合、加熱温度は400〜600℃程度
であり、例えばポリイミド樹脂の軟化温度は230℃程
度であるので、半導体チップ25とフィルム基板22と
の間に介在された樹脂24は加熱されることにより軟化
し、その後冷却されることにより固化し、固化した樹脂
24によって半導体チップ25とフィルム基板22とが
接着される。
Next, as shown in FIG.
With the resin 24 interposed between the semiconductor chip 25 and the semiconductor chip 25, the bump electrodes 26 of the semiconductor chip 25 are positioned and mounted on the corresponding connection electrodes 23 of the film substrate 22. Next, when a thermocompression bonding head (not shown) is pressed from above the semiconductor chip 25 while being heated, the bump electrodes 26 of the semiconductor chip 25 and the connection electrodes 23 of the film substrate 22 are shared by an alloy of both constituent metals. Crystal bonding. In this case, the heating temperature is about 400 to 600 ° C., for example, since the softening temperature of the polyimide resin is about 230 ° C., the resin 24 interposed between the semiconductor chip 25 and the film substrate 22 is heated. The semiconductor chip 25 and the film substrate 22 are softened and then solidified by cooling, and the solidified resin 24 adheres the semiconductor chip 25 and the film substrate 22.

【0010】ここで、好ましい金属材料の組合わせの一
例としては、バンプ電極26を金、メッキ層23bをス
ズからそれぞれ構成した場合と、バンプ電極26を金、
メッキ層23bを半田からそれぞれ構成した場合と、バ
ンプ電極26を半田、メッキ層23bを金からそれぞれ
構成した場合とがあげられる。これらの場合には、バン
プ電極26とメッキ層23bとの間に金とスズとの共晶
合金が形成され、この金とスズとの共晶合金によってバ
ンプ電極26と接続電極23とが共晶接合される。
Here, as an example of a preferable combination of metal materials, a case where the bump electrode 26 is made of gold and the plating layer 23b is made of tin, and a case where the bump electrode 26 is made of gold and
There are a case where the plating layer 23b is made of solder, and a case where the bump electrode 26 is made of solder and the plating layer 23b is made of gold. In these cases, a eutectic alloy of gold and tin is formed between the bump electrode 26 and the plating layer 23b, and the eutectic alloy of gold and tin causes the bump electrode 26 and the connection electrode 23 to be eutectic. Joined.

【0011】このように、半導体チップ25のバンプ電
極26とフィルム基板22の接続電極23とが共晶接合
されているので、バンプ電極26と接続電極23との接
合部分の電気抵抗を低くすることができ、高周波特性を
良くすることができる。また、半導体チップ25とフィ
ルム基板22とがその間に介在された樹脂24によって
接着されているので、フィルム基板22の内部に加熱に
よる残留応力が生じ、この残留応力によってフィルム基
板22が元の状態に戻ろうとしても、樹脂24がそれを
させず、バンプ電極26と接続電極23との接合部分が
剥がれるのを防止し、接合不良が生じないようにするこ
とができる。また、樹脂24は熱可塑性樹脂からなって
いるので、加熱すると再び軟化する。このため、加熱す
ることにより半導体チップ25をフィルム基板22から
容易に取り外すことができ、半導体チップ25を容易に
リペアすることができる。
As described above, since the bump electrodes 26 of the semiconductor chip 25 and the connection electrodes 23 of the film substrate 22 are eutectic-bonded, the electrical resistance at the junction between the bump electrodes 26 and the connection electrodes 23 can be reduced. And high frequency characteristics can be improved. Further, since the semiconductor chip 25 and the film substrate 22 are bonded by the resin 24 interposed therebetween, residual stress is generated inside the film substrate 22 by heating, and the residual stress causes the film substrate 22 to return to its original state. Even if it is attempted to return, the resin 24 does not do so, so that the joint between the bump electrode 26 and the connection electrode 23 can be prevented from peeling off, so that a joint failure does not occur. Further, since the resin 24 is made of a thermoplastic resin, it is softened again when heated. Therefore, the semiconductor chip 25 can be easily removed from the film substrate 22 by heating, and the semiconductor chip 25 can be easily repaired.

【0012】なお、上記実施形態では、フィルム基板2
2の上面における所定の箇所に樹脂24を塗布したが、
これに限らず、図3に示す塗布位置の変形例のように、
半導体チップ25の下面における所定の箇所に樹脂24
を塗布してもよい。また、上記実施形態では、回路基板
を単層のフィルム基板22としたが、これに限らず、図
4に示す回路基板の第1変形例のように、多層のフィル
ム基板22としてもよい。また、上記実施形態では、回
路基板を片面配線のフィルム基板22としたが、これに
限らず、図5に示す回路基板の第2変形例のように、両
面配線のフィルム基板22としてもよい。また、上記実
施形態では、樹脂24としてポリイミド樹脂、シリコー
ン樹脂などの熱可塑性樹脂について説明したが、これに
限らず、エポキシ樹脂、フェノール樹脂などの熱硬化性
樹脂であってもよく、さらに熱可塑性樹脂と熱硬化性樹
脂との混合物であってもよい。さらに、上記実施形態で
は、半導体チップ25の下面にバンプ電極26を設けた
が、これに限らず、フィルム基板22の接続電極23上
にバンプ電極26を設けるようにしてもよい。この場
合、半導体チップ25よりもフィルム基板22の方が安
価であるので、不良発生時の金銭ロスを少なくすること
ができる。
In the above embodiment, the film substrate 2
The resin 24 was applied to a predetermined location on the upper surface of the second 2,
Not limited to this, as in the modification of the application position shown in FIG.
Resin 24 is provided at a predetermined location on the lower surface of semiconductor chip 25.
May be applied. Further, in the above-described embodiment, the circuit board is a single-layer film board 22, but the circuit board is not limited to this, and may be a multilayer film board 22 as in a first modification of the circuit board shown in FIG. Further, in the above-described embodiment, the circuit board is a single-sided wiring film substrate 22, but is not limited to this, and may be a double-sided wiring film substrate 22 as in a second modification of the circuit board shown in FIG. In the above embodiment, a thermoplastic resin such as a polyimide resin or a silicone resin is described as the resin 24. However, the present invention is not limited to this, and a thermosetting resin such as an epoxy resin or a phenol resin may be used. It may be a mixture of a resin and a thermosetting resin. Further, in the above embodiment, the bump electrodes 26 are provided on the lower surface of the semiconductor chip 25. However, the present invention is not limited to this, and the bump electrodes 26 may be provided on the connection electrodes 23 of the film substrate 22. In this case, since the film substrate 22 is cheaper than the semiconductor chip 25, it is possible to reduce money loss when a defect occurs.

【0013】[0013]

【発明の効果】以上説明したように、この発明によれ
ば、半導体チップのバンプ電極と回路基板の接続電極と
が共晶接合されているので、バンプ電極と接続電極との
接合部分の電気抵抗を低くすることができ、高周波特性
を良くすることができる。また、半導体チップと回路基
板とがその間に介在された樹脂によって接着されている
ので、回路基板の内部に加熱による残留応力が生じ、こ
の残留応力によって回路基板が元の状態に戻ろうとして
も樹脂がそれを防ぎ、バンプ電極と接続電極との接合部
分が剥がれるのを防止し、接合不良が生じないようにす
ることができる。
As described above, according to the present invention, since the bump electrode of the semiconductor chip and the connection electrode of the circuit board are eutectic-bonded, the electrical resistance of the junction between the bump electrode and the connection electrode is increased. Can be reduced, and high-frequency characteristics can be improved. In addition, since the semiconductor chip and the circuit board are bonded by the resin interposed therebetween, residual stress due to heating is generated inside the circuit board, and even if the circuit board attempts to return to the original state due to the residual stress. However, it is possible to prevent the bonding portion between the bump electrode and the connection electrode from peeling off, and to prevent the occurrence of poor bonding.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の一実施形態における半導体装置の製
造に際し、フィルム基板の上面に樹脂を塗布し、半導体
チップをフィルム基板上に配置した状態を示す断面図。
FIG. 1 is a cross-sectional view showing a state in which a resin is applied to an upper surface of a film substrate and a semiconductor chip is arranged on the film substrate in manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】同半導体装置の断面図。FIG. 2 is a cross-sectional view of the semiconductor device.

【図3】実施形態における樹脂の塗布位置の変形例を示
す断面図。
FIG. 3 is a cross-sectional view showing a modification of the application position of the resin in the embodiment.

【図4】実施形態における回路基板の第1変形例を示す
断面図。
FIG. 4 is an exemplary sectional view showing a first modification of the circuit board according to the embodiment;

【図5】実施形態における回路基板の第2変形例を示す
断面図。
FIG. 5 is an exemplary sectional view showing a second modification of the circuit board according to the embodiment;

【図6】従来の半導体装置の一例を示す断面図。FIG. 6 is a cross-sectional view illustrating an example of a conventional semiconductor device.

【図7】従来の問題点を説明するための断面図。FIG. 7 is a cross-sectional view for explaining a conventional problem.

【図8】従来の半導体装置の別の例を示す断面図。FIG. 8 is a sectional view showing another example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

22 フィルム基板 23 接続電極 23a 接続電極本体 23b メッキ層 24 樹脂 25 半導体チップ 26 バンプ電極 DESCRIPTION OF SYMBOLS 22 Film board 23 Connection electrode 23a Connection electrode main body 23b Plating layer 24 Resin 25 Semiconductor chip 26 Bump electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップのバンプ電極と回路基板の
接続電極とが共晶接合されているとともに、前記半導体
チップと前記回路基板とがその間に介在された樹脂によ
って接着されていることを特徴とする半導体装置。
1. The semiconductor device according to claim 1, wherein the bump electrodes of the semiconductor chip and the connection electrodes of the circuit board are eutectic bonded, and the semiconductor chip and the circuit board are bonded by a resin interposed therebetween. Semiconductor device.
【請求項2】 前記回路基板はフィルム基板からなるこ
とを特徴とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein said circuit board comprises a film substrate.
【請求項3】 前記バンプ電極は金からなり、前記接続
電極は接続電極本体と該接続電極本体の表面に形成され
たスズメッキ層とからなることを特徴とする請求項1ま
たは2記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the bump electrode is made of gold, and the connection electrode is made of a connection electrode body and a tin plating layer formed on a surface of the connection electrode body. .
【請求項4】 前記樹脂は熱可塑性樹脂または熱硬化性
樹脂からなることを特徴とする請求項1〜3のいずれか
に記載の半導体装置。
4. The semiconductor device according to claim 1, wherein said resin is made of a thermoplastic resin or a thermosetting resin.
JP19162196A 1996-07-03 1996-07-03 Semiconductor device Expired - Lifetime JP3269390B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19162196A JP3269390B2 (en) 1996-07-03 1996-07-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19162196A JP3269390B2 (en) 1996-07-03 1996-07-03 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH1022334A true JPH1022334A (en) 1998-01-23
JP3269390B2 JP3269390B2 (en) 2002-03-25

Family

ID=16277692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19162196A Expired - Lifetime JP3269390B2 (en) 1996-07-03 1996-07-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3269390B2 (en)

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JP2007232838A (en) * 2006-02-28 2007-09-13 Epson Imaging Devices Corp Electro-optical device, mounting structure, method of manufacturing the electro-optical device, and electronic equipment
US10004656B2 (en) 2007-10-15 2018-06-26 Alterg, Inc. Systems, methods and apparatus for differential air pressure devices
US10342461B2 (en) 2007-10-15 2019-07-09 Alterg, Inc. Method of gait evaluation and training with differential pressure system
US9642764B2 (en) 2009-05-15 2017-05-09 Alterg, Inc. Differential air pressure systems
US9914003B2 (en) 2013-03-05 2018-03-13 Alterg, Inc. Monocolumn unweighting systems
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