JP4069588B2 - Tape carrier and semiconductor device using the same - Google Patents

Tape carrier and semiconductor device using the same Download PDF

Info

Publication number
JP4069588B2
JP4069588B2 JP2001009888A JP2001009888A JP4069588B2 JP 4069588 B2 JP4069588 B2 JP 4069588B2 JP 2001009888 A JP2001009888 A JP 2001009888A JP 2001009888 A JP2001009888 A JP 2001009888A JP 4069588 B2 JP4069588 B2 JP 4069588B2
Authority
JP
Japan
Prior art keywords
tape carrier
lead
copper foil
cof
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001009888A
Other languages
Japanese (ja)
Other versions
JP2002217246A (en
Inventor
豊張 小泉
健司 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP2001009888A priority Critical patent/JP4069588B2/en
Publication of JP2002217246A publication Critical patent/JP2002217246A/en
Application granted granted Critical
Publication of JP4069588B2 publication Critical patent/JP4069588B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、液晶用及びＣＳＰ（Chip Scale Package）用ＴＡＢ（Tape Automated Bonding）テープや、プリンタ用あるいはＬＣＤ（Liquid Crystal Display：液晶表示装置）用ＴＡＢテープなどのテープキャリア、特にＣＯＦ（Chip on Film）接続のためのＴＡＢテープキャリアとそれを用いた半導体装置に関するものである。
【０００２】
【従来の技術】
従来のＴＡＢテープキャリアは、９〜３５μｍ厚さの銅箔をロールラミネート・キュア後、フォトレジストをコートしてプレキュアを行い露光して現像、ポストキュアした後、銅箔のエッチングを行い、リードを含む配線パターンを形成した後に、液状のフォトソルダレジストあるいはエポキシ系ソルダレジストを印刷コートして露光・現像しあるいはポストベークを行い、配線パターン上に絶縁保護膜層を形成していた。
【０００３】
さらに、このＴＡＢテープキャリアを用いて半導体装置パッケージを組み立てるには、図７に示すように、ボンディング治具２９及びボンディング・ステージ３０を用い、搭載した半導体素子２５の外部引きだし用電極上に形成された突起型電極（Ａｕバンプ２６）に、前記ＴＡＢテープキャリアの銅箔２の配線パターンの一部として形成したＳｎめっき２１の施されたリードを、加熱ボンディングツール（ボンディング治具２９）で熱圧着させるＣＯＦ接続構造としていた。
【０００４】
【発明が解決しようとする課題】
一般にＴＡＢテープキャリアは、銅箔が９〜３５μｍ厚さのものをラミネート・キュア後、液状のフォトレジストを塗布し、所定の露光・現像を経てエッチングし、銅箔パターンを形成している。
【０００５】
このフォトレジストを塗布する銅箔パターンの表面は平滑であり、その最大あらさが２．０μｍ未満となっている。このことは、次のような長所と欠点として現れる。
【０００６】
まず長所としては、フォトレジスト面（銅箔の表面）のあらさが小さく平滑（最大あらさＲｚ＝２．０μｍ未満）であることから、１８μｍ厚さの銅箔を使用しても微細なパターン（５０μｍピッチ）を均一にエッチングすることができ、５０〜６０μｍ配線ピッチでは歩留が良く、液晶あるいはＣＳＰ用のＴＡＢテープキャリアの製造の生産性が高い。
【０００７】
しかしながら、欠点として、半導体素子の外部引きだし用電極上に形成された突起型電極（Ａｕバンプ）に前記ＴＡＢテープキャリアのリードを加熱ボンディングツールで熱圧着させるＣＯＦ接続構造では、突起型電極（Ａｕバンプ）と前記ＴＡＢテープキャリアのリード表面のあらさが平滑のため、加圧時の摩擦が少なく、熱圧着の強度が小さくなって安定しないとう課題があった。
【０００８】
すなわち、銅箔表面のあらさが平滑（最大あらさＲｚ＝２．０μｍ未満）の場合、加圧時にリードの平滑な表面が、Ａｕバンプの上を滑り変形して、接合強度のばらつきが大きく、接合の信頼性が悪かった。
【０００９】
そこで、本発明の目的は、上記課題を解決し、加圧時の摩擦が大きく熱圧着による高い接合強度が得られるＣＯＦ用テープキャリア及びそれを用いた半導体装置を提供することにある。
【００１０】
【課題を解決するための手段】
上記目的を達成するため、本発明は、次のように構成したものである。
【００１１】
（１）請求項１の発明は、絶縁性の樹脂フィルムから成るテープ基材の片面に銅箔を貼り合わせ、該銅箔をフォトエッチングすることによりＣＯＦ接続のためのリードを含む配線パターンを形成し、その配線パターン上の前記ＣＯＦ接続のためのリードを除いた領域をソルダレジスト膜で保護すると共に前記ソルダレジスト膜から露出された前記ＣＯＦ接続のためのリード領域にＳｎ、Ｎｉ、Ａｕ等のめっきを施したＴＡＢテープキャリアにおいて、前記銅箔として前記テープ基材と反対側の面における最大あらさが２．０μｍ以上８μｍ以下に制御された銅箔を用いてなることを特徴とする。この場合、前記テープ基材はポリイミド樹脂フィルムから構成するとよい（請求項２）。
【００１２】
本発明においては、微細パターンＣＯＦ用のＴＡＢテープキャリアの構造として、前記銅箔が２〜１８μｍ厚さの電解あるいは圧延箔から成ることが好ましい（請求項３）。
【００１３】
また、本発明においては、前記配線パターン上に無電解めっきまたは電気めっきが施されている構成（請求項４）とするのが好ましい。
【００１４】
（２）請求項５の発明に係る半導体装置は、請求項１〜４のいずれかに記載のテープキャリアを用い、該テープキャリアに半導体素子を搭載し、半導体素子の外部引きだし用電極上に形成された突起型電極（Ａｕバンプ）に前記テープキャリアのＣＯＦ接続のためのリードを加熱ボンディングツールで熱圧着させたことを特徴とする。
【００１５】
本発明の要点は、上記した従来の問題を解決するため、銅箔２〜１８μｍ厚さの光沢表面、すなわち銅箔パターン表面の最大あらさが２．０μｍ以上８μｍ以下である「あらさの大きい箔」を使用するものであり、これにより、加圧時には、リードの荒れた表面が、Ａｕバンプの上を滑ることとなり、リードの荒れた表面が摩擦変形して接合強度のばらつきを減少させる。従って、安定した接合強度を保持することができ、接合強度の信頼性を高める。その結果、本発明のＴＡＢテープキャリアによれば、ＣＯＦの接続構造における接続信頼性及び歩留の改善と生産性を向上させることができる。
【００１６】
＜作用（要点の補足説明）＞
銅箔２〜１８μｍ厚さの光沢表面、すなわち、あらさの大きい箔を使用することにより、加圧時にリードの荒れた表面がＡｕバンプの上を滑る際に摩擦変形して、接合強度のばらつきを減少させ、安定した接合強度を保持するようになり、接合強度の信頼性が高くなる。
【００１７】
図１は、ボンディング治具２９及びボンディング・ステージ３０を用いて、搭載した半導体素子２５の外部引きだし用電極上に形成された突起型電極（Ａｕバンプ２６）に、ＴＡＢテープキャリアの銅箔２の配線パターンの一部として形成したＳｎめっき２１の施されたリードを、加熱ボンディングツール（ボンディング治具２９）で熱圧着させる場合を示している。図中、２２はポリイミド樹脂フィルムとして東レデュポン株式会社製の商品名「カプトンＥＮ」を用いたテープ基材である。
【００１８】
従来の図７のように、リード（銅箔２）の表面が平滑の場合、加圧時にＡｕバンプ２６の上を滑るため、熱圧着の強度が小さくなって安定しない。
【００１９】
これに対し、本発明の場合は、図１（ａ）のように、リード（銅箔２）が荒れた表面を有しているため、加圧時にリードがＡｕバンプ２６の上を滑る際に、摩擦変形しながら局部溶着する。すなわち、図１（ｂ）のように、銅箔２及びＡｕバンプ２６が塑性流動３１し、対接する部分が強く接合される。このため、接合強度のばらつきを減少させ、安定した熱圧着の接合強度を保持する。
【００２０】
【発明の実施の形態】
以下、本発明を図示の実施形態に基づいて説明する。
【００２１】
＜実施形態１＞
図３に本発明のＴＡＢテープキャリアとこれを用いた半導体装置の第１の実施例を示す。
【００２２】
厚さ７５μｍ、幅７０mmのポリイミド樹脂フィルムから成るテープ基材２０にエポキシ系接着剤３を貼り合わせたものに、パンチングで送り穴（パーフォレーション）を打ち抜きした後、これに三井金属鉱業製のＳＱ−ＶＬＰ箔銅箔（厚さ箔１８μｍ）（表面の最大あらさ３．０μｍ）のテープをラミネート・キュアし、接着剤使用の片面銅貼り１層ＣＣＬ（Copper Clad Laminate）を得た。
【００２３】
次にフォトアプリケーションで銅箔面を露光・エッチングして、銅箔信号層のＣＯＦ接続のためのインナリード４、入力側アウターリード１４及び出力側アウターリード１５を含む配線パターン（４０μｍピッチ）を形成した。
【００２４】
次に、この配線パターンに液状のソルダレジスト１６を塗布し、そのソルダレジスト塗布層から露出している領域（上記インナリード４等）に、無電解Ｓｎめっき２８を０．４μｍ厚さ施して完成品とした。このＴＡＢテープキャリアの場合、ＣＯＦ接続のためのインナリード４の表面の最大あらさが３．０μｍであり、これは２．０μｍ以上８μｍ以下の範囲内にある。
【００２５】
比較のため、三井金属鉱業製のＴＱＳ−ＶＬＰ箔（１２μｍ厚さ）（銅箔のレジスト面の最大あらさＲｚ＝２．０μｍ以下）を用い、これをラミネート・キュアした後、フォトアプリケーションで配線パターン（５０μｍピッチ）を形成した。その結果、この比較品に比較して、本発明のＣＯＦ用のＴＡＢテープキャリアは、特に断線、ショートが少なく（フォトレジストの密着性が良く）、歩留が向上した。
【００２６】
次に、上記ＴＡＢテープキャリアを用いて半導体装置を組み立てるため、該テープキャリアに半導体素子２５を搭載し、半導体素子の外部引きだし用電極上に形成された突起型電極（Ａｕバンプ２６）と、上記テープキャリアのＣＯＦ接続のためのインナリード４を、加熱ボンディングツールで熱圧着させ、半導体素子２５のフリップチップ・インナリードボンディングのＳｎ／Ａｕ接合（フリップチップ接合２４）を得た。そして、その接続部をアンダフィル剤８で充填し固めた。
【００２７】
本発明のインナリード４の荒れた表面の場合、アンダフィル剤８を充填する前の熱圧着の接合強度が、６ｇｆ｛１０-2Ｎ｝／リード１本と、強く安定した。一方、比較品の場合は、３〜６ｇｆ｛１０-2Ｎ｝／リード１本と、熱圧着の接合強度が不安定であった。
【００２８】
これは、本実施形態ではリード表面があれているため、Ａｕバンプ２６の上を滑る際に、摩擦変形しながら局部溶着することとなり、接合強度のばらつきを減少させ、安定した熱圧着の接合強度が保持できるものと推定される。
【００２９】
温度サイクル試験特性は、配線パターンの４０μｍピッチ部の熱圧着部の電気試験での確認では、−６５℃（３０分保持）、＋１２５℃（３０分保持）を１サイクルとして、１０００サイクル実施したが、試験中の熱圧着部の配線抵抗の増加もなく安定しており、信頼性に優れていることが判明した。
【００３０】
一方、図３に示すように、上記半導体素子の接合後、配線パターンの出力側アウターリード１５を、異方性導電膜１８を介して、ＬＣＤ（Liquid Crystal Display：液晶表示装置）の液晶パネルの透明電極／ガラス基板１７と接合した。これは、図２に示すように、テープ基材２２上のＳｎめっき２１付き銅箔２（出力側アウターリード１５）と、ガラス基板１７ａ上の透明電極１７ｂとの間に、Ｎｉ粒子５を含む異方性導電膜１８を介在させ、これをボンディング治具２９及びボンディング・ステージ３０を用いて押圧することにより、異方性導電膜１８及び銅箔２に塑性流動を起こさせて行った。
【００３１】
この結果、半導体素子接合後の異方性導電膜１８によるプリント基板へのアウターリード接合も、良好で液晶用として組み立てができた。
【００３２】
＜実施形態２＞
上記実施形態１では、接着剤使用の片面銅貼り１層ＣＣＬテープを用い、これに配線パターンを形成して微細パターンＣＯＦ用のＴＡＢテープキャリアを構成したが、図４に示すように、接着剤レス片面銅貼り１層ＣＣＬテープを用いて構成することもできる。
【００３３】
図４の実施形態の場合、テープ基材たる絶縁フィルム２０に、厚さ７５μｍで幅７０mmのポリイミド樹脂である東レデュポン株式会社製の商品名「カプトンＥＮ」を用い、このテープ基材に接着剤なしで銅箔２を貼り、これに配線パターンを形成した。
【００３４】
＜実施形態３＞
図５に本発明のＴＡＢテープキャリアとこれを用いた半導体装置の第３の実施例を示す。
【００３５】
まず図５（ａ）に示すように、厚さ５０μｍ、幅３５mmのポリイミド樹脂フィルムから成るテープ基材２０に、エポキシ系接着剤３を貼り合わせたものに、パンチングで送り穴（パーフォレーション）を打ち抜きし、はんだボール用ビアホール１２をレーザ加工して設けた後、これに三井金属鉱業製のＳＱ−ＶＬＰ箔銅箔（厚さ箔９μｍ）（表面の最大あらさ３．５μｍ）のテープを、その粗化処理面（最大あらさ３．５μｍ）を上に光沢面を接着層面にしてラミネート・キュアし、接着剤使用の片面銅貼り１層ＣＣＬを得た。
【００３６】
次にフォトアプリケーションで銅箔面を露光・エッチングして、銅箔信号層のＣＯＦ接続のためのインナリード４、入力側アウターリード１４及び出力側アウターリード１５を含む配線パターン（３０μｍピッチ）を形成した。
【００３７】
次に、この配線パターンに液状のソルダレジスト１６を塗布し、そのソルダレジスト膜（塗布層）から露出している領域（上記インナリード４等）に、無電解Ｓｎめっき２８を０．４μｍ厚さ施して、ＴＡＢ用テープキャリア１の完成品とした。このＴＡＢテープキャリアの場合、ＣＯＦ接続のためのインナリード４の表面の最大あらさが３．５μｍであり、これは２．０μｍ以上８μｍ以下の範囲内にある。
【００３８】
次に図５（ｂ）に示すように、上記ＴＡＢテープキャリア１を用いて半導体装置を組み立てた。すなわち、ＴＡＢテープキャリア１に半導体素子２５を搭載し、半導体素子の外部引きだし用電極上に形成された突起型電極（Ａｕバンプ２６）と、上記テープキャリアのＣＯＦ接続のためのインナリード４を、加熱ボンディングツールで熱圧着させ、半導体素子２５のフリップチップ・インナリードボンディングのＳｎ／Ａｕ接合（フリップチップ接合２４）を得た。そして、その接続部をアンダフィル剤８で充填し固めた。また、はんだボール用ビアホール１２にはんだボール１０を搭載して、半導体装置パッケージを完成させた。
【００３９】
その結果、本実施形態のＣＯＦ用のＴＡＢテープキャリア１は、特に断線、ショートが少なく（フォトレジストの密着性が良く）、歩留が向上した。
【００４０】
また、半導体素子２５のフリップチップ接合後、異方性導電膜によるプリント基板へのアウタリード接合も良好で、ＣＯＦタイプのＬＣＤ用ＴＡＢテープキャリアを歩留良く生産できた。
【００４１】
温度サイクル試験特性は、配線パターンの３０μｍピッチ部の異方性導電膜接合部の電気試験での確認では、−６５℃（３０分保持）、＋１２５℃（３０分保持）を１サイクルとして、１０００サイクル実施したが、試験中の熱圧着部の配線抵抗の増加も少なく、接合が安定しており、信頼性に優れていることが判明した。
【００４２】
＜実施形態４＞
上記実施形態３では、接着剤使用の片面銅貼り１層ＣＣＬテープを用い、これに配線パターンを形成して微細パターンＣＯＦ用のＴＡＢテープキャリアを構成したが、図６（ａ）に示すように、接着剤レス片面銅貼り１層ＣＣＬテープを用いてＴＡＢテープキャリア１を構成し、これを用いて図６（ｂ）のように半導体装置のパッケージを組み立てることもできる。
【００４３】
＜他の実施形態、変形例＞
上記実施形態では、接着剤使用の片面銅貼り１層ＣＣＬ又は接着剤レス片面銅貼り１層ＣＣＬのテープを用いたが、テープ基材の両面に配線層を有する２層ＣＣＬのテープを用いてＴＡＢテープキャリアを構成することもできる。
【００４４】
またテープ基材としては、ポリイミド樹脂フィルムの他、ガラスエポキシテープ等の樹脂フィルムを用いることもできる。
【００４５】
ここで、上記実施形態（図３〜図６）の作用効果をまとめれば、次のようになる。
【００４６】
（１）本実施形態のＴＡＢテープキャリアは、上記のように銅箔表面の最大表面のあらさがＲｚ＝２μｍ以上８μｍ以下である「あらさの大きい箔」に制御されており、フォトレジストが均一に塗布できると共に、フォトレジストの密着強度が向上することから、微細配線のエッチング歩留も向上し、品質の安定したＣＯＦ用のＴＡＢテープキャリアを供給することができる。
【００４７】
（２）本実施形態のＴＡＢテープキャリアは、微細配線（５０μｍピッチ以下３０μｍピッチ）のエッチング形状が良好であり、エッチングファクタが３．５以上と向上する。また、Ｓｎめっき後端リードと、半導体素子の外部引きだし用電極に形成された突起型電極（Ａｕバンプ）との熱圧着に関し、その接合強度が安定しており優れている。また温度サイクル試験（−６５℃と１５０℃）での信頼性が高く優れている。
【００４８】
（３）本実施形態のＴＡＢテープキャリアのプリント基板へのアウタリード接合は、異方性導電膜により良好な組み立てもでき、しかも４０μｍピッチの配線の形成が容易なため、スリムな設計が可能となり、小型化に容易な構造のＴＡＢテープキャリアとＣＯＦ接続構造を安定して供給することができる。
【００４９】
（４）本実施形態のＴＡＢテープキャリアでの半導体の突起電極との接合は、従来の限界を超えて歩留と生産性が良好であり、しかも安定して量産することができ、品質の安定したＣＯＦ接続構造とＣＯＦ用のＴＡＢテープキャリアを供給することができる。
【００５０】
＜使用方法、応用システムなど＞
本発明のＴＡＢテープキャリアは、耐マイグレーション特性に優れた、微細配線（ピッチ６０μｍ以下）のデバイスホール無しのフリップチップ接続用および図５及び図６のようなデバイスホール無しのフリップチップ接合タイプのＣＳＰ・ＢＧＡ用として適用することが可能である。
【００５１】
【発明の効果】
以上説明したように本発明によれば、次のような優れた効果が得られる。
【００５２】
（１）請求項１〜６の発明に係るテープキャリアは、銅箔の配線パターンにおけるＣＯＦ接続のためのリード表面の最大あらさが２．０μｍ以上８μｍ以下である「あらさの大きい箔」を使用しているため、加圧時には、リードの荒れた表面が、Ａｕバンプの上を滑ることとなり、リードの荒れた表面が摩擦変形して接合強度のばらつきを減少させる。従って、安定した接合強度を保持することができ、接合強度の信頼性の高いＴＡＢテープキャリアを得ることができる。その結果、本発明のテープキャリアによれば、ＣＯＦの接続構造における接続信頼性及び歩留の改善と生産性を向上させることができる。
【００５３】
また本発明のＴＡＢテープキャリアは、上記のように銅箔表面の最大表面のあらさがＲｚ＝２μｍ以上８μｍ以下である「あらさの大きい箔」に制御されているため、フォトレジストが均一に塗布できると共に、フォトレジストの密着強度が向上することから、微細配線のエッチング歩留も向上し、品質の安定したＣＯＦ用のＴＡＢテープキャリアを供給することができる。
【００５４】
（２）請求項７の発明に係る半導体装置は、請求項１〜６のいずれかに記載のテープキャリアを用い、半導体素子の外部引きだし用電極上に形成された突起型電極に、テープキャリアのＣＯＦ接続のためのリードを加熱ボンディングツールで熱圧着させる構造であるため、接続信頼性の高いＣＯＦの接続構造の半導体装置を、歩留良く生産することができる。
【図面の簡単な説明】
【図１】本発明のＴＡＢテープキャリアにおけるＣＯＦ接続構造を示したもので、（ａ）は接続前の横断面図、（ｂ）は接続後の横断面図である。
【図２】本発明のＴＡＢテープキャリアにおける液晶パネルとの接続構造を示した横断面図である。
【図３】本発明の第１の実施形態に係るＴＡＢテープキャリアを用いた半導体装置の横断面図である。
【図４】本発明の第２の実施形態に係るＴＡＢテープキャリアを用いた半導体装置の横断面図である。
【図５】本発明の第３の実施形態を示したもので、（ａ）はＴＡＢテープキャリアの横断面図、（ｂ）はそれを用いた半導体装置の横断面図である。
【図６】本発明の第４の実施形態を示したもので、（ａ）はＴＡＢテープキャリアの横断面図、（ｂ）はそれを用いた半導体装置の横断面図である。
【図７】従来のＴＡＢテープキャリアのＣＯＦ接続構造を示した図である。
【符号の説明】
１ ＴＡＢ用テープキャリア
２ 銅箔
３ 接着剤
４ インナリード
１０ はんだボール
１２ はんだボール用ビアホール
１４ 入力側アウターリード
１５ 出力側アウターリード
１６ ソルダレジスト
１７ 透明電極／ガラス基板
１８ 異方性導電膜
２０、２２ テープ基材
２１、２８ Ｓｎめっき
２４ フリップチップ接合
２５ 半導体素子
２６ Ａｕバンプ
３１ 塑性流動[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a tape carrier such as TAB (Tape Automated Bonding) tape for liquid crystal and CSP (Chip Scale Package), TAB tape for printer or LCD (Liquid Crystal Display), particularly COF (Chip on Film). ) A TAB tape carrier for connection and a semiconductor device using the TAB tape carrier.
[0002]
[Prior art]
A conventional TAB tape carrier has a 9-35 μm thick copper foil roll-laminated and cured, coated with a photoresist, pre-cured, exposed, developed, post-cured, etched copper foil, and lead After forming the wiring pattern including the wiring pattern, a liquid photo solder resist or an epoxy solder resist is printed and exposed, developed, or post-baked to form an insulating protective film layer on the wiring pattern.
[0003]
Further, in order to assemble a semiconductor device package using this TAB tape carrier, as shown in FIG. 7, a bonding jig 29 and a bonding stage 30 are used and formed on the external extraction electrode of the mounted semiconductor element 25. The lead having the Sn plating 21 formed as a part of the wiring pattern of the copper foil 2 of the TAB tape carrier is thermocompression-bonded to the protruding electrode (Au bump 26) with a heating bonding tool (bonding jig 29). It was set as the COF connection structure to be made.
[0004]
[Problems to be solved by the invention]
In general, a TAB tape carrier is formed by laminating and curing a copper foil having a thickness of 9 to 35 μm, applying a liquid photoresist, etching through predetermined exposure and development, and forming a copper foil pattern.
[0005]
The surface of the copper foil pattern to which this photoresist is applied is smooth, and the maximum roughness is less than 2.0 μm. This manifests itself as the following advantages and disadvantages.
[0006]
First, since the roughness of the photoresist surface (the surface of the copper foil) is small and smooth (maximum roughness Rz = less than 2.0 μm), a fine pattern (50 μm) can be obtained even when an 18 μm thick copper foil is used. (Pitch) can be uniformly etched, with a wiring pitch of 50-60 μm, the yield is good, and the productivity of manufacturing a TAB tape carrier for liquid crystal or CSP is high.
[0007]
However, as a disadvantage, in the COF connection structure in which the lead of the TAB tape carrier is thermocompression-bonded to the protruding electrode (Au bump) formed on the external extraction electrode of the semiconductor element with a heating bonding tool, the protruding electrode (Au bump) ) And the roughness of the lead surface of the TAB tape carrier, there is a problem that there is little friction during pressurization, the strength of thermocompression bonding is reduced, and it is not stable.
[0008]
That is, when the roughness of the copper foil surface is smooth (maximum roughness Rz = less than 2.0 μm), the smooth surface of the lead slides and deforms on the Au bump during pressurization, resulting in a large variation in bonding strength. The reliability of was bad.
[0009]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a COF tape carrier and a semiconductor device using the same, which can solve the above-described problems and can obtain a high bonding strength by thermocompression bonding with a large friction during pressing.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured as follows.
[0011]
(1) The invention of claim 1 forms a wiring pattern including leads for COF connection by bonding a copper foil to one side of a tape base material made of an insulating resin film and photoetching the copper foil. and, Sn in the lead region for the exposed the COF connected from the solder resist film to protect the area except the lead for the COF connections on the wiring pattern by Seo Rudarejisuto film, Ni, such as Au in TAB tape carriers facilities plating, characterized by comprising using a copper foil maximum roughness is controlled to 2.0μm or more 8μm or less in a surface opposite to the tape base material as the copper foil. In this case, the tape base material is preferably composed of a polyimide resin film.
[0012]
In the present invention, as the structure of the TAB tape carrier for the fine pattern COF, the copper foil is preferably made of electrolytic or rolled foil having a thickness of 2 to 18 μm.
[0013]
Moreover, in this invention, it is preferable to set it as the structure (Claim 4 ) by which the electroless plating or electroplating is given on the said wiring pattern.
[0014]
(2) A semiconductor device according to the invention of claim 5 uses the tape carrier according to any one of claims 1 to 4 , a semiconductor element is mounted on the tape carrier, and is formed on an external lead electrode of the semiconductor element A lead for the COF connection of the tape carrier is thermocompression bonded to the protruding electrode (Au bump) by a heat bonding tool.
[0015]
The main point of the present invention is to solve the above-mentioned conventional problems, a glossy surface having a thickness of 2 to 18 μm of copper foil, that is, a copper foil pattern surface having a maximum roughness of 2.0 μm or more and 8 μm or less “foil with large roughness” As a result, during pressurization, the rough surface of the lead slides on the Au bump, and the rough surface of the lead is frictionally deformed to reduce the variation in bonding strength. Therefore, stable bonding strength can be maintained, and the reliability of bonding strength is increased. As a result, according to the TAB tape carrier of the present invention, it is possible to improve the connection reliability and yield in the COF connection structure and the productivity.
[0016]
<Operation (supplementary explanation of key points)>
By using a glossy surface with a copper foil thickness of 2 to 18 μm, that is, a rough foil, when the rough surface of the lead slides on the Au bump during pressurization, frictional deformation occurs, resulting in uneven bonding strength. As a result, the stable bonding strength is maintained, and the reliability of the bonding strength is increased.
[0017]
FIG. 1 shows a method for forming a copper foil 2 of a TAB tape carrier on a protruding electrode (Au bump 26) formed on an external extraction electrode of a mounted semiconductor element 25 using a bonding jig 29 and a bonding stage 30. The case where the lead with Sn plating 21 formed as a part of the wiring pattern is thermocompression bonded with a heating bonding tool (bonding jig 29) is shown. In the figure, 22 is a tape base material using a trade name “Kapton EN” manufactured by Toray DuPont Co., Ltd. as a polyimide resin film.
[0018]
When the surface of the lead (copper foil 2) is smooth as shown in FIG. 7 of the prior art, the surface of the Au bump 26 is slid when pressed, so that the strength of thermocompression bonding becomes small and unstable.
[0019]
On the other hand, in the case of the present invention, as shown in FIG. 1A, the lead (copper foil 2) has a rough surface. Therefore, when the lead slides on the Au bump 26 during pressurization. , Local welding while frictional deformation. That is, as shown in FIG. 1B, the copper foil 2 and the Au bump 26 are plastically flowed 31, and the contacting portions are strongly joined. For this reason, the dispersion | variation in joining strength is reduced and the joining strength of the stable thermocompression bonding is maintained.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on illustrated embodiments.
[0021]
<Embodiment 1>
FIG. 3 shows a first embodiment of a TAB tape carrier of the present invention and a semiconductor device using the same.
[0022]
After punching a perforation by punching a tape base material 20 made of a polyimide resin film having a thickness of 75 μm and a width of 70 mm, the SQ- A tape of VLP foil copper foil (thickness foil 18 μm) (maximum surface roughness 3.0 μm) was laminated and cured to obtain a single-layer copper-laminated CCL (Copper Clad Laminate) using an adhesive.
[0023]
Next, the copper foil surface is exposed and etched with a photo application to form a wiring pattern (40 μm pitch) including the inner lead 4, the input side outer lead 14 and the output side outer lead 15 for COF connection of the copper foil signal layer. did.
[0024]
Next, a liquid solder resist 16 is applied to the wiring pattern, and electroless Sn plating 28 is applied to a region exposed from the solder resist coating layer (the inner lead 4 and the like) to a thickness of 0.4 μm. It was a product. In the case of this TAB tape carrier, the maximum roughness of the surface of the inner lead 4 for COF connection is 3.0 μm, which is in the range of 2.0 μm to 8 μm.
[0025]
For comparison, TQS-VLP foil (12 μm thickness) (maximum roughness of copper foil resist surface Rz = 2.0 μm or less) manufactured by Mitsui Mining & Smelting Co., Ltd. (50 μm pitch) was formed. As a result, compared with this comparative product, the TAB tape carrier for COF of the present invention had particularly few disconnections and shorts (good photoresist adhesion) and improved yield.
[0026]
Next, in order to assemble a semiconductor device using the TAB tape carrier, a semiconductor element 25 is mounted on the tape carrier, a protruding electrode (Au bump 26) formed on the external lead electrode of the semiconductor element, and the above The inner lead 4 for the COF connection of the tape carrier was thermocompression bonded with a heating bonding tool to obtain a Sn / Au bonding (flip chip bonding 24) of flip chip / inner lead bonding of the semiconductor element 25. Then, the connecting portion was filled with an underfill agent 8 and hardened.
[0027]
In the case of the rough surface of the inner lead 4 of the present invention, the bonding strength of the thermocompression bonding before filling the underfill agent 8 was strong and stable at 6 gf {10 −2 N} / one lead. On the other hand, in the case of the comparative product, the bonding strength of 3 to 6 gf {10 −2 N} / one lead and thermocompression bonding was unstable.
[0028]
In this embodiment, since the lead surface is raised, when sliding on the Au bump 26, it is locally welded while being frictionally deformed, reducing variations in bonding strength, and stable bonding strength of thermocompression bonding. Is presumed to be retained.
[0029]
As for the temperature cycle test characteristics, in the confirmation in the electrical test of the thermocompression bonding part of the 40 μm pitch part of the wiring pattern, 1000 cycles were performed with −65 ° C. (holding for 30 minutes) and + 125 ° C. (holding for 30 minutes) as one cycle. As a result, it was found that the wiring resistance of the thermocompression bonding part under test was stable without increasing, and the reliability was excellent.
[0030]
On the other hand, as shown in FIG. 3, after bonding the semiconductor elements, the output side outer leads 15 of the wiring pattern are connected to the liquid crystal panel of an LCD (Liquid Crystal Display) via an anisotropic conductive film 18. Bonded to the transparent electrode / glass substrate 17. This includes Ni particles 5 between the copper foil 2 with Sn plating 21 (output-side outer lead 15) on the tape base material 22 and the transparent electrode 17b on the glass substrate 17a, as shown in FIG. The anisotropic conductive film 18 was interposed and pressed using a bonding jig 29 and a bonding stage 30 to cause plastic flow in the anisotropic conductive film 18 and the copper foil 2.
[0031]
As a result, outer over lead bonding to a printed circuit board by the anisotropic conductive film 18 after the semiconductor device junctions were also able to assemble a good liquid crystal.
[0032]
<Embodiment 2>
In the first embodiment, a single-layer copper-clad single-layer CCL tape using an adhesive is used, and a wiring pattern is formed on the CCL tape to form a TAB tape carrier for a fine pattern COF. As shown in FIG. It is also possible to use a single-layer CCL tape with a single-sided copper bonding.
[0033]
In the case of the embodiment of FIG. 4, the product name “Kapton EN” manufactured by Toray DuPont Co., Ltd., which is a polyimide resin having a thickness of 75 μm and a width of 70 mm, is used for the insulating film 20 as a tape base material. The copper foil 2 was pasted without forming a wiring pattern thereon.
[0034]
<Embodiment 3>
FIG. 5 shows a third embodiment of the TAB tape carrier of the present invention and a semiconductor device using the same.
[0035]
First, as shown in FIG. 5A, punching holes (perforations) are punched out on a tape substrate 20 made of a polyimide resin film having a thickness of 50 μm and a width of 35 mm, and an epoxy adhesive 3 bonded thereto. After the solder ball via hole 12 is formed by laser processing, a tape of SQ-VLP foil copper foil (thickness foil 9 μm) (maximum surface roughness 3.5 μm) manufactured by Mitsui Mining & Smelting Co., Ltd. Lamination and curing was performed with the surface to be treated (maximum roughness 3.5 μm) and the glossy surface as the adhesive layer surface, to obtain a single-sided copper-clad CCL using an adhesive.
[0036]
Next, the copper foil surface is exposed and etched with a photo application to form a wiring pattern (30 μm pitch) including the inner lead 4, the input side outer lead 14, and the output side outer lead 15 for COF connection of the copper foil signal layer. did.
[0037]
Next, a liquid solder resist 16 is applied to the wiring pattern, and an electroless Sn plating 28 is 0.4 μm thick on a region exposed from the solder resist film (coating layer) (the inner lead 4 and the like). Thus, a finished product of the TAB tape carrier 1 was obtained. In the case of this TAB tape carrier, the maximum roughness of the surface of the inner lead 4 for COF connection is 3.5 μm, which is in the range of 2.0 μm to 8 μm.
[0038]
Next, as shown in FIG. 5B, a semiconductor device was assembled using the TAB tape carrier 1. That is, the semiconductor element 25 is mounted on the TAB tape carrier 1, and the protruding electrode (Au bump 26) formed on the external extraction electrode of the semiconductor element, and the inner lead 4 for the COF connection of the tape carrier, A heat bonding tool was used for thermocompression bonding to obtain a flip chip / inner lead bonding Sn / Au bonding (flip chip bonding 24) of the semiconductor element 25. Then, the connecting portion was filled with an underfill agent 8 and hardened. Also, the solder ball 10 was mounted in the solder ball via hole 12 to complete the semiconductor device package.
[0039]
As a result, the TAB tape carrier 1 for COF of this embodiment has particularly few disconnections and shorts (good adhesion of the photoresist) and improved yield.
[0040]
Further, after the flip chip bonding of the semiconductor element 25, the outer lead bonding to the printed circuit board by the anisotropic conductive film was also good, and a COF type TAB tape carrier for LCD could be produced with a high yield.
[0041]
The temperature cycle test characteristics are as follows: -65 ° C (30 minutes hold), + 125 ° C (30 minutes hold) as one cycle in the electrical test of the anisotropic conductive film junction of the 30 μm pitch part of the wiring pattern. Although the cycle was carried out, it was found that there was little increase in the wiring resistance of the thermocompression bonding part under test, the bonding was stable, and the reliability was excellent.
[0042]
<Embodiment 4>
In the third embodiment, a single-layer copper-clad single-layer CCL tape using an adhesive is used, and a wiring pattern is formed on the CCL tape to form a TAB tape carrier for a fine pattern COF. As shown in FIG. The TAB tape carrier 1 can be constituted by using an adhesiveless single-sided copper-clad single-layer CCL tape, and a semiconductor device package can be assembled using the TAB tape carrier 1 as shown in FIG.
[0043]
<Other embodiments, modified examples>
In the said embodiment, although the tape of the single-sided copper pasting 1 layer CCL of adhesive use or the adhesiveless single-sided copper pasting 1 layer CCL was used, the tape of the 2 layer CCL which has a wiring layer on both surfaces of a tape base material is used. A TAB tape carrier can also be constructed.
[0044]
Moreover, as a tape base material, resin films, such as a glass epoxy tape other than a polyimide resin film, can also be used.
[0045]
Here, it is as follows if the effect of the said embodiment (FIGS. 3-6) is put together.
[0046]
(1) In the TAB tape carrier of this embodiment, the roughness of the maximum surface of the copper foil surface is controlled to “large foil” with Rz = 2 μm to 8 μm as described above, and the photoresist is uniform. Since it can be applied and the adhesion strength of the photoresist is improved, the etching yield of fine wiring is also improved, and a TAB tape carrier for COF with stable quality can be supplied.
[0047]
(2) The TAB tape carrier of this embodiment has an excellent etching shape of fine wiring (50 μm pitch or less and 30 μm pitch), and an etching factor is improved to 3.5 or more. Further, regarding the thermocompression bonding between the Sn plating rear end lead and the protruding electrode (Au bump) formed on the external extraction electrode of the semiconductor element, the bonding strength is stable and excellent. In addition, the reliability in the temperature cycle test (−65 ° C. and 150 ° C.) is high and excellent.
[0048]
(3) The outer lead bonding of the TAB tape carrier of the present embodiment to the printed circuit board can be satisfactorily assembled with an anisotropic conductive film, and because it is easy to form wiring with a pitch of 40 μm, a slim design is possible. It is possible to stably supply a TAB tape carrier and a COF connection structure that are easy to downsize.
[0049]
(4) The TAB tape carrier of the present embodiment is bonded to the semiconductor bump electrode so that the yield and productivity are good and the mass production is stable and the quality is stable. The COF connection structure and the TAB tape carrier for COF can be supplied.
[0050]
<Usage method, application system, etc.>
The TAB tape carrier of the present invention is excellent in migration resistance, for flip chip connection without a device hole of fine wiring (pitch of 60 μm or less), and a flip chip bonding type CSP without a device hole as shown in FIGS. -It can be applied for BGA.
[0051]
【The invention's effect】
As described above, according to the present invention, the following excellent effects can be obtained.
[0052]
(1) The tape carrier according to the first to sixth aspects of the present invention uses a “foil with a large roughness” in which the maximum roughness of the lead surface for COF connection in the copper foil wiring pattern is 2.0 μm or more and 8 μm or less. Therefore, during pressurization, the rough surface of the lead slides on the Au bump, and the rough surface of the lead is frictionally deformed to reduce the variation in bonding strength. Therefore, stable bonding strength can be maintained, and a TAB tape carrier with high bonding strength reliability can be obtained. As a result, according to the tape carrier of the present invention, it is possible to improve the connection reliability and yield in the COF connection structure and the productivity.
[0053]
In addition, since the TAB tape carrier of the present invention is controlled to a “large foil” having a maximum roughness of the copper foil surface of Rz = 2 μm or more and 8 μm or less as described above, the photoresist can be applied uniformly. In addition, since the adhesion strength of the photoresist is improved, the etching yield of the fine wiring is also improved, and a TAB tape carrier for COF with stable quality can be supplied.
[0054]
(2) A semiconductor device according to a seventh aspect of the present invention uses the tape carrier according to any one of the first to sixth aspects of the present invention, and a protrusion-type electrode formed on the external lead electrode of the semiconductor element, Since the lead for COF connection is thermocompression bonded with a heat bonding tool, a semiconductor device having a COF connection structure with high connection reliability can be produced with high yield.
[Brief description of the drawings]
1A and 1B show a COF connection structure in a TAB tape carrier of the present invention, in which FIG. 1A is a cross-sectional view before connection, and FIG. 1B is a cross-sectional view after connection.
FIG. 2 is a cross-sectional view showing a connection structure with a liquid crystal panel in a TAB tape carrier of the present invention.
FIG. 3 is a cross-sectional view of a semiconductor device using a TAB tape carrier according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view of a semiconductor device using a TAB tape carrier according to a second embodiment of the present invention.
5A and 5B show a third embodiment of the present invention, in which FIG. 5A is a cross-sectional view of a TAB tape carrier, and FIG. 5B is a cross-sectional view of a semiconductor device using the TAB tape carrier.
6A and 6B show a fourth embodiment of the present invention, in which FIG. 6A is a transverse sectional view of a TAB tape carrier, and FIG. 6B is a transverse sectional view of a semiconductor device using the same.
FIG. 7 is a view showing a COF connection structure of a conventional TAB tape carrier.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 TAB tape carrier 2 Copper foil 3 Adhesive 4 Inner lead 10 Solder ball 12 Solder ball via hole 14 Input side outer lead 15 Output side outer lead 16 Solder resist 17 Transparent electrode / glass substrate 18 Anisotropic conductive film 20, 22 Tape base material 21, 28 Sn plating 24 Flip chip bonding 25 Semiconductor element 26 Au bump 31 Plastic flow

Claims (5)

絶縁性の樹脂フィルムから成るテープ基材の片面に銅箔を貼り合わせ、該銅箔をフォトエッチングすることによりＣＯＦ接続のためのリードを含む配線パターンを形成し、その配線パターン上の前記ＣＯＦ接続のためのリードを除いた領域をソルダレジスト膜で保護すると共に前記ソルダレジスト膜から露出された前記ＣＯＦ接続のためのリード領域にＳｎ、Ｎｉ、Ａｕ等のめっきを施したＴＡＢテープキャリアにおいて、
前記銅箔として前記テープ基材と反対側の面における最大あらさが２．０μｍ以上８μｍ以下に制御された銅箔を用いてなることを特徴とするテープキャリア。One side of the tape substrate made of an insulating resin film bonded to a copper foil, a wiring pattern including a lead for COF connection is formed by photo-etching the copper foil, the COF connections on the wiring pattern in TAB tape carriers facilities Sn, Ni, a plating of Au or the like to lead region for the exposed the COF connected from the solder resist film with a region excluding the lead for protection in Seo Rudarejisuto film,
A tape carrier comprising a copper foil whose maximum roughness on the surface opposite to the tape base material is controlled to 2.0 μm or more and 8 μm or less as the copper foil . 前記テープ基材がポリイミド樹脂フィルムから成ることを特徴とする請求項１に記載のテープキャリア。  The tape carrier according to claim 1, wherein the tape base material is made of a polyimide resin film. 前記銅箔が２〜１８μｍ厚さの電解あるいは圧延箔から成ることを特徴とする請求項１又は２に記載のテープキャリア。  The tape carrier according to claim 1 or 2, wherein the copper foil is made of electrolytic or rolled foil having a thickness of 2 to 18 µm. 前記配線パターン上に無電解めっきまたは電気めっきが施されていることを特徴とする請求項１〜３のいずれかに記載のテープキャリア。  The tape carrier according to any one of claims 1 to 3, wherein electroless plating or electroplating is performed on the wiring pattern. 請求項１〜４のいずれかに記載のテープキャリアを用い、該テープキャリアに半導体素子を搭載し、半導体素子の外部引きだし用電極上に形成された突起型電極に前記テープキャリアのＣＯＦ接続のためのリードを加熱ボンディングツールで熱圧着させたことを特徴とする半導体装置。A tape carrier according to any one of claims 1 to 4 , wherein a semiconductor element is mounted on the tape carrier, and the projecting electrode formed on the external lead electrode of the semiconductor element is connected to the tape carrier by COF. A semiconductor device characterized in that the lead is thermocompression bonded with a heat bonding tool.
JP2001009888A 2001-01-18 2001-01-18 Tape carrier and semiconductor device using the same Expired - Fee Related JP4069588B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001009888A JP4069588B2 (en) 2001-01-18 2001-01-18 Tape carrier and semiconductor device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001009888A JP4069588B2 (en) 2001-01-18 2001-01-18 Tape carrier and semiconductor device using the same

Publications (2)

Publication Number Publication Date
JP2002217246A JP2002217246A (en) 2002-08-02
JP4069588B2 true JP4069588B2 (en) 2008-04-02

Family

ID=18877300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001009888A Expired - Fee Related JP4069588B2 (en) 2001-01-18 2001-01-18 Tape carrier and semiconductor device using the same

Country Status (1)

Country Link
JP (1) JP4069588B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9674955B2 (en) * 2011-11-09 2017-06-06 Lg Innotek Co., Ltd. Tape carrier package, method of manufacturing the same and chip package

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3536023B2 (en) * 2000-10-13 2004-06-07 シャープ株式会社 COF tape carrier and COF semiconductor device manufactured using the same
JP2009016716A (en) * 2007-07-09 2009-01-22 Hitachi Cable Ltd Tab tape carrier and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9674955B2 (en) * 2011-11-09 2017-06-06 Lg Innotek Co., Ltd. Tape carrier package, method of manufacturing the same and chip package

Also Published As

Publication number Publication date
JP2002217246A (en) 2002-08-02

Similar Documents

Publication Publication Date Title
JP3429734B2 (en) Wiring board, multilayer wiring board, circuit component package, and method of manufacturing wiring board
JPH10173003A (en) Semiconductor device and its manufacturing method, and film carrier tape and its manufacturing method
KR20120049144A (en) Wiring board with electronic component, and method of manufacturing the same
JP3269390B2 (en) Semiconductor device
JP4069588B2 (en) Tape carrier and semiconductor device using the same
JP3897278B2 (en) Manufacturing method of flexible wiring board
JP2001217513A (en) Circuit board
JP3350454B2 (en) Semiconductor integrated circuit device, method of manufacturing the same, and manufacturing apparatus
JP2001127425A (en) Wiring board and bonding method thereof, mounting and bonding method of mounting component, electronic component, circuit board and electronic apparatus
JP2000307055A (en) Semiconductor device, its manufacture, circuit substrate, and electronics
JP2002270652A (en) Tape carrier and semiconductor device using the same
JP3547270B2 (en) Mounting structure and method of manufacturing the same
JP2000013029A (en) High density wiring board, its manufacture and electronic device using the same
JP2001053194A (en) Double layer wiring tab tape and manufacturing method thereof
JP2001127117A (en) Method for manufacturing tab tape
JP2705297B2 (en) High strength TAB tape carrier
JP4031899B2 (en) Manufacturing method of film carrier tape for mounting electronic components
JP3888210B2 (en) Film carrier manufacturing method
JP2004335602A (en) Printed wiring board
JPH05206143A (en) Composite film, and formation of transfer bump by use thereof
JP2002299387A (en) Tape carrier for semiconductor device and its manufacturing method
JPH1117300A (en) Wiring board and circuit part mounting body and electronic part package and manufacture of wiring board and manufacture of package of electronic part
JPH11135173A (en) Thickness direction conductive sheet and manufacture thereof
JP3247888B2 (en) Electronic component package and method for manufacturing electronic component package
JP3257931B2 (en) Semiconductor package, method of manufacturing the same, and semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060317

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20060317

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20060317

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070928

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071002

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071130

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071225

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080107

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110125

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees