JPH10163261A - Manufacture of electronic component mounting wiring board - Google Patents

Manufacture of electronic component mounting wiring board

Info

Publication number
JPH10163261A
JPH10163261A JP8319258A JP31925896A JPH10163261A JP H10163261 A JPH10163261 A JP H10163261A JP 8319258 A JP8319258 A JP 8319258A JP 31925896 A JP31925896 A JP 31925896A JP H10163261 A JPH10163261 A JP H10163261A
Authority
JP
Japan
Prior art keywords
solder layer
electronic component
solder
terminal electrode
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8319258A
Other languages
Japanese (ja)
Inventor
Shunji Murano
俊次 村野
Shinjiro Oka
真二郎 岡
Yasuhiko Shigeta
泰彦 重田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP8319258A priority Critical patent/JPH10163261A/en
Publication of JPH10163261A publication Critical patent/JPH10163261A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

Abstract

PROBLEM TO BE SOLVED: To prevent the welded parts between a wiring board and an electronic component from being broken easily, even if a thermal stress, etc., are applied between both. SOLUTION: Along with attaching solder layers 3 to parts of the top surface of each of a plurality of wiring conductors 2 formed on an insulating substrate 1, an isolation band 4 having a thickness appraximately equal to the sum of the thicknesses of a wiring conductor 2 and a solder layer 3 is provide between each wiring conductor and the next on the top surface of the above-mentioned insulating board. Next, an electronic component 7 with a plurality of terminal electrodes 7a having areas smaller than the solder layers 3 is put on the insulating board 1, so that each terminal electrode 7a may touch a part of a solder layer 3. Next, the exposed region of the solder layer 3 brought into contact with the terminal electrode 7a of the electronic component 7 is covered with flow-out preventing material 8 having a thermal decomposition temperature higher than the melting temperature of the solder layer 3. And the solder layers 3 are heated and melted, and the terminal electrodes 7a of the electronic component 7 are joined with solder to the wiring conductors 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、発光ダイオードア
レイやLSI等の電子部品をフリップチップ方式にて搭
載した電子部品搭載用配線基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a wiring board for mounting electronic components on which electronic components such as a light emitting diode array and an LSI are mounted by a flip chip method.

【0002】[0002]

【従来技術及びその問題点】従来、発光ダイオードアレ
イやLSI等の電子部品が搭載される配線基板は、例え
ば図5に示す如く、アルミナセラミックスやガラス等か
ら成る絶縁基板11の上面にAgやCu等から成る複数
個の配線導体12を所定厚み、所定パターンに被着・形
成するとともに、これら配線導体12の一部上面に所定
厚みの半田層13をスクリーン印刷等によって被着させ
た構造を有しており、かかる配線基板の半田層13に電
子部品14の端子電極15を当接させた状態で前記半田
層13を高温で加熱・溶融させ、電子部品14の端子電
極15を配線導体12に半田接合させることによって電
子部品14が配線基板上に搭載されることとなる。
2. Description of the Related Art Conventionally, as shown in FIG. 5, a wiring board on which electronic components such as a light emitting diode array and an LSI are mounted is formed on an upper surface of an insulating substrate 11 made of alumina ceramics or glass. And a plurality of wiring conductors 12 each having a predetermined thickness and a predetermined pattern are attached and formed, and a solder layer 13 having a predetermined thickness is attached on a partial upper surface of the wiring conductors 12 by screen printing or the like. The solder layer 13 is heated and melted at a high temperature in a state where the terminal electrode 15 of the electronic component 14 is in contact with the solder layer 13 of the wiring board, and the terminal electrode 15 of the electronic component 14 is connected to the wiring conductor 12. The electronic component 14 is mounted on the wiring board by soldering.

【0003】しかしながら、この従来の配線基板におい
ては、配線導体12の配列密度が高密度(例えば、10
0μm以下のピッチ)である場合、前述の如く半田層1
3を加熱・溶融させた際に該溶融した半田13がその表
面張力や電子部品14の重み等によって横に広がり、隣
接する半田層同士が短絡を起こす欠点を有していた。そ
こで本願発明者等は上記欠点を解消するために、絶縁基
板11上の各配線導体12間に配線導体12及び半田層
13の厚みの総和と略等しい厚みをもった分離帯を設
け、この分離帯によって溶融半田13が横に広がるのを
防止することを提案した(特願平8−166243号参
照)。
However, in this conventional wiring board, the arrangement density of the wiring conductors 12 is high (for example, 10
0 μm or less), the solder layer 1
When the solder 3 was heated and melted, the melted solder 13 spread laterally due to its surface tension, the weight of the electronic component 14, and the like. In order to solve the above-mentioned drawbacks, the inventors of the present invention provided a separator between each of the wiring conductors 12 on the insulating substrate 11 and having a thickness substantially equal to the total thickness of the wiring conductors 12 and the solder layers 13. It has been proposed to prevent the molten solder 13 from being spread laterally by the band (see Japanese Patent Application No. 8-166243).

【0004】ところが、近年、発光ダイオードアレイや
LSI等の電子部品はコウトダウンの要求に応えるべく
徐々に小型化される傾向にあり、これに伴って電子部品
の端子電極や半田層の面積も極めて小さくなってきてい
る。この場合、電子部品の端子電極は極めて少量の半田
によって配線導体に接合されることから、半田接合部に
十分な機械的強度を付与することができず、配線基板及
び電子部品間に熱応力等が印加されると、これによって
半田接合部が容易に破損してしまうという欠点が誘発さ
れる。
However, in recent years, electronic components such as light-emitting diode arrays and LSIs have tended to be gradually reduced in size in order to respond to the demand for downsizing, and accordingly, the area of terminal electrodes and solder layers of the electronic components has become extremely small. It has become to. In this case, since the terminal electrodes of the electronic component are joined to the wiring conductor by a very small amount of solder, sufficient mechanical strength cannot be given to the solder joint, and thermal stress or the like between the wiring board and the electronic component cannot be provided. Is applied, this leads to the disadvantage that the solder joints are easily broken.

【0005】[0005]

【課題を解決するための手段】本発明は上記欠点に鑑み
案出されたもので、本発明の電子部品搭載用配線基板の
製造方法は、絶縁基板上に形成された複数個の配線導体
の各々の一部上面に半田層を被着させるとともに前記絶
縁基板上面の各配線導体間に配線導体及び半田層の厚み
の総和に対し略等しい厚みを有する分離帯を配設する工
程と、前記半田層よりも小さな面積の端子電極が複数個
形成された電子部品を絶縁基板上に、各端子電極が前記
半田層の一部に当接するようにして載置させる工程と、
前記電子部品の端子電極が当接された半田層の露出領域
を、該半田層の溶融温度よりも高い熱分解温度を有した
流出防止材によって被覆する工程と、前記半田層を加熱
・溶融させ、配線導体に電子部品の端子電極を半田接合
させる工程と、を含むことを特徴とする。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and a method of manufacturing a wiring board for mounting electronic components according to the present invention is directed to a method for manufacturing a plurality of wiring conductors formed on an insulating substrate. Disposing a solder layer on each partial upper surface and disposing a separator between the wiring conductors on the upper surface of the insulating substrate and having a thickness substantially equal to the total thickness of the wiring conductor and the solder layer; A step of placing an electronic component on which a plurality of terminal electrodes having an area smaller than the layer is formed on an insulating substrate so that each terminal electrode is in contact with a part of the solder layer,
Covering the exposed area of the solder layer with which the terminal electrode of the electronic component is in contact with an outflow prevention material having a higher thermal decomposition temperature than the melting temperature of the solder layer; and heating and melting the solder layer. And bonding a terminal electrode of the electronic component to the wiring conductor by soldering.

【0006】また本発明の電子部品搭載用配線基板の製
造方法は、絶縁基板上に形成された複数個の配線導体の
各々の一部上面に半田層を被着させるとともに、該半田
層の上面及び配線導体間に位置する絶縁基板上面に、半
田層の溶融温度よりも高い熱分解温度を有し、かつ各半
田層の一部を露出させるための窓部を有する流出防止膜
を被着させる工程と、前記流出防止膜の窓部と略等しい
面積の複数個の端子電極を有した電子部品を絶縁基板上
に、各端子電極を前記流出防止膜の窓部内の半田層に当
接するようにして載置させる工程と、前記半田層を加熱
・溶融させ、配線導体に電子部品の端子電極を半田接合
させる工程と、を含むことを特徴とする。
According to the method of manufacturing a wiring board for mounting electronic components of the present invention, a solder layer is applied to a partial upper surface of each of a plurality of wiring conductors formed on an insulating substrate, and the upper surface of the solder layer is formed. And applying an outflow prevention film having a thermal decomposition temperature higher than the melting temperature of the solder layer and having a window for exposing a part of each solder layer on the upper surface of the insulating substrate located between the wiring conductors. The electronic component having a plurality of terminal electrodes having substantially the same area as the window portion of the outflow prevention film is placed on an insulating substrate, and each terminal electrode is brought into contact with a solder layer in the window portion of the outflow prevention film. And heating and melting the solder layer, and soldering the terminal electrode of the electronic component to the wiring conductor.

【0007】[0007]

【発明の実施の形態】以下、本発明を添付図面に基づい
て詳細に説明する。 (第1形態)まず本発明の製法の第1形態について説明
する。図1は本発明の製法の第1形態によって製作した
電子部品搭載用配線基板の部分平面図、図2(a)は図
1のX−X線断面図、図2(b)は図1のY−Y線断面
図であり、1は絶縁基板、2は配線導体、3は半田層、
4は分離帯、7は電子部品、7aは端子電極、8は流出
防止材である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. (First Embodiment) First, a first embodiment of the manufacturing method of the present invention will be described. FIG. 1 is a partial plan view of a wiring board for mounting electronic components manufactured according to a first embodiment of the manufacturing method of the present invention, FIG. 2 (a) is a cross-sectional view taken along line XX of FIG. 1, and FIG. FIG. 2 is a cross-sectional view taken along the line YY, where 1 is an insulating substrate, 2 is a wiring conductor, 3 is a solder layer,
Reference numeral 4 denotes a separator, 7 denotes an electronic component, 7a denotes a terminal electrode, and 8 denotes an outflow preventing material.

【0008】前記絶縁基板1は、例えば、厚み1mm程
度のホウケイ酸ガラス、ソーダライムガラス、アルミナ
セラミックス等によって形成されており、その上面で複
数個の配線導体2や半田層3,分離帯4等を支持するよ
うになっている。
The insulating substrate 1 is made of, for example, borosilicate glass, soda lime glass, alumina ceramics or the like having a thickness of about 1 mm, and has a plurality of wiring conductors 2, a solder layer 3, a separation band 4, etc. on its upper surface. Has come to support.

【0009】また前記絶縁基板1の上面に被着されてい
る複数個の配線導体2は、隣接する配線導体2との間に
所定の間隔を隔てて高密度(例えば、100μm以下の
ピッチ)に配列されており、例えばAgやCu,Au等
の金属によって3〜20μmの厚みをもって被着・形成
される。
The plurality of wiring conductors 2 attached on the upper surface of the insulating substrate 1 are arranged at a high density (for example, at a pitch of 100 μm or less) at a predetermined interval from adjacent wiring conductors 2. They are arranged and formed with a thickness of 3 to 20 μm using a metal such as Ag, Cu, or Au.

【0010】前記配線導体2は、その一部上面に被着さ
れる半田層3を介して電子部品7の端子電極7aに電気
的に接続され、これによって電子部品7に駆動電力や種
々の電気信号等を供給するようになっている。
The wiring conductor 2 is electrically connected to a terminal electrode 7a of an electronic component 7 via a solder layer 3 attached to a part of the upper surface of the wiring conductor 2, thereby providing the electronic component 7 with driving power and various electric power. It supplies signals and the like.

【0011】そして前記配線導体2の一部上面に被着さ
れている半田層3は、後述する電子部品7の端子電極7
aを配線導体2に半田接合させるためのものであり、複
数個の配線導体2の各一端に略一定の厚み(5〜30μ
m)をもって被着される。
The solder layer 3 applied to a part of the upper surface of the wiring conductor 2 is connected to a terminal electrode 7 of an electronic component 7 described later.
a to be solder-bonded to the wiring conductor 2, and one end of each of the plurality of wiring conductors 2 has a substantially constant thickness (5 to 30 μm).
m).

【0012】また前記絶縁基板上面の各配線導体2間に
は、配線導体2及び半田層3の厚みの総和に対し略等し
い厚みを有する分離帯4が配設されている。
A separation band 4 having a thickness substantially equal to the total thickness of the wiring conductor 2 and the solder layer 3 is provided between the wiring conductors 2 on the upper surface of the insulating substrate.

【0013】前記分離帯4は半田ぬれ性の悪い電気絶縁
材、例えば、ガラス、熱可塑性樹脂等から成り、隣接す
る半田層3間に配線導体2及び半田層3の厚みの総和と
略等しい高さの壁をつくることから、後述する電子部品
7を絶縁基板1上に搭載するにあたって半田層3を加熱
・溶融(半田リフロー)させる際、該溶融した半田3が
その表面張力や電子部品7の重み等によって隣接する半
田層3と短絡を起こそうとするのを分離帯4によって有
効に防止することができる。
The separator 4 is made of an electrical insulating material having poor solder wettability, for example, glass, thermoplastic resin, etc., and has a height substantially equal to the sum of the thicknesses of the wiring conductor 2 and the solder layer 3 between the adjacent solder layers 3. When the solder layer 3 is heated and melted (solder reflow) when mounting an electronic component 7 to be described later on the insulating substrate 1, the molten solder 3 has a surface tension and a surface tension of the electronic component 7. The separation band 4 can effectively prevent an attempt to cause a short circuit with the adjacent solder layer 3 due to weight or the like.

【0014】そして前記絶縁基板1の上面所定位置に
は、発光ダイオードアレイやLSI等の電子部品7がフ
リップチップ方式にて搭載されている。
At a predetermined position on the upper surface of the insulating substrate 1, an electronic component 7 such as a light emitting diode array or an LSI is mounted in a flip-chip manner.

【0015】前記電子部品7は、その下面に前記半田層
3よりも小さな面積の端子電極7aが複数個形成されて
おり、これらの端子電極7aの下面を半田層3の上面の
一部に被着させておくことにより電子部品7の端子電極
7aを半田層3を介して配線導体2に電気的に接続させ
ている。
On the lower surface of the electronic component 7, a plurality of terminal electrodes 7a having an area smaller than that of the solder layer 3 are formed, and the lower surfaces of these terminal electrodes 7a are partially covered on the upper surface of the solder layer 3. The terminal electrode 7a of the electronic component 7 is electrically connected to the wiring conductor 2 via the solder layer 3 by being attached.

【0016】尚、前述のように電子部品7の端子電極7
aの面積を半田層3に比し小さくなしておくのは、端子
電極7aを配線導体2に対して強固に半田接合させるの
に十分な半田の量を確保するためであり、これによって
絶縁基板1と電子部品7との間に熱応力等が印加された
際に半田接合部が破損するのを有効に防止することがで
きる。
As described above, the terminal electrode 7 of the electronic component 7
The reason why the area of “a” is made smaller than that of the solder layer 3 is to secure a sufficient amount of solder for firmly joining the terminal electrode 7 a to the wiring conductor 2 by soldering. Damage to the solder joints when thermal stress or the like is applied between the electronic component 1 and the electronic component 7 can be effectively prevented.

【0017】また更に前記端子電極7aが当接されてい
る半田層3の上面には、該当接部を除く領域に流出防止
材8が被着されている。
Further, on the upper surface of the solder layer 3 with which the terminal electrode 7a is in contact, an outflow preventing material 8 is applied in a region other than the contact portion.

【0018】前記流出防止材8は、電子部品7を絶縁基
板1上に搭載するにあたって半田層3を加熱・溶融(半
田リフロー)させる際、該溶融した半田3が分離帯4等
で囲まれる空間から流出しないようにするための蓋とし
ての作用を為し、半田層3の溶融温度よりも高い熱分解
温度を有した電気絶縁材料、例えば樹脂やワックス,ゴ
ム等によって形成される。
When the solder layer 3 is heated and melted (solder reflow) when the electronic component 7 is mounted on the insulating substrate 1, the outflow preventing material 8 surrounds the melted solder 3 by the separation band 4 or the like. It is formed of an electrically insulating material having a thermal decomposition temperature higher than the melting temperature of the solder layer 3, for example, resin, wax, rubber, or the like, which acts as a lid to prevent the solder layer from flowing out.

【0019】次に上述した電子部品搭載用配線基板の製
造方法について図3を用いて説明する。 (1)まず、図3(a)に示すように、絶縁基板1上に
形成された複数個の配線導体2の各々の一部上面に半田
層3を被着させるとともに前記絶縁基板1上面の各配線
導体2間に配線導体2及び半田層3の厚みの総和に対し
略等しい厚みを有する分離帯4を配設する。
Next, a method of manufacturing the above-described wiring board for mounting electronic components will be described with reference to FIG. (1) First, as shown in FIG. 3A, a solder layer 3 is applied to a partial upper surface of each of a plurality of wiring conductors 2 formed on an insulating substrate 1 and an upper surface of the insulating substrate 1 is formed. A separator 4 having a thickness substantially equal to the total thickness of the wiring conductor 2 and the solder layer 3 is provided between the wiring conductors 2.

【0020】前記配線導体2は、例えば、銀粉末に適当
な有機溶媒、有機溶剤等を添加混合して得た銀ペースト
を絶縁基板1の上面に従来周知のスクリーン印刷等を採
用することによって所定厚み(3〜20μm)、所定パ
ターンに印刷・塗布し、しかる後、これを約580℃の
温度で焼き付けることによって絶縁基板1上に被着・形
成される。
The wiring conductor 2 is formed, for example, by applying a conventionally known screen printing or the like to the upper surface of the insulating substrate 1 by using a silver paste obtained by adding and mixing an appropriate organic solvent, an organic solvent and the like to silver powder. A predetermined pattern having a thickness (3 to 20 μm) and a predetermined pattern are printed and applied. Thereafter, the resultant is baked at a temperature of about 580 ° C. to be formed on the insulating substrate 1.

【0021】また前記分離帯4は、上述のようにして配
線導体2を形成した後、従来周知の厚膜手法、フォトリ
ソグラフィー技術(リフトオフ法)等を採用することに
よって所定厚み、所定パターンに被着・形成される。具
体的には、まず絶縁基板1の上面所定領域に液状に成し
た光硬化型樹脂の前駆体をスクリーン印刷法、スピンコ
ート法等によって所定の厚みに塗布し、次に前記前駆体
を分離帯4の反転パターンに応じて露光、現像し、しか
る後、絶縁基板上面の電子部品7が実装される領域にわ
たってガラスペーストを塗布、焼成し、最後に前記光硬
化させた樹脂をその上に被着させたガラスと共に剥離さ
せることによってガラスから成る分離帯4が所定のパタ
ーンで被着・形成される。この場合、前記分離帯4は熱
伝導率の比較的低いガラスにより形成されているため、
後述する半田リフローの際に外部より印加される熱は分
離帯4中で良好に蓄積されることとなり、半田リフロー
を短時間で効率良く行うことができる。
After forming the wiring conductor 2 as described above, the separation band 4 is covered with a predetermined thickness and a predetermined pattern by employing a conventionally known thick film technique, a photolithography technique (lift-off method) or the like. Weared and formed. Specifically, first, a liquid-cured resin precursor formed in a liquid state is applied to a predetermined region on the upper surface of the insulating substrate 1 to a predetermined thickness by a screen printing method, a spin coating method, or the like. Exposure and development are performed in accordance with the reverse pattern of No. 4, and thereafter, a glass paste is applied and baked over the region on the upper surface of the insulating substrate on which the electronic component 7 is mounted, and finally the photocured resin is deposited thereon. Separation band 4 made of glass is adhered and formed in a predetermined pattern by peeling off the glass together with the glass. In this case, since the separation zone 4 is formed of glass having a relatively low thermal conductivity,
The heat applied from the outside during the solder reflow described later is well accumulated in the separation zone 4, and the solder reflow can be efficiently performed in a short time.

【0022】そして前記半田層3は、上述のようにして
分離帯4を形成した後、従来周知のディッピング法等を
採用することによって極めて簡単に形成することができ
る。即ち、上面に配線導体2及び分離帯4が形成されて
いる絶縁基板1をそのまま半田浴の中に浸漬することに
よって配線導体2の表面に半田が選択的に付着し、これ
によって半田層3が形成されることとなる。尚、このよ
うなディッピング法によって半田層3を形成する場合
は、半田を付着させたくない領域に予めソルダーレジス
ト層5を被着させておかなければならない。
The above-mentioned solder layer 3 can be formed very simply by forming a separation band 4 as described above and then employing a conventionally well-known dipping method or the like. That is, the solder is selectively adhered to the surface of the wiring conductor 2 by immersing the insulating substrate 1 on which the wiring conductor 2 and the separation band 4 are formed on the upper surface as it is in a solder bath. Will be formed. When the solder layer 3 is formed by such a dipping method, the solder resist layer 5 must be previously applied to a region where solder is not to be attached.

【0023】(2)次に図3(b)に示すように、前記
半田層3よりも小さな面積の端子電極7aが複数個形成
された電子部品7を絶縁基板1上に、各端子電極7aが
前記半田層3の一部に当接するようにして載置させる。
(2) Next, as shown in FIG. 3B, an electronic component 7 having a plurality of terminal electrodes 7a having an area smaller than that of the solder layer 3 is placed on the insulating substrate 1 and each terminal electrode 7a Is placed in contact with a part of the solder layer 3.

【0024】前記電子部品7の端子電極7aは、例えば
半田層3の面積が7.0 ×10-3mm2である場合、3.2 ×1
0-3mm2 の面積で形成されており、このように半田層
3を端子電極7aよりも大きくなしておくことにより、
後述する半田リフローの際に端子電極7aを配線導体2
に対して強固に半田接合させるのに十分な半田の量を確
保することができる。
For example, when the area of the solder layer 3 is 7.0 × 10 −3 mm 2 , the terminal electrode 7a of the electronic component 7 is 3.2 × 1
0 -3 mm 2 , and by making the solder layer 3 larger than the terminal electrode 7a,
The terminal electrode 7a is connected to the wiring conductor 2 at the time of solder reflow described later.
In this case, it is possible to secure a sufficient amount of solder for making a strong solder joint.

【0025】(3)続いて図3(c)に示すように、前
記電子部品7の端子電極7aが当接された半田層3の露
出領域を、該半田層3の溶融温度よりも高い熱分解温度
を有した流出防止材8によって被覆する。
(3) Subsequently, as shown in FIG. 3 (c), the exposed region of the solder layer 3 where the terminal electrode 7a of the electronic component 7 is in contact is heated to a temperature higher than the melting temperature of the solder layer 3. It is covered with an outflow prevention material 8 having a decomposition temperature.

【0026】前記流出防止材8は、半田層3の溶融温度
よりも高い熱分解温度を有した電気絶縁材料、例えば半
田層3の溶融温度が180℃である場合、これよりも熱
分解温度の高いエポキシ樹脂やポリイミド樹脂,アクリ
ル樹脂等の種々の樹脂材、カルナウバワックスやモンタ
ンワックス,カンデリラワックス等の種々のワックス
材、ニトリルゴム,シリコンゴム等のゴム材等から成
り、例えばエポキシ系の光硬化型樹脂を用いる場合、光
硬化型樹脂の前駆体をディスペンサー等を用いて半田層
3が露出する領域に100〜300μm程度の厚みをも
って帯状に塗布するとともに、該前駆体にUVランプ等
を用いて光を照射させ、これを光硬化させることによっ
て形成される。
When the melting temperature of the solder layer 3 is 180.degree. C., for example, when the melting temperature of the solder layer 3 is 180.degree. It is made of various resin materials such as high epoxy resin, polyimide resin, and acrylic resin, various wax materials such as carnauba wax, montan wax, and candelilla wax, and rubber materials such as nitrile rubber and silicone rubber. When using a photocurable resin, a precursor of the photocurable resin is applied in a band shape with a thickness of about 100 to 300 μm to a region where the solder layer 3 is exposed using a dispenser or the like, and a UV lamp or the like is applied to the precursor. It is formed by irradiating light and curing the light.

【0027】また前記流出防止材8として、前述の光硬
化型樹脂に代えて熱硬化型樹脂を用いる場合、必ずしも
この工程中で樹脂を硬化させておく必要はなく、後述す
る半田リフローの際に同時に熱硬化させても構わない。
When a thermosetting resin is used as the outflow preventing material 8 in place of the photocurable resin, it is not necessary to cure the resin in this step. It may be cured at the same time.

【0028】(4)そして最後に、前記半田層3を加熱
・溶融させ、配線導体2に電子部品7の端子電極7aを
半田接合させる。
(4) Finally, the solder layer 3 is heated and melted, and the terminal electrode 7a of the electronic component 7 is joined to the wiring conductor 2 by soldering.

【0029】前記半田層3は、流出防止材8の熱分解温
度よりも十分に低い温度(例えば200〜250℃)に
設定された炉の中で半田リフローされ、これによって絶
縁基板1上の配線導体2と電子部品7の端子電極7aと
がフリップチップ方式にて電気的・機械的に接続される
こととなる。
The solder layer 3 is subjected to solder reflow in a furnace set at a temperature sufficiently lower than the thermal decomposition temperature of the outflow prevention member 8 (for example, 200 to 250 ° C.). The conductor 2 and the terminal electrode 7a of the electronic component 7 are electrically and mechanically connected by the flip chip method.

【0030】この場合、半田層3の面積は電子部品7の
端子電極7aよりも十分に大きく形成されており、電子
部品7が極めて小型のものであっても、端子電極7aと
配線導体2とをより多くの半田3によって強固に接合す
ることができることから、絶縁基板1と電子部品7との
間に熱応力等が印加されても両者の半田接合部が容易に
破損することはなく、電子部品搭載用配線基板を長期間
にわたって良好に機能させることができる。
In this case, the area of the solder layer 3 is formed sufficiently larger than the terminal electrode 7a of the electronic component 7, and even if the electronic component 7 is extremely small, the area of the terminal electrode 7a and the wiring conductor 2 is small. Can be firmly joined by more solder 3, so that even if a thermal stress or the like is applied between the insulating substrate 1 and the electronic component 7, the solder joint between the two is not easily broken, and The component mounting wiring board can function well for a long period of time.

【0031】しかも、前記半田層3の露出領域は該半田
3の溶融温度よりも高い熱分解温度を有する流出防止材
8によって被覆されていることから、半田リフローの際
に溶融した半田3が表面張力等によって分離帯4等で囲
まれる領域から外部に流出しようとするのが流出防止材
8によって有効に防止され、電子部品7の搭載作業をよ
り確実に行うことができる。
Further, since the exposed area of the solder layer 3 is covered with the outflow preventing material 8 having a higher thermal decomposition temperature than the melting temperature of the solder 3, the molten solder 3 at the time of the solder reflow has An outflow preventing member 8 effectively prevents the outflow from the region surrounded by the separation band 4 or the like due to tension or the like, and the mounting operation of the electronic component 7 can be performed more reliably.

【0032】(第2形態)次に本発明の製法の第2形態
について説明する。図4(a)及び(b)は本発明の製
法の第2形態によって製作した電子部品搭載用配線基板
の断面図であり、9は流出防止膜、9aは窓部である。
尚、同図の分図(a)(b)は図2の分図(a)(b)
にそれぞれ対応させて示したもので、先に述べた第1形
態のものと同じ構成要素には同一の符号を付し、重複説
明を省略する。
(Second Embodiment) Next, a second embodiment of the manufacturing method of the present invention will be described. FIGS. 4A and 4B are cross-sectional views of an electronic component mounting wiring board manufactured by the second embodiment of the manufacturing method of the present invention, where 9 denotes a flow-out preventing film, and 9a denotes a window.
It should be noted that the division diagrams (a) and (b) of FIG.
The same reference numerals are given to the same components as those of the above-described first embodiment, and redundant description will be omitted.

【0033】図4に示す電子部品搭載用配線基板が第1
形態によって製作されたものと相違する点は、第1形態
で用いた分離帯4及び流出防止材8の代わりに、複数個
の窓部9aを有する流出防止膜9を用いている点であ
る。
The wiring board for mounting electronic components shown in FIG.
The difference from the one manufactured according to the embodiment is that the outflow prevention film 9 having a plurality of windows 9a is used instead of the separation band 4 and the outflow prevention material 8 used in the first embodiment.

【0034】前記流出防止膜9は半田層3の溶融温度よ
りも高い熱分解温度の電気絶縁性材料、例えばエポキシ
樹脂やアクリル樹脂等によって形成されており、個々の
窓部9aが各半田層3上に位置するようにして絶縁基板
1及び電子部品7間に介在させている。
The outflow prevention film 9 is formed of an electrically insulating material having a thermal decomposition temperature higher than the melting temperature of the solder layer 3, for example, an epoxy resin or an acrylic resin. It is interposed between the insulating substrate 1 and the electronic component 7 so as to be located above.

【0035】また前記電子部品7の端子電極7aは流出
防止膜9の窓部9aと略等しい面積で形成されており、
該端子電極7aを流出防止膜9の窓部9a内の半田層3
に被着させておくことによって電子部品7の端子電極7
aを半田層3を介して配線導体2に電気的に接続させて
いる。
The terminal electrode 7a of the electronic component 7 has an area substantially equal to the window 9a of the outflow prevention film 9.
The terminal electrode 7a is connected to the solder layer 3 in the window 9a of the outflow prevention film 9.
To the terminal electrodes 7 of the electronic component 7.
a is electrically connected to the wiring conductor 2 via the solder layer 3.

【0036】そして、上述の電子部品搭載用配線基板は
以下の手順(1)〜(4)に沿って製造される。 (1)まず複数個の配線導体2が形成された絶縁基板1
を準備し、該絶縁基板1上の配線導体2の各々の一部上
面に半田層3を被着させる。
Then, the above-mentioned wiring board for mounting electronic components is manufactured according to the following procedures (1) to (4). (1) First, an insulating substrate 1 on which a plurality of wiring conductors 2 are formed
Is prepared, and a solder layer 3 is applied to a partial upper surface of each of the wiring conductors 2 on the insulating substrate 1.

【0037】(2)次に前記半田層3の上面及び配線導
体2間に位置する絶縁基板1の上面に、前記半田層3の
溶融温度よりも高い熱分解温度を有し、かつ各半田層3
の一部を露出させるための窓部9aを有する流出防止膜
9を被着させる。
(2) Next, the upper surface of the solder layer 3 and the upper surface of the insulating substrate 1 located between the wiring conductors 2 have a thermal decomposition temperature higher than the melting temperature of the solder layer 3 and each solder layer 3
The outflow prevention film 9 having the window 9a for exposing a part of the film is applied.

【0038】前記流出防止膜9は、例えば光硬化型のエ
ポキシ樹脂から成る場合、該樹脂の前駆体を従来周知の
スクリーン印刷法等によって各半田層3上に窓部9aが
形成されるようにして所定の厚みをもって印刷・塗布
し、しかる後、前記前駆体にUVランプを用いて紫外線
を照射し、前駆体を光硬化させることによって形成され
る。このとき、流出防止膜9の膜厚は、電子部品7の端
子電極7aの厚みと略同じか、もしくはそれよりも薄く
形成しておかなければならない。
When the outflow prevention film 9 is made of, for example, a photo-curable epoxy resin, a window portion 9a is formed on each solder layer 3 by a conventionally known screen printing method or the like using a precursor of the resin. Then, the precursor is printed and applied with a predetermined thickness, and then the precursor is irradiated with ultraviolet rays using a UV lamp, and the precursor is photo-cured to form the precursor. At this time, the thickness of the outflow prevention film 9 must be substantially equal to or smaller than the thickness of the terminal electrode 7a of the electronic component 7.

【0039】(3)続いて前記流出防止膜9の窓部9a
と略等しい面積の複数個の端子電極7aを有した電子部
品7を絶縁基板1上に、各端子電極7aを前記流出防止
膜9の窓部9a内の半田層3に当接するようにして載置
させる。
(3) Subsequently, the window 9a of the outflow prevention film 9
An electronic component 7 having a plurality of terminal electrodes 7a having substantially the same area as the electronic component 7 is mounted on the insulating substrate 1 such that each terminal electrode 7a is in contact with the solder layer 3 in the window 9a of the outflow prevention film 9. Place.

【0040】(4)そして最後に前記半田層3を所定の
温度で加熱・溶融させ、配線導体2に電子部品7の端子
電極7を半田接合させることによって電子部品搭載用配
線基板が完成する。
(4) Finally, the solder layer 3 is heated and melted at a predetermined temperature, and the terminal electrodes 7 of the electronic component 7 are joined to the wiring conductor 2 by soldering, thereby completing the electronic component mounting wiring board.

【0041】このような第2形態の製法によっても、半
田層3の面積は電子部品7の端子電極7aよりも十分に
大きく形成されており、電子部品7が極めて小型のもの
であっても、端子電極7aと配線導体2とをより多くの
半田3によって強固に接合することができることから、
絶縁基板1と電子部品7との間に熱応力等が印加されて
も両者の半田接合部が容易に破損することはなく、電子
部品搭載用配線基板を長期間にわたって良好に機能させ
ることができる。
According to the manufacturing method of the second embodiment, the area of the solder layer 3 is formed sufficiently larger than the terminal electrode 7a of the electronic component 7, and even if the electronic component 7 is extremely small, Since the terminal electrode 7a and the wiring conductor 2 can be firmly joined by more solder 3,
Even when thermal stress or the like is applied between the insulating substrate 1 and the electronic component 7, the solder joints of the two are not easily broken, and the electronic component mounting wiring board can function well for a long period of time. .

【0042】また、前記半田層3の表面のうち端子電極
7aが当接される部位を除く全領域を半田層3の溶融温
度よりも高い熱分解温度を有する流出防止膜9によって
被覆するようにしたことから、半田リフローの際に溶融
した半田3が表面張力等によって横に広がったり、或い
は外部に流出したりすることはなく、電子部品7の搭載
作業を確実に行うことができる。
The entire area of the surface of the solder layer 3 except for the area where the terminal electrode 7a is in contact is covered with the outflow prevention film 9 having a thermal decomposition temperature higher than the melting temperature of the solder layer 3. Therefore, the solder 3 melted at the time of solder reflow does not spread laterally due to surface tension or the like or flows out, and the mounting work of the electronic component 7 can be reliably performed.

【0043】尚、本発明は上述した形態に限定されるも
のではなく、本発明の要旨を逸脱しない範囲において種
々の変更、改良等が可能である。
The present invention is not limited to the above-described embodiment, and various changes and improvements can be made without departing from the gist of the present invention.

【0044】[0044]

【発明の効果】本発明によれば、半田層の面積は電子部
品の端子電極よりも十分に大きく形成することができ、
電子部品が極めて小型のものであっても、その端子電極
と配線導体とをより多くの半田によって強固に接合する
ことが可能である。そのため、絶縁基板と電子部品との
間に熱応力等が印加されても両者の半田接合部が容易に
破損することはなく、電子部品搭載用配線基板を長期間
にわたって良好に機能させることができる。
According to the present invention, the area of the solder layer can be formed sufficiently larger than the terminal electrode of the electronic component.
Even if the electronic component is extremely small, the terminal electrode and the wiring conductor can be firmly joined with more solder. Therefore, even when thermal stress or the like is applied between the insulating substrate and the electronic component, the solder joints of the two are not easily damaged, and the electronic component mounting wiring board can function well for a long period of time. .

【0045】また本発明によれば、半田の溶融温度より
も高い熱分解温度を有する流出防止材もしくは流出防止
膜を用いて半田層の露出表面を覆うようにしたことか
ら、半田リフローの際に溶融した半田が外部に流出して
しまうことはなく、電子部品の実装作業を確実に行うこ
とができる。
According to the present invention, the exposed surface of the solder layer is covered with the outflow prevention material or the outflow prevention film having a thermal decomposition temperature higher than the melting temperature of the solder. The molten solder does not leak out, and the mounting operation of the electronic component can be performed reliably.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の製法の第1形態によって製作した電子
部品搭載用配線基板の部分平面図である。
FIG. 1 is a partial plan view of an electronic component mounting wiring board manufactured by a first embodiment of a manufacturing method of the present invention.

【図2】(a)は図1のX−X線断面図、(b)は図1
のY−Y線断面図である。
2A is a cross-sectional view taken along line XX of FIG. 1, and FIG.
5 is a sectional view taken along line YY of FIG.

【図3】(a)〜(c)は本発明の製法の一形態を示す
各工程毎の断面図である。
3 (a) to 3 (c) are cross-sectional views for respective steps showing one embodiment of the manufacturing method of the present invention.

【図4】(a)及び(b)は本発明の製法の第2形態に
よって製作した電子部品搭載用配線基板の断面図であ
る。
FIGS. 4A and 4B are cross-sectional views of an electronic component mounting wiring board manufactured by a second embodiment of the manufacturing method of the present invention.

【図5】従来の電子部品搭載用配線基板の部分断面図で
ある。
FIG. 5 is a partial sectional view of a conventional wiring board for mounting electronic components.

【符号の説明】[Explanation of symbols]

1・・・絶縁基板 2・・・配線導体 3・・・半田層 4・・・分離帯 7・・・電子部品 7a・・端子電極 8・・・流出防止材 9・・・流出防止膜 9a・・窓部 DESCRIPTION OF SYMBOLS 1 ... Insulating board 2 ... Wiring conductor 3 ... Solder layer 4 ... Separation band 7 ... Electronic component 7a ... Terminal electrode 8 ... Outflow prevention material 9 ... Outflow prevention film 9a ..Windows

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】絶縁基板上に形成された複数個の配線導体
の各々の一部上面に半田層を被着させるとともに前記絶
縁基板上面の各配線導体間に配線導体及び半田層の厚み
の総和に対し略等しい厚みを有する分離帯を配設する工
程と、 前記半田層よりも小さな面積の端子電極が複数個形成さ
れた電子部品を絶縁基板上に、各端子電極が前記半田層
の一部に当接するようにして載置させる工程と、 前記電子部品の端子電極が当接された半田層の露出領域
を、該半田層の溶融温度よりも高い熱分解温度を有した
流出防止材によって被覆する工程と、 前記半田層を加熱・溶融させ、配線導体に電子部品の端
子電極を半田接合させる工程と、を含むことを特徴とす
る電子部品搭載用配線基板の製造方法。
1. A solder layer is applied to a partial upper surface of each of a plurality of wiring conductors formed on an insulating substrate, and the total thickness of the wiring conductor and the solder layer is provided between the respective wiring conductors on the insulating substrate upper surface. Arranging a separation band having substantially the same thickness with respect to the electronic component on which a plurality of terminal electrodes having an area smaller than the solder layer are formed on an insulating substrate; each terminal electrode being part of the solder layer; And mounting the exposed part of the solder layer to which the terminal electrode of the electronic component is abutted with an outflow prevention material having a thermal decomposition temperature higher than the melting temperature of the solder layer. And a step of heating and melting the solder layer, and soldering a terminal electrode of the electronic component to the wiring conductor by soldering.
【請求項2】絶縁基板上に形成された複数個の配線導体
の各々の一部上面に半田層を被着させるとともに、該半
田層の上面及び配線導体間に位置する絶縁基板上面に、
半田層の溶融温度よりも高い熱分解温度を有し、かつ各
半田層の一部を露出させるための窓部を有する流出防止
膜を被着させる工程と、 前記流出防止膜の窓部と略等しい面積の複数個の端子電
極を有した電子部品を絶縁基板上に、各端子電極を前記
流出防止膜の窓部内の半田層に当接するようにして載置
させる工程と、 前記半田層を加熱・溶融させ、配線導体に電子部品の端
子電極を半田接合させる工程と、を含むことを特徴とす
る電子部品搭載用配線基板の製造方法。
2. A method according to claim 1, further comprising: applying a solder layer to a part of an upper surface of each of the plurality of wiring conductors formed on the insulating substrate;
Having a thermal decomposition temperature higher than the melting temperature of the solder layer, and applying an outflow prevention film having a window for exposing a part of each solder layer; and Placing an electronic component having a plurality of terminal electrodes of equal area on an insulating substrate such that each terminal electrode is in contact with a solder layer in a window of the outflow prevention film; and heating the solder layer. A method of melting and causing a terminal electrode of the electronic component to be solder-bonded to the wiring conductor.
JP8319258A 1996-11-29 1996-11-29 Manufacture of electronic component mounting wiring board Pending JPH10163261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8319258A JPH10163261A (en) 1996-11-29 1996-11-29 Manufacture of electronic component mounting wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8319258A JPH10163261A (en) 1996-11-29 1996-11-29 Manufacture of electronic component mounting wiring board

Publications (1)

Publication Number Publication Date
JPH10163261A true JPH10163261A (en) 1998-06-19

Family

ID=18108195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8319258A Pending JPH10163261A (en) 1996-11-29 1996-11-29 Manufacture of electronic component mounting wiring board

Country Status (1)

Country Link
JP (1) JPH10163261A (en)

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JP2003168829A (en) * 2001-09-19 2003-06-13 Matsushita Electric Works Ltd Light emitting device
KR100618941B1 (en) * 2005-11-08 2006-09-01 김성규 Transparent light emitting apparatus and manufacturing method thereof
CN103196107A (en) * 2012-01-05 2013-07-10 莫列斯公司 Holder, LED module, and LED system
KR101336699B1 (en) * 2012-03-06 2013-12-04 한국프린티드일렉트로닉스연구조합 Methods for manufacturing and smart packaging of Light Emitting Diode and using printed electronics technology
JP2015500561A (en) * 2011-11-18 2015-01-05 ルクスビュー テクノロジー コーポレイション Microdevice transfer head heater assembly and method for transferring microdevice
JP5899517B2 (en) * 2012-08-10 2016-04-06 パナソニックIpマネジメント株式会社 Manufacturing method and manufacturing system of component mounting board

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003168829A (en) * 2001-09-19 2003-06-13 Matsushita Electric Works Ltd Light emitting device
KR100618941B1 (en) * 2005-11-08 2006-09-01 김성규 Transparent light emitting apparatus and manufacturing method thereof
WO2007055455A1 (en) * 2005-11-08 2007-05-18 Sung Kyu Kim Transparent light emitting apparatus and manufacturing method thereof
JP2015500561A (en) * 2011-11-18 2015-01-05 ルクスビュー テクノロジー コーポレイション Microdevice transfer head heater assembly and method for transferring microdevice
CN103196107A (en) * 2012-01-05 2013-07-10 莫列斯公司 Holder, LED module, and LED system
JP2013157319A (en) * 2012-01-05 2013-08-15 Molex Inc Holder and led module using the same
US9170002B2 (en) 2012-01-05 2015-10-27 Molex, Llc Holder and LED module using same
CN105698130A (en) * 2012-01-05 2016-06-22 莫列斯有限公司 Holder
TWI579501B (en) * 2012-01-05 2017-04-21 Molex Inc Cylinders, LED modules and LED systems
KR101336699B1 (en) * 2012-03-06 2013-12-04 한국프린티드일렉트로닉스연구조합 Methods for manufacturing and smart packaging of Light Emitting Diode and using printed electronics technology
JP5899517B2 (en) * 2012-08-10 2016-04-06 パナソニックIpマネジメント株式会社 Manufacturing method and manufacturing system of component mounting board

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