JP4436588B2 - Semiconductor mounting module - Google Patents

Semiconductor mounting module Download PDF

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Publication number
JP4436588B2
JP4436588B2 JP2002085281A JP2002085281A JP4436588B2 JP 4436588 B2 JP4436588 B2 JP 4436588B2 JP 2002085281 A JP2002085281 A JP 2002085281A JP 2002085281 A JP2002085281 A JP 2002085281A JP 4436588 B2 JP4436588 B2 JP 4436588B2
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JP
Japan
Prior art keywords
mounting
semiconductor chip
electrode
mounting substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002085281A
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Japanese (ja)
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JP2003282812A (en
Inventor
優治 八木
隆文 柏木
雅昭 勝又
一人 西田
一路 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP2002085281A priority Critical patent/JP4436588B2/en
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Publication of JP4436588B2 publication Critical patent/JP4436588B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は各種電子機器に利用される半導体実装モジュールに関するものである。
【０００２】
【従来の技術】
近年、電子機器の小型化に伴いベアチップタイプの半導体チップを実装した半導体実装モジュールの開発が盛んに行われている。特に電子機器の小型化に有利なフェイスダウン実装が多く採用される中で、インライン実装が可能で短時間実装が可能なＡＣＦ（Ａnisotropic Ｃonductive Ｆilm）実装に代表される熱硬化性樹脂を用いた実装形態が注目されている。
【０００３】
図３（ａ），（ｂ）に一般的な熱硬化性樹脂による半導体チップを実装した半導体実装モジュールの要部平面図と要部断面図を示す。半導体実装モジュールの小型化のために、実装基板1の片面には、ベアチップタイプの半導体チップ２を実装し、他面にはセラミック電子部品、抵抗、コンデンサなどのチップ状電子部品３を実装する両面実装形態が採用され、実装基板１の片面には半導体チップ２を実装する電極４が、他面にはチップ状電子部品３を実装する電極５が設けられるが、これらの電極４，５は対向位置関係を配慮されずに設計される場合が殆どである。
【０００４】
また、上記電極４，５は実装基板１の基材の表面に金属板を貼付け、フォトリソ工法などでパターニングする方法や、基材の表面に金属膜を転写したり印刷してパターン形成した後焼成することによって固化する方法が用いられるため、基材の両面に電極４，５が突出して設けられた構成となっている。
【０００５】
熱硬化性樹脂を用いた半導体チップ２の実装基板１への実装は図４（ａ），（ｂ）に示すようにして行われている。すなわち、図４（ａ）に示すように実装基板１の電極４を形成した部分上に熱硬化性樹脂６を設け、実装面に複数のバンプ７を設けた半導体チップ２を位置合せし、続いて図４（ｂ）に示すように半導体チップ２の上面に加熱加圧ツール８を押し当て、半導体チップ２に圧力と熱を加えることにより半導体チップ２のバンプ７を電極４に押付け、熱硬化性樹脂６を硬化させて実装基板１への半導体チップ２の実装を行っている。この熱硬化性樹脂６の硬化時には半導体チップ２を実装基板１側に引付ける力が働き、半導体チップ２のバンプ７と実装基板１の電極４との接続の信頼性をより向上させている。
【０００６】
【発明が解決しようとする課題】
しかしながら、上記のような半導体チップ２の実装においては、実装基板１の剛性や電極４に対する電極５の形成位置が接続の信頼性に大きな影響を与えることになる。
【０００７】
すなわち、図５（ａ），（ｂ）に示すように実装基板１の半導体チップ２を実装する片面と対向する他面で半導体チップ２側から透過して見た場合に、バンプ７の位置する部分で電極５が存在する部分と存在しない部分があると、図５（ａ）に示すように加熱加圧ツール８で加圧すると電極５の存在しない部分が沈みこみ、図５（ｂ）に示すように実装後加熱加圧ツール８による加圧を解放すると実装基板１のスプリングバックにより実装基板１の電極５の存在する部分に対応する半導体チップ２のバンプ７が持ち上げられてバンプ７と電極４との間に隙間が形成され接続が破壊されてしまうという接続信頼性の劣化が発生してしまう問題があった。
【０００８】
本発明は以上のような従来の欠点を除去し、半導体チップの実装面と異なる面に形成する電極の位置に工夫を加えることにより接続の信頼性の高い半導体実装モジュールを提供することを目的とするものである。
【０００９】
【課題を解決するための手段】
上記課題を解決するために本発明は以下のように構成されている。
【００１０】
上記課題を解決するために本発明の請求項１に記載の発明は、少なくとも両面に半導体チップやチップ状電子部品を実装する電極を有する実装基板と、実装面の四辺の近くに実装基板の電極に接続される複数のバンプを設けた半導体チップとを備え、上記実装基板の半導体チップの実装面と異なる面に半導体チップの四隅近傍のバンプに対応する電極を設け、この電極の少なくとも１つ以上が前記半導体チップの二辺に沿う形状であるとともに、前記半導体チップの端面から前記バンプの配列方向に対して０．５ｍｍ以上の長さを持つ構成であり、この構成とすることにより半導体チップが加圧実装されても実装基板が大きく変形せず、接続の信頼性を著しく高めることができる。
【００１１】
さらに、半導体チップの実装時の実装基板の限界変形を規制し、実装基板の変形復帰時にバンプと電極との接続が破壊されるのを防止することができる。
【００１２】
請求項２に記載の発明は、半導体チップの四隅近傍のバンプに対応する電極として、チップ状電子部品を実装する電極を用いた構成であり、この構成とすることにより、実装基板として必要な電極で半導体チップの接続信頼性を確保することができる。
【００１５】
【発明の実施の形態】
以下、本発明の半導体実装モジュールの一実施の形態を図１、図２を用いて説明する。
【００１６】
まず、図１（ａ），（ｂ）、図２（ａ），（ｂ）に示す構成について説明する。図１（ａ），（ｂ）において、９はガラスエポキシ樹脂、紙−フェノール樹脂あるいはセラミックなどの絶縁物から構成される実装基板であり、この実装基板９の片面には少なくともベアチップタイプの半導体チップ１０の実装面の四辺の近くに設けた多数の金や半田からなるバンプ１１と接続される電極１２および配線パターン（図示せず）が設けられ、他面にはセラミック電子部品、抵抗、コイル、コンデンサなどのチップ状電子部品１３を実装する電極１４および配線パターン（図示せず）が設けられている。
【００１７】
この実装基板９の他面に設けられる電極１４は、実装基板９の片面に実装される半導体チップ１０の四隅近傍の複数のバンプ１１に対応する位置に形成されている。
【００１８】
この電極１４がパターン設計上形成されない場合は、半導体チップ１０の隅近傍に設けられた複数のバンプ１１に対応するように、ダミー電極１５を設ける。このダミー電極１５は半導体チップ１０の二辺のバンプ１１に対応するようにＬ字形とすることもできる。
【００１９】
また、チップ状電子部品１３を実装する電極１４としても方形状だけでなく、半導体チップ１０の二辺のバンプ１１に対応するようにＬ字形としてもよい。
【００２０】
そして、図２（ａ），（ｂ）に示すように半導体チップ１０の四隅近傍のバンプ１１に対応する電極１４やダミー電極１５は、実装基板９に実装する半導体チップ１０の端面からバンプ１１の配列方向に対して０．５ｍｍ以上の長さをもつ構成としてある。
【００２１】
これは、０．５ｍｍ以下の長さしかない電極１４やダミー電極１５であると、半導体チップ１０の実装時の圧力により実装基板９が大きく沈みこみ、すなわち大きく変形し、この圧力を解放すると実装基板９のスプリングバックによって強く圧接されていた電極１４やダミー電極１５と対応する位置のバンプ１１が電極１２から離れて接続が破壊されてしまうことになる。
【００２２】
しかし、電極１４やダミー電極１５の長さが０．５ｍｍ以上になると、その実装時の実装基板９の変形がかなり小さくなり、変形復元時にバンプ１１と電極１２との接続が破壊されるには至らない。
【００２３】
なお、図１、図２において、１６は実装基板９と半導体チップ１０との間に施された熱硬化性樹脂であり、半導体チップ１０の実装時に加熱加圧ツールを用いて実装し、熱硬化性樹脂１６の硬化時の引付力でより半導体チップ１０の実装強度、バンプ１１と電極１２の接続の安定化を図るために用いられるものである。
【００２４】
このような熱硬化性樹脂１６は必ずしも必要ではなく、半導体チップ１０を実装基板９の所定の位置に押付けて超音波を加えて実装する超音波実装や、半導体チップ１０を実装基板９の所定の位置に押付けてバンプ１１と電極１２とを加熱して接続するような実装形態を採用することもできる。
【００２５】
【発明の効果】
以上のように本発明の半導体実装モジュールは構成されるため、半導体チップの実装時に圧力がかけられても実装基板は殆ど変形しなくなり、したがって加圧を解放したときの実装基板のスプリングバックによって半導体チップのバンプと実装基板の電極との接続が破壊されることを阻止でき、信頼性の優れた半導体実装モジュールを提供することができる。
【図面の簡単な説明】
【図１】（ａ）本発明の半導体実装モジュールの一実施の形態の要部平面図
（ｂ）同要部の断面図
【図２】（ａ）同要部の拡大平面図
（ｂ）同要部の拡大断面図
【図３】（ａ）従来の半導体実装モジュールの要部平面図
（ｂ）同要部の断面図
【図４】（ａ），（ｂ）一般的な半導体チップの実装状態を説明する断面図
【図５】（ａ），（ｂ）従来の半導体チップの実装時の問題点を説明する断面図
【符号の説明】
９ 実装基板
１０半導体チップ
１１ バンプ
１２ 電極
１３ チップ状電子部品
１４ 電極
１５ ダミー電極
１６ 熱硬化性樹脂[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor mounting module used for various electronic devices.
[0002]
[Prior art]
In recent years, with the miniaturization of electronic devices, development of semiconductor mounting modules on which bare chip type semiconductor chips are mounted has been actively performed. In particular, face down mounting, which is advantageous for downsizing electronic devices, is often used. Mounting using thermosetting resin typified by ACF (Anisotropic Conductive Film) mounting that enables in-line mounting and short-time mounting. The form is drawing attention.
[0003]
FIGS. 3A and 3B are a plan view and a cross-sectional view of main parts of a semiconductor mounting module on which a semiconductor chip made of a general thermosetting resin is mounted. In order to reduce the size of the semiconductor mounting module, a mounting chip 1 is mounted on one side with a bare chip type semiconductor chip 2, and the other side is mounted with a chip-shaped electronic component 3 such as a ceramic electronic component, resistor or capacitor. The mounting form is adopted, and an electrode 4 for mounting the semiconductor chip 2 is provided on one side of the mounting substrate 1 and an electrode 5 for mounting the chip-shaped electronic component 3 is provided on the other side. In most cases, the design is made without considering the positional relationship.
[0004]
Further, the electrodes 4 and 5 are formed by attaching a metal plate to the surface of the base material of the mounting substrate 1 and patterning it by a photolithographic method or the like. Since the method of solidifying is used, the electrodes 4 and 5 are provided so as to protrude on both surfaces of the base material.
[0005]
Mounting of the semiconductor chip 2 using the thermosetting resin on the mounting substrate 1 is performed as shown in FIGS. That is, as shown in FIG. 4A, the thermosetting resin 6 is provided on the portion of the mounting substrate 1 where the electrodes 4 are formed, the semiconductor chip 2 provided with a plurality of bumps 7 on the mounting surface is aligned, and then As shown in FIG. 4B, the heating and pressing tool 8 is pressed against the upper surface of the semiconductor chip 2, and pressure and heat are applied to the semiconductor chip 2, thereby pressing the bumps 7 of the semiconductor chip 2 against the electrode 4 and thermosetting. The semiconductor chip 2 is mounted on the mounting substrate 1 by curing the functional resin 6. When the thermosetting resin 6 is cured, a force that attracts the semiconductor chip 2 toward the mounting substrate 1 works, and the reliability of the connection between the bump 7 of the semiconductor chip 2 and the electrode 4 of the mounting substrate 1 is further improved.
[0006]
[Problems to be solved by the invention]
However, in mounting the semiconductor chip 2 as described above, the rigidity of the mounting substrate 1 and the formation position of the electrode 5 with respect to the electrode 4 have a great influence on the connection reliability.
[0007]
That is, as shown in FIGS. 5A and 5B, the bumps 7 are located when viewed from the side of the semiconductor chip 2 on the other side of the mounting substrate 1 facing the side on which the semiconductor chip 2 is mounted. If there is a portion where the electrode 5 is present and a portion where the electrode 5 is not present, the portion where the electrode 5 does not exist sinks when pressed by the heating and pressing tool 8 as shown in FIG. As shown, when the pressure applied by the heating and pressing tool 8 is released after mounting, the bump 7 of the semiconductor chip 2 corresponding to the portion where the electrode 5 of the mounting substrate 1 exists is lifted by the spring back of the mounting substrate 1, and the bump 7 and the electrode There is a problem that a connection reliability is deteriorated such that a gap is formed between the four and the connection is broken.
[0008]
It is an object of the present invention to provide a semiconductor mounting module with high connection reliability by eliminating the above-described conventional drawbacks and devising the positions of electrodes formed on a surface different from the mounting surface of the semiconductor chip. To do.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is configured as follows.
[0010]
In order to solve the above-mentioned problems, the invention according to claim 1 of the present invention includes a mounting substrate having electrodes for mounting a semiconductor chip or a chip-like electronic component on at least both surfaces, and electrodes of the mounting substrate near the four sides of the mounting surface. A semiconductor chip provided with a plurality of bumps connected to the semiconductor chip, electrodes corresponding to the bumps near the four corners of the semiconductor chip are provided on a surface different from the mounting surface of the semiconductor chip of the mounting substrate, and at least one of the electrodes Is a shape along two sides of the semiconductor chip, and has a length of 0.5 mm or more from the end face of the semiconductor chip with respect to the arrangement direction of the bumps. Even if the pressure mounting is performed, the mounting substrate is not greatly deformed, and the connection reliability can be remarkably improved.
[0011]
Further , it is possible to restrict the limit deformation of the mounting substrate when the semiconductor chip is mounted, and to prevent the connection between the bump and the electrode from being broken when the deformation of the mounting substrate is restored.
[0012]
The invention according to claim 2 is a configuration in which an electrode for mounting a chip-like electronic component is used as an electrode corresponding to bumps near the four corners of the semiconductor chip, and by this configuration, an electrode necessary as a mounting substrate is obtained. Thus, the connection reliability of the semiconductor chip can be ensured.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of a semiconductor mounting module according to the present invention will be described below with reference to FIGS.
[0016]
First, the configuration shown in FIGS. 1A and 1B and FIGS. 2A and 2B will be described. 1A and 1B, reference numeral 9 denotes a mounting substrate made of an insulating material such as glass epoxy resin, paper-phenol resin, or ceramic. At least one bare chip type semiconductor chip is provided on one surface of the mounting substrate 9. 10 are provided with electrodes 12 and wiring patterns (not shown) connected to bumps 11 made of gold or solder provided near the four sides of the mounting surface, and ceramic electronic components, resistors, coils, An electrode 14 and a wiring pattern (not shown) for mounting a chip-shaped electronic component 13 such as a capacitor are provided.
[0017]
The electrodes 14 provided on the other surface of the mounting substrate 9 are formed at positions corresponding to the plurality of bumps 11 near the four corners of the semiconductor chip 10 mounted on one surface of the mounting substrate 9.
[0018]
When this electrode 14 is not formed due to pattern design, dummy electrodes 15 are provided so as to correspond to the plurality of bumps 11 provided near the corners of the semiconductor chip 10. The dummy electrode 15 may be L-shaped so as to correspond to the bumps 11 on the two sides of the semiconductor chip 10.
[0019]
Further, the electrode 14 on which the chip-shaped electronic component 13 is mounted is not limited to a square shape, and may be L-shaped so as to correspond to the bumps 11 on the two sides of the semiconductor chip 10.
[0020]
2A and 2B, the electrodes 14 and the dummy electrodes 15 corresponding to the bumps 11 near the four corners of the semiconductor chip 10 are formed on the bumps 11 from the end face of the semiconductor chip 10 mounted on the mounting substrate 9. The arrangement has a length of 0.5 mm or more with respect to the arrangement direction.
[0021]
In the case of the electrode 14 or the dummy electrode 15 having a length of only 0.5 mm or less, the mounting substrate 9 sinks greatly due to the pressure at the time of mounting the semiconductor chip 10, that is, greatly deforms. The bumps 11 at positions corresponding to the electrodes 14 and the dummy electrodes 15 that are strongly pressed by the spring back of the substrate 9 are separated from the electrodes 12 and the connection is broken.
[0022]
However, when the length of the electrode 14 or the dummy electrode 15 is 0.5 mm or more, the deformation of the mounting substrate 9 at the time of mounting becomes considerably small, and the connection between the bump 11 and the electrode 12 is broken when the deformation is restored. It does n’t come.
[0023]
1 and 2, reference numeral 16 denotes a thermosetting resin applied between the mounting substrate 9 and the semiconductor chip 10. When the semiconductor chip 10 is mounted, the thermosetting resin is mounted by using a heating and pressing tool, and thermosetting is performed. This is used to stabilize the mounting strength of the semiconductor chip 10 and the connection between the bumps 11 and the electrodes 12 with the attractive force at the time of curing of the conductive resin 16.
[0024]
Such a thermosetting resin 16 is not necessarily required. Ultrasonic mounting in which the semiconductor chip 10 is pressed against a predetermined position of the mounting substrate 9 and ultrasonic waves are applied, or the semiconductor chip 10 is mounted on the mounting substrate 9 in a predetermined manner. It is also possible to adopt a mounting form in which the bump 11 and the electrode 12 are heated and connected by being pressed to a position.
[0025]
【The invention's effect】
As described above, since the semiconductor mounting module of the present invention is configured, the mounting substrate is hardly deformed even when pressure is applied during mounting of the semiconductor chip. Therefore, the semiconductor is mounted by springback of the mounting substrate when the pressure is released. It is possible to prevent breakage of the connection between the bumps of the chip and the electrodes of the mounting substrate, and it is possible to provide a highly reliable semiconductor mounting module.
[Brief description of the drawings]
1A is a plan view of a main part of an embodiment of a semiconductor mounting module of the present invention; FIG. 2B is a cross-sectional view of the main part; FIG. 2A is an enlarged plan view of the main part; [FIG. 3] (a) Plan view of relevant part of conventional semiconductor mounting module (b) Cross-sectional view of relevant part [FIG. 4] (a), (b) Mounting of general semiconductor chip Cross-sectional view explaining the state [FIGS. 5] and (b) Cross-sectional views explaining problems in mounting a conventional semiconductor chip [Explanation of symbols]
9 Mounting substrate 10 Semiconductor chip 11 Bump 12 Electrode 13 Chip-shaped electronic component 14 Electrode 15 Dummy electrode 16 Thermosetting resin

Claims (2)

少なくとも両面に半導体チップやチップ状電子部品を実装する電極を有する実装基板と、実装面の四辺の近くに、実装基板の電極に接続される、複数のバンプを設けた半導体チップとを備え、上記実装基板の半導体チップの実装面と異なる面に半導体チップの四隅近傍のバンプに対応する電極を設けるとともに、前記半導体チップの四隅近傍のバンプに対応する電極が前記半導体チップの端面から前記バンプの配列方向に対して０．５ｍｍ以上の長さを持つ構成である半導体実装モジュールであって、
前記半導体チップの四隅近傍のバンプに対応する電極として、その少なくとも１つ以上を前記半導体チップの二辺に沿うＬ字形としたことを特徴とする半導体実装モジュール。A mounting substrate having an electrode for mounting a semiconductor chip or a chip-shaped electronic component on at least both sides, and a semiconductor chip provided with a plurality of bumps connected to the electrodes of the mounting substrate near the four sides of the mounting surface; bumps with Keru set the corresponding electrode to the vicinity of the four corners of the semiconductor chip in the semiconductor chip mounting surface of the mounting substrate with different surface electrodes corresponding to the bump of the four corners of the semiconductor chip of the bump from the end face of the semiconductor chip A semiconductor mounting module having a length of 0.5 mm or more with respect to the arrangement direction,
At least one or more electrodes corresponding to bumps near the four corners of the semiconductor chip are L-shaped along two sides of the semiconductor chip. 半導体チップの四隅近傍のバンプに対応する電極として、チップ状電子部品を実装する電極を用いた請求項１に記載の半導体実装モジュール。  The semiconductor mounting module according to claim 1, wherein an electrode for mounting a chip-like electronic component is used as an electrode corresponding to a bump near four corners of the semiconductor chip.
JP2002085281A 2002-03-26 2002-03-26 Semiconductor mounting module Expired - Fee Related JP4436588B2 (en)

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US6960830B2 (en) * 2002-10-31 2005-11-01 Rohm Co., Ltd. Semiconductor integrated circuit device with dummy bumps
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