WO2000021135A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
WO2000021135A1
WO2000021135A1 PCT/JP1998/004463 JP9804463W WO0021135A1 WO 2000021135 A1 WO2000021135 A1 WO 2000021135A1 JP 9804463 W JP9804463 W JP 9804463W WO 0021135 A1 WO0021135 A1 WO 0021135A1
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WO
WIPO (PCT)
Prior art keywords
chip
chips
insulating sheet
semiconductor device
wiring
Prior art date
Application number
PCT/JP1998/004463
Other languages
French (fr)
Japanese (ja)
Inventor
Junichi Arita
Kenji Ujiie
Shuji Eguchi
Haruo Akahoshi
Takuya Fukuda
Hideo Miura
Yasunori Narizuka
Naotaka Tanaka
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to AU92828/98A priority Critical patent/AU9282898A/en
Priority to PCT/JP1998/004463 priority patent/WO2000021135A1/en
Publication of WO2000021135A1 publication Critical patent/WO2000021135A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Definitions

  • the present invention relates to a semiconductor device and a manufacturing technology thereof, and more particularly to a technology effective when applied to a semiconductor device having a multi-chip module (Multi Chip Module; MCM) having a plurality of semiconductor chips mounted on a substrate.
  • MCM Multi Chip Module
  • the multi-chip module is a method to create a desired system by creating integrated circuits such as CPU, RAM, ROM, and ASIC on a chip-by-chip basis and mounting these chips on a wiring board. is there. To mount the chip on the board, mounting methods such as pin bonding, TAB, and flip chip are used.
  • manoret chip module ⁇ is described in, for example, "Iii, Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 12, No. 2, June 1998 (IEEE TR ANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 12, NO. 2, JUNE 1989) " See No. 920, etc.
  • An object of the present invention is to provide a technique for improving the mounting density of a multichip module.
  • the semiconductor device of the present invention has a multi-chip module configured by combining a plurality of chips on which integrated circuits having different operation power supply voltages are formed, and is provided above a first layer wiring for electrically connecting the chips.
  • a second layer wiring for supplying power to the chip is arranged, and the second layer wiring is divided for each power supply voltage so that different power supply voltages can be supplied to the plurality of chips.
  • the semiconductor device of the present invention has a multi-chip module configured by combining a plurality of chips including a CPU, and includes a first layer wiring for electrically connecting the chips, and A second-layer wiring for supplying power is arranged, and a pad for testing an operation of another chip is connected to the first-layer wiring connected to the CPU.
  • the method of manufacturing a semiconductor device according to the present invention includes the following steps.
  • the method for manufacturing a semiconductor device according to the present invention includes the following steps.
  • the method for manufacturing a semiconductor device according to the present invention includes the following steps.
  • the method for manufacturing a semiconductor device according to the present invention includes the following steps.
  • step (d) a reference position of the first and second chips with respect to a common coordinate of the plurality of chips, and a shift information between the positions of the first and second chips measured in the step (c). Forming a wiring between the first chip and the second chip by laser direct writing or electron beam direct writing after correcting the drawing position by
  • step (e) a step of forming wiring between a plurality of chips by repeating the step (d).
  • the method for manufacturing a semiconductor device according to the present invention includes the following steps.
  • the position of the photomask is corrected based on the information on the shift between the reference positions of the first and second chips and the positions of the first and second chips measured in the step (c). Exposing the second photoresist film between the first and second chips,
  • step (h) repeating the step (g) to obtain the second chip between the plurality of chips; Step of exposing the photoresist film of 2,
  • FIG. 1A is a perspective view showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention
  • FIG. 1B is a sectional view of the same.
  • FIG. 2A is a perspective view showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention
  • FIG. 2B is a sectional view of the same.
  • FIG. 3 is a perspective view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 8 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 9 is a perspective view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 10 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 11 is a perspective view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 12 is a perspective view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 13 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 15 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 16 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 17 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 18 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 19 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 20 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 21 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 22 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 23 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 24 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 25 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 26 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 27 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. is there.
  • FIG. 28 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 29 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 30 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 31 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 32 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 33 is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 34 is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 35 is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 36 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 37 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 38 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 39 is a perspective view showing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 40 is a cross-sectional view illustrating the semiconductor device according to the first embodiment of the present invention.
  • FIG. 41 is a cross-sectional view illustrating the semiconductor device according to the first embodiment of the present invention.
  • FIG. 42 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.
  • FIG. 43 is a plan view showing a semiconductor device according to another embodiment of the present invention.
  • FIG. 44 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.
  • an insulating sheet 2 coated with a thermoplastic adhesive (or adhesive) 1 on both sides is attached to one surface of a flat support base 3.
  • the insulation sheet 2 is made of, for example, a polyimide resin film having a thickness of about 20 to 30 zm and a length and width of about 4 Omm X 4 Omm
  • the support base 3 is made of, for example, a metal plate.
  • the adhesive 1 is selected so that the adhesive strength with the support base 3 is smaller than the adhesive strength with the chips 4 (4a to 4c) to be attached to the insulating sheet 2 in a later step.
  • a through hole 5 having a diameter of about 20 / zm is formed in the insulating sheet 2 by, for example, laser or plasma processing.
  • the pattern of the through hole 5 is laid out in accordance with the pad pattern of the chip 4 to be attached to the insulating sheet 2 in the next step.
  • the first chip 4a is placed above the insulating sheet 2 using the chip mounter 6, and the pads 7 formed on the main surface (element forming surface) of the chip 4a are formed.
  • the position is recognized by the first camera 8A, and the position of the through hole 5 formed in the insulating sheet 2 is recognized by the second camera 8B.
  • bump electrodes 9 (or metal pillars) for electrical connection may be formed on the pads 7 of the chip 4a in advance.
  • the bump electrodes 9 (or metal pillars) are made of, for example, Au (gold), A1 (aluminum), Cu (copper) with Ni (nickel) plating or Au plating on the surface.
  • FIG. 6 After the pads 7 of the chip 4a are accurately aligned with the corresponding through holes 5 of the insulating sheet 2 as shown in, the main surface of the chip 4a is attached to the insulating sheet 2. Attach. Subsequently, as shown in FIG. 6, other chips 4b and 4c are sequentially attached to the corresponding positions of the insulating sheet 2 in the same manner as described above. Thereafter, the insulating sheet 2 is peeled from the support base 3 to obtain the insulating sheet 2 in which a plurality of chips 4a to 4c are adhered to predetermined positions as shown in FIG.
  • the bonding of the chips 4a to 4c and the insulating sheet 2 can be performed by the following method.
  • an insulating sheet 2 coated with an adhesive 1 on both sides is attached to one surface of a transparent and flat glass plate 10, and the insulating sheet is formed by the above-described method (for example, laser or plasma processing).
  • a through hole 5 is formed in 2.
  • the insulating sheet 2 is made of, for example, a polyimide resin having optical transparency
  • the glass plate 10 is made of, for example, quartz glass.
  • the adhesive 1 an adhesive whose adhesive strength to the glass plate 10 is smaller than adhesive strength to the chip 4 is selected.
  • the first chip 4a is arranged above the insulating sheet 2 using the chip mounter 6, and the camera 8C is arranged below the insulating sheet 2 to form the chip 4a.
  • the position of the pad 7 formed on the main surface is recognized by the camera 8C through the glass plate 10 and the through hole 5.
  • the chip mounter 6 controls the chip mounter 6 based on the positional deviation information ( ⁇ , ⁇ , ⁇ coordinates) between the pad 7 and the through hole 5 recognized by the force lens 8 C, as shown in FIG.
  • the main surface of the chip 4 a is attached to the insulating sheet 2.
  • the other chips 4b and 4c are sequentially attached to the corresponding positions of the insulating sheet 2 in the same manner as described above, and then the insulating sheet 2 is peeled off from the glass plate 10, whereby As shown in FIG. 7, an insulating sheet 2 in which a plurality of chips 4a to 4c are adhered at predetermined positions is obtained.
  • the bonding of the chips 4a to 4c and the insulating sheet 2 can be performed by the following method.
  • an insulating sheet 2 coated with an adhesive 1 on both sides is attached to one surface of a flat support base 3, and then, as shown in FIG.
  • the pattern showing the chip mounting position on the surface of sheet 2 For example, the outline of chip 4) is formed.
  • the first chip 4a is placed above the insulating sheet 2 using the chip mounter 6, and the outer shape of the chip 4a is recognized by the first camera 8A.
  • SSM3 ⁇ 4 Ru Q a position of the pattern 1 1 formed in the insulating sheet 2 at the second camera 8 B
  • the chip mounter 6 controls the chip mounter 6 based on the positional deviation information ( ⁇ , ⁇ , ⁇ coordinates) between the outer shape of the chip 4 a and the pattern 11 recognized by the two cameras 8 A and 8 B, As shown in FIG. 13, after the chip 4 a and the corresponding pattern 11 are accurately positioned, the main surface of the chip 4 a is attached to the insulating sheet 2. Subsequently, after the other chips 4 b and 4 c are sequentially attached to the corresponding positions of the insulating sheet 2 in the same manner as described above, the insulating sheet 2 is peeled from the support base 3, as shown in FIG. An insulating sheet 2 in which such a plurality of chips 4a to 4c are adhered to predetermined positions is obtained.
  • the bonding of the chips 4a to 4c and the insulating sheet 2 can be performed by the following method.
  • an insulating sheet 2 coated with an adhesive 1 on both sides is attached to one surface of a flat support base 3 (or a transparent glass plate 10).
  • a through hole 5 is formed in 2.
  • a resin 12 whose adhesive strength with the support base 3 (or the transparent glass plate 10) is larger than that with the insulating sheet 2 is placed inside the through hole 5.
  • a resin 12 having optical transparency is used.
  • the chips 4 a to 4 c are sequentially attached to the corresponding positions of the insulating sheet 2 by the method shown in FIGS. 5 and 6 (or FIGS. 9 and 10), and FIG.
  • the insulating sheet 2 is peeled from the support base 3 (or the glass plate 10).
  • the resin 12 filled in the through hole 5 is peeled off together with the support base 3 (or the glass plate 10), so that the insulating sheet 2 as shown in FIG. 7 is obtained.
  • the diameter of the through hole 5 formed in the insulating sheet 2 is small, or the viscosity of the adhesive 1 is small. This is effective when there is a possibility that the adhesive 1 may be clogged.
  • the bonding of the chips 4a to 4c and the insulating sheet 2 can be performed by the following method.
  • a light-transmitting insulating sheet 2 having a thickness of about 20 to 30 m coated with a thermosetting adhesive 1 on one side, and a light-transmitting sheet made of quartz glass or the like Prepare a support stage 16 with a light-shielding target mark 15 A formed in part of the window 14, and superimpose the insulating sheet 2 on the support stage 16 and mechanically fix it with a clamp 13 etc. (Or fix it with adhesive tape).
  • the first chip 4a is held on the lower surface of the X, ⁇ , ⁇ table 17 which can be heated, pressurized and moved up and down.
  • Upper surface of the X, ⁇ , ⁇ table 17 which can be heated, pressurized and moved up and down.
  • a target mark 15B is formed on the main surface of the chip 4a in advance.
  • bump electrodes 9 or metal pillars for electrical connection as shown in FIG. 4 may be formed on the pads 7 of the chip 4a.
  • the X, ⁇ , and ⁇ tables 17 are controlled based on the displacement information (X, Y, and 0 coordinates) of the two target marks 15A and 15B recognized by the camera 8C, and After the tip 4a is moved right above the predetermined position of the insulating sheet 2, the adhesive 1 is heated by pressing the main surface of the chip 4a against the upper surface of the insulating sheet 2 as shown in FIG. By curing, the chip 4a is attached to the insulating sheet 2.
  • the other chips 4b and 4c are sequentially attached to the corresponding positions of the insulating sheet 2 in the same manner as described above, so that a plurality of chips 4a to 4c are formed as shown in FIG.
  • the insulating sheet 2 adhered to the predetermined position is obtained.
  • the insulating sheet 2 to which the chips 4a to 4c are attached by any of the methods described above is placed on a platen 18A as shown in Fig. 21 and the chips 4a to 4c are Apply a highly thermally conductive compound (or adhesive) 19 to the back (top) surface. At this time, spread the clean resin film on the surface plate 18 A, etc. Contamination of the chips 4a to 4c by foreign matter adhering to the surface may be prevented.
  • a heat sink 20 made of a metal such as Cu or A1 is placed on the back surface (upper surface) of the chips 4 a to 4 c, and a second platen is further placed thereon.
  • the heat radiating plate 20 is bonded to the back surfaces of the chips 4 a to 4 c by overlapping the 18 B and pressing the heat radiating plate 20 against the compound 19.
  • the spacer 21 is sandwiched between the two surface plates 18A and 18B, and the chips 4a to 4c are damaged by excessive pressure from the surface plates 18A and 18B. Let's prevent it.
  • a gap between the insulating sheet 2 and the heat sink 20 is filled with an underfill resin 22 having high thermal conductivity.
  • the underfill resin 22 may be injected under a reduced pressure atmosphere of about 100 Pa, for example.
  • a through hole 5 is formed in the insulating sheet 2 by the above-described method, thereby forming a chip as shown in FIG.
  • the pads 7 (or the bump electrodes 9) of the steps 4a to 4c are exposed.
  • the through holes 5 may be formed immediately after the chips 4 a to 4 c are attached to the insulating sheet 2. If foreign matter adheres to the surface of the insulating sheet 2 when removing the surface plates 18 A and 18 B and the spacer 21, clean the surface of the insulating sheet 2 with an organic solvent or the like. It is preferable to perform a cleaning process by plasma assing or the like.
  • wiring is formed on the insulating sheet 2 by the following method.
  • a photosensitive resist applied to the surface of the insulating sheet 2 is exposed and developed to form a resist pattern 23 for wiring formation, and then as shown in FIG. 26.
  • a first layer wiring 24 is formed on the surface of the insulating sheet 2 by embedding a Cu film in a gap between the resist patterns 23 by a plating method.
  • the first-layer wiring 24 is a signal wiring (or bus wiring) that mainly connects the chips 4a to 4c.
  • FIG. 27 is an overall plan view of the insulating sheet 2 on which the first-layer wirings 24 are formed.
  • the chips 4a to 4f include, for example, a CPU, a controller, an image ASIC, an I / O control, a dedicated memory, and a DRAM.
  • the CPU is operated to check the quality of the other chips 4b to 4f.
  • a testing pad 26 for determination is drawn through the wiring 24.
  • the chip is exchanged by the following method, for example. First, as shown in FIG. 28, the wiring 24 connecting the defective chip (for example, 4c) and another chip (4b) is etched and removed.
  • the chip 4c is heated to melt the insulating sheet 2 on the chip 4c and the underfill resin 22 around the chip 4c. At this time, it is preferable to surround the chip 4c with a heat diffusion preventing wall 40 in order to prevent the influence of heat on the surrounding of the adjacent chip 4b.
  • the defective chip 4 c is peeled off from the heat sink 20, and then the surface of the heat sink 20 is cleaned to remove foreign matter. Then, as shown in FIG. 31. Then, glue 4 g of a good chip on the heat sink 20.
  • heat (or light) curable resin 41 is injected into and around the chip 4 g, and the resin 41 is cured by heating (or light irradiation).
  • a through hole 5 is formed in the resin 41 above the pad 7 formed on the main surface of the chip 4 g, and the chip 4 g and the chip 4 b are formed by, for example, the above-mentioned plating method. Is formed to connect the wires 24.
  • a second insulating sheet 27 is attached to the upper part of the wiring 24, and a through hole (not shown) is formed in the insulating sheet 27 by the method described above. Thereafter, a Cu film is buried in the gap between the resist patterns 28 formed on the insulating sheet 27 by the method described above, thereby forming the second-layer wirings 25.
  • the wiring 25 of the second layer is mainly a power supply wiring.
  • a third insulating sheet 29 is connected to the upper part of the wiring 25.
  • a bump electrode 31 for external connection composed of a solder ball, an Au ball, or the like is formed on the through hole 30.
  • a microcomputer with a multi-chip module structure is almost completed.
  • the insulating sheet 27 on which the wiring 25 and the through-hole 28 are formed in advance must be connected to the wiring of the first layer.
  • the bump electrode 3 is attached on the upper part of the through-holes 30.
  • the wiring formed above the chips 4a to 4f may have a multilayer structure of three or more layers as necessary.
  • the wirings 24 and 25 can be formed by the following method.
  • the position of each chip 4 a to 4 f with respect to the insulating sheet 2 is determined by recognizing the reference point (for example, the position of the pad 7) of each chip 4 a to 4 f attached to the insulating sheet 2 with the camera. Is measured.
  • the reference positions of the chips 4a and 4b with respect to the common coordinates of all the chips 4a to 4f affixed to the insulating sheet 2 and the positions of the chips 4a and 4b measured using the above camera After correcting the drawing position based on the positional deviation information ( ⁇ , ⁇ , ⁇ coordinates), as shown in FIG. 35, the chip 4a and the chip 4b are connected by the laser direct writing method or the electron beam direct writing method. A first layer wiring 24 is formed therebetween.
  • the wiring 24 connecting the other chips 4 b to 4 f is sequentially formed by the same method as described above, thereby forming the first layer wiring 24 shown in FIG. 27. To achieve.
  • the wiring forming method described above it is possible to form the wiring 24 having a fine pitch of about 10 ⁇ by correcting the displacement of each chip 4 a to 4 f with respect to the common coordinates. Become.
  • a second insulating sheet 27 is adhered to the upper part of the wiring 24, and a through hole 32 is formed on the insulating sheet 27 by the method described above.
  • a Cu film is deposited on the insulating sheet 27 by sputtering, and the Cu film is patterned using the photoresist film formed by the batch exposure as a mask, thereby forming a second layer on the insulating sheet 27.
  • the eye wiring 25 is formed.
  • the displacement of the chips 4 a to 4 f can be absorbed by the through hole 32, so that
  • the second-layer wiring 25 can be formed by a batch exposure method having a higher throughput than the direct writing method or the electron beam direct writing method.
  • the wiring 24 can be formed by the following method.
  • the surface of the insulating sheet 2 is defined as a reference wiring area (A) defined as “an area including the main surface of the chip and its periphery”, and an inter-chip area defined as “an intermediate area between the chip and the chip”.
  • the wiring 24 is formed by dividing the wiring region (B) and performing two-step exposure.
  • the reference points for example, the positions of the pads 7 of the chips 4a to 4f pasted on the insulating sheet 2 are recognized by the camera, and the respective chips 4a to the insulating sheet 2 are recognized. Measure the position of ⁇ 4f.
  • a Cu film is deposited on the insulating sheet 2 by, for example, a sputtering method.
  • a photoresist film is applied on the Cu film, and then all of the films adhered to the insulating sheet 2 are removed.
  • the position of the photomask based on the deviation information ( ⁇ , ⁇ , ⁇ coordinates) between the reference position of chip 4a with respect to the common coordinates of chips 4a to 4f and the position of chip 4a measured using the above camera Is corrected, and the photoresist film in the reference wiring area (A) of the chip 4a is exposed.
  • wiring 24 A is formed in the reference wiring region (A) of each chip 4 a to 4 f. Form.
  • a new photoresist film is applied on the insulating sheet 2. Then, the reference positions of the chips 4a and 4b with respect to the common coordinates of the chips 4a to 4f, and the positions of the chips 4a and 4b measured using the camera described above. The position of the photomask is corrected based on the displacement information (X, Y, 0 coordinates), and the photoresist film in the inter-chip wiring region (B) of the chips 4a and 4b is exposed.
  • the photoresist film in the inter-chip wiring region (B) of the other chips 4b to 4f is sequentially step-exposed, and then the Cu film is patterned by using the photoresist film as a mask. As shown in FIG. 38, wiring 24B is formed in the inter-chip wiring region (B) of each of the chips 4a to 4f.
  • the wiring 24 (24A + 24B) having a fine pitch of about 10 jum is corrected by correcting the displacement of each chip 4a to 4f with respect to the common coordinates. ) Can be formed. Further, according to the above-described wiring forming method, the wiring 24 can be formed in a shorter time than a laser direct writing method or an electron beam direct writing method having a low throughput.
  • the multi-chip module in which the wirings 24 and 25 are formed by any of the above methods can be used for various packages, for example, a BGA (ball grid array) type package as shown in FIG. It is sealed into a socket pin type package like this, or a TAB lead type package as shown in Fig. 41, and becomes the final product.
  • BGA ball grid array
  • all the chips are attached to one surface of the insulating sheet.
  • some chips (4a to 4e) are attached to one surface of the insulating sheet 2.
  • the wirings 42 and 43 can be formed on the upper part of the chip, and another chip 4f and the wiring 44 can be stacked on the upper part. According to this structure, the length of the wiring connecting the chips 4a to 4f is reduced, so that a multi-chip module with an improved operation speed can be obtained. Also, since the area of the heat radiating plate 20 is reduced, a multi-chip module with a high mounting density can be obtained.
  • the present invention can be applied to, for example, a multi-chip module configured by combining a plurality of chips 4 h, 4 i, and 4 j operating at different power supply voltages, as shown in FIGS. 43 and 44, for example. it can.
  • chip 4 h operates at 1.8 V, for example.
  • a silicon chip on which an integrated circuit is formed a chip 4 i is, for example, a GaAs chip on which an integrated circuit operating at 3.3 V is formed, and a chip 4 h is an integrated circuit, which is operated at, for example, 7.0 V
  • the first layer wiring 45 mainly forms a signal wiring or a bus wiring
  • the second layer wiring 46 is mainly a power supply wiring.
  • These second-layer wirings 46 are configured to be divided for each power supply voltage so that different power supply voltages can be supplied to the plurality of chips 4h, 4i, and 4j.
  • the power supply wirings 46 need only be one layer, so that a low-cost multi-chip module can be obtained.
  • the power supply wiring 46 in the upper layer covers the signal wiring or the bus wiring in the lower layer, a noise-resistant Manoreti chip module can be obtained.
  • the multi-chip module of the present invention can significantly reduce the distance between chips, so that a highly integrated multi-chip module can be easily realized. It can be widely applied to mounting on various electronic devices such as lightweight electronic devices.

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Abstract

A method for manufacturing a multi-chip module (MCM) comprises: (a) forming through holes in an insulating sheet, after applying an adhesive to both sides of the insulating sheet and sticking the insulating sheet to one side of a supporting base; (b) measuring the position of a first chip provided near the insulating sheet and the positions of the through holes; (c) sticking the major surface of the first chip to one side of the insulating sheet, after correcting the position of the first chip based on information on misalignment between the first chip and the through holes; (d) sticking a plurality of chips to one side of the insulating sheet by repeating the steps (c) and (d); and (e) forming a wiring on the other side of the insulating sheet and electrically connecting the wiring and the chips through the through holes.

Description

明 細 書 半導体装置およびその製造方法 技術分野  Description Semiconductor device and method for manufacturing the same
本発明は、 半導体装置およびその製造技術に関し、 特に、 基板上に複数個の半 導体チップを搭載したマルチチップモジュール (Multi Chip Module ;M CM)を有 する半導体装置に適用して有効な技術に関する。 背景技術  The present invention relates to a semiconductor device and a manufacturing technology thereof, and more particularly to a technology effective when applied to a semiconductor device having a multi-chip module (Multi Chip Module; MCM) having a plurality of semiconductor chips mounted on a substrate. . Background art
マルチチップ ·モジュールは、 C P U、 R AM, R OM, A S I Cなどの集積 回路をチップ単位で作成し、 これらのチップを配線基板上に実装することによつ て、 所望のシステムを実現する方式である。 チップを基板上に実装するには、 ヮ ィャボンディング、 T A B、 フリップチップなどの実装方式が用いられる。  The multi-chip module is a method to create a desired system by creating integrated circuits such as CPU, RAM, ROM, and ASIC on a chip-by-chip basis and mounting these chips on a wiring board. is there. To mount the chip on the board, mounting methods such as pin bonding, TAB, and flip chip are used.
この種のマノレチチップモジュー^^については、 例えば 「アイ ·ィー ·ィ— ·ィ 一、 トランザクションズ オン コンポ一ネンッ、 ハイブリツズ、 アンド マ二 ュファクチャリング テクノロジー、 1 2卷、 第 2号、 1 9 8 9年 6月（IEEE TR ANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 12， NO. 2, JUNE 1989)」 P 1 8 5〜P 1 9 4や、 米国特許第 5 2 5 8 9 2 0号などに記載 がある。  This type of manoret chip module ^^ is described in, for example, "Iii, Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 12, No. 2, June 1998 (IEEE TR ANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 12, NO. 2, JUNE 1989) " See No. 920, etc.
マルチチップモジュールの製造工程では、 配線基板上に複数個のチップを実装 した後、 これらのチップを電気的に接続する配線を形成しなければならない。 こ の場合、 例えば携帯情報機器、 ディジタルカメラ、 ノートパソコンといった小型 軽量電子機器に搭載する高集積マルチチップモジュールでは、 1 0 /z m程度の微 細なピッチを有する配線を使ってチップ間を結線する技術が必要となる。しかし、 配線基板上に複数個のチップを実装する従来の技術では、 配線基板上の所定位置 にチップを高精度に実装することが困難なために、 チップの位置ずれが不可避的 に生じる。 そのため、 微細な配線を使ってチップ間を結線する高密度マルチチッ プモジュールを実現するためには、 チップの位置ずれを最小限に抑える技術ゃチ ップの位置ずれを補正してチップ間を高密度に結線する技術の開発が不可欠とな る。 In the manufacturing process of a multi-chip module, it is necessary to mount a plurality of chips on a wiring board and then form wiring for electrically connecting these chips. In this case, for example, in a highly integrated multichip module mounted on small and light electronic devices such as portable information devices, digital cameras, and notebook computers, the chips are connected using wires with a fine pitch of about 10 / zm. Technology is required. However, in the conventional technique of mounting a plurality of chips on a wiring board, it is difficult to mount the chip at a predetermined position on the wiring board with high accuracy, so that a chip displacement is inevitable. Therefore, in order to realize a high-density multi-chip module that connects chips by using fine wiring, technology to minimize chip displacement is needed. It is indispensable to develop a technology to correct the chip displacement and connect the chips with high density.
本発明の目的は、 マルチチップ ·モジュールの実装密度を向上させる技術を提 供することにある。  An object of the present invention is to provide a technique for improving the mounting density of a multichip module.
本発明の前記ならびにその他の目的と新規な特徴は、 本明細書の記述および添 付図面から明らかになるであろう。 発明の開示  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、 以下の通りである。  The following is a brief description of an outline of typical inventions among the inventions disclosed in the present application.
本発明の半導体装置は、 動作電源電圧の異なる集積回路が形成された複数個の チップを組み合わせて構成されたマルチチップモジュールを有し、 チップ間を電 気的に接続する第 1層配線の上部に、 前記チップに電源を供給する第 2層配線が 配置され、 前記第 2層配線は、 前記複数個のチップに異なる電源電圧を供給する ことができるよう、 電源電圧ごとに分割されている。  The semiconductor device of the present invention has a multi-chip module configured by combining a plurality of chips on which integrated circuits having different operation power supply voltages are formed, and is provided above a first layer wiring for electrically connecting the chips. A second layer wiring for supplying power to the chip is arranged, and the second layer wiring is divided for each power supply voltage so that different power supply voltages can be supplied to the plurality of chips.
また、 本発明の半導体装置は、 C P Uを含む複数個のチップを組み合わせて構 成されたマルチチップモジュールを有し、 チップ間を電気的に接続する第 1層配 線の上部に、 前記チップに電源を供給する第 2層配線が配置され、 前記 C P Uに 接続された前記第 1層配線には、 他のチップの動作をテストするためのパッドが 接続されている。  In addition, the semiconductor device of the present invention has a multi-chip module configured by combining a plurality of chips including a CPU, and includes a first layer wiring for electrically connecting the chips, and A second-layer wiring for supplying power is arranged, and a pad for testing an operation of another chip is connected to the first-layer wiring connected to the CPU.
本発明の半導体装置の製造方法は、 以下の工程を含んでいる。  The method of manufacturing a semiconductor device according to the present invention includes the following steps.
( a ) 両面に接着剤を塗布した絶縁シートを支持ベースの一面に貼り付けた後、 前記絶縁シートにスルーホールを形成する工程、  (a) after attaching an insulating sheet coated with an adhesive on both sides to one surface of the support base, forming a through hole in the insulating sheet;
( b ) 前記絶縁シートの近傍に配置した第 1のチップの位置と前記スルーホール の位置とを計測する工程、  (b) measuring the position of the first chip and the position of the through hole disposed near the insulating sheet;
( c ) 前記第 1のチップと前記スルーホールとの位置ずれ情報に基づいて前記第 1のチップの位置を補正した後、 前記第 1のチップの主面を前記絶縁シートの一 面に貼り付ける工程、  (c) After correcting the position of the first chip on the basis of the positional deviation information between the first chip and the through hole, affixing the main surface of the first chip to one surface of the insulating sheet Process,
( d ) 前記工程 （b ) 、 （c ) を繰り返すことにより、 前記絶縁シートの一面に 複数個のチップを貼り付ける工程、 (d) By repeating the steps (b) and (c), one surface of the insulating sheet A process of attaching a plurality of chips,
(e) 前記絶縁シートの他面に配線を形成し、 前記スルーホールを通じて前記配 線と前記チップとを電気的に接続する工程。  (e) forming a wiring on the other surface of the insulating sheet, and electrically connecting the wiring to the chip through the through hole.
また、 本発明の半導体装置の製造方法は、 以下の工程を含んでいる。  The method for manufacturing a semiconductor device according to the present invention includes the following steps.
(a) 両面に接着剤を塗布した絶縁シートを支持ベースの一面に貼り付けた後、 前記絶縁シートの一面にチップ搭載位置を示すパターンを形成する工程、  (a) after attaching an insulating sheet coated with an adhesive on both sides to one surface of a support base, forming a pattern indicating a chip mounting position on one surface of the insulating sheet,
( b ) 前記絶縁シートの近傍に配置した第 1のチップの位置と前記パターンの位 置とを計測する工程、  (b) measuring a position of the first chip arranged near the insulating sheet and a position of the pattern;
( c ) 前記第 1のチップと前記パターンとの位置ずれ情報に基づいて前記第 1の チップの位置を補正した後、 前記第 1のチップの主面を前記絶縁シートの一面に 貼り付ける工程、  (c) a step of correcting the position of the first chip based on positional deviation information between the first chip and the pattern, and pasting a main surface of the first chip to one surface of the insulating sheet;
(d) 前記工程 （b) 、 (c) を繰り返すことにより、 前記絶縁シートの一面に 複数個のチップを貼り付ける工程、  (d) a step of attaching a plurality of chips to one surface of the insulating sheet by repeating the steps (b) and (c);
(e) 前記絶縁シートの他面に配線を形成し、 スルーホールを通じて前記配線と 前記チップとを電気的に接続する工程。  (e) forming a wiring on the other surface of the insulating sheet, and electrically connecting the wiring and the chip through through holes;
また、 本発明の半導体装置の製造方法は、 以下の工程を含んでいる。  The method for manufacturing a semiconductor device according to the present invention includes the following steps.
(a) 一面に接着剤を塗布した絶縁シートを支持ステージに固定する工程、 (a) fixing an insulating sheet coated with an adhesive on one side to a support stage,
(b) 前記絶縁シートの近傍に配置した第 1のチップに形成されたターゲットマ 一クの位置と前記支持ステージに形成されたターゲットマークの位置とを計測す る工程、 (b) measuring a position of a target mark formed on a first chip disposed near the insulating sheet and a position of a target mark formed on the support stage;
( c ) 前記第 1のチップに形成されたターゲットマークと前記支持ステージに形 成されたターゲットマークとの位置ずれ情報に基づいて前記第 1のチップの位置 を補正した後、 前記第 1のチップの主面を前記絶縁シートの一面に貼り付けるェ 程、  (c) correcting the position of the first chip based on positional deviation information between a target mark formed on the first chip and a target mark formed on the support stage; Attaching the main surface of the insulating sheet to one surface of the insulating sheet,
(d) 前記工程 （b) 、 (c) を繰り返すことにより、 前記絶縁シートの一面に 複数個のチップを貼り付ける工程、  (d) a step of attaching a plurality of chips to one surface of the insulating sheet by repeating the steps (b) and (c);
( e ) 前記複数個のチップの裏面に支持ベースを固定する工程、  (e) fixing a support base to the back surface of the plurality of chips,
( f ) 前記絶縁シートの他面に配線を形成し、 スルーホールを通じて前記配線と 前記チップとを電気的に接続する工程。 また、 本発明の半導体装置の製造方法は、 以下の工程を含んでいる。 (f) forming wiring on the other surface of the insulating sheet, and electrically connecting the wiring to the chip through through holes; The method for manufacturing a semiconductor device according to the present invention includes the following steps.
(a) 絶縁シートの一面に複数個のチップの主面を貼り付ける工程、  (a) attaching a plurality of chip main surfaces to one surface of an insulating sheet,
( b ) 前記複数個のチップの裏面に支持べ一スを固定する工程、  (b) fixing a support base to the back surface of the plurality of chips,
(c) 前記絶縁シートに対する前記複数個のチップの位置を計測する工程、  (c) measuring the positions of the plurality of chips with respect to the insulating sheet,
(d) 前記複数個のチップの共通座標に対する第 1および第 2のチップの基準位 置と、 前記工程 （c) で計測された前記第 1および第 2のチップの位置とのずれ 情報に基づいて描画位置を補正した後、レーザ直描法または電子線直描法により、 前記第 1のチップと前記第 2のチップとの間に配線を形成する工程、  (d) a reference position of the first and second chips with respect to a common coordinate of the plurality of chips, and a shift information between the positions of the first and second chips measured in the step (c). Forming a wiring between the first chip and the second chip by laser direct writing or electron beam direct writing after correcting the drawing position by
(e) 前記工程 （d) を繰り返すことにより、 複数個のチップ間に配線を形成す る工程。  (e) a step of forming wiring between a plurality of chips by repeating the step (d).
また、 本発明の半導体装置の製造方法は、 以下の工程を含んでいる。  The method for manufacturing a semiconductor device according to the present invention includes the following steps.
(a) 絶縁シートの一面に複数個のチップの主面を貼り付ける工程、  (a) attaching a plurality of chip main surfaces to one surface of an insulating sheet,
( b ) 前記複数個のチップの裏面に支持べ一スを固定する工程、  (b) fixing a support base to the back surface of the plurality of chips,
( c ) 前記絶縁シートに対する前記複数個のチップの位置を計測する工程、  (c) measuring the positions of the plurality of chips with respect to the insulating sheet,
(d) 前記絶縁シートの他面に導電膜を形成し、 続いて前記導電膜の上部に第 1 のフォトレジスト膜を塗布した後、 前記複数個のチップの共通座標に対する第 1 のチップの基準位置と、 前記工程 （c) で計測された前記第 1のチップの位置と のずれ情報に基づいてフォトマスクの位置を補正し、 前記第 1のチップの主面上 の前記第 1のフォ トレジスト膜を露光する工程、  (d) forming a conductive film on the other surface of the insulating sheet, subsequently applying a first photoresist film on the conductive film, and then referencing the first chip with respect to the common coordinates of the plurality of chips. Correcting the position of the photomask based on the positional information of the position of the first chip and the position of the first chip measured in the step (c); and correcting the position of the first photoresist on the main surface of the first chip. Exposing the film,
(e) 前記工程 （d) を繰り返すことにより、 前記複数個のチップの主面上の前 記第 1のフォトレジスト膜を露光する工程、  (e) exposing the first photoresist film on the main surfaces of the plurality of chips by repeating the step (d);
( f ) 前記第 1のフォ トレジスト膜をマスクにして前記導電膜をパターニングす ることにより、 前記複数個のチップの主面上に配線を形成する工程、  (f) forming wiring on the main surfaces of the plurality of chips by patterning the conductive film using the first photoresist film as a mask,
(g) 前記第 1のフォ トレジスト膜を除去し、 続いて前記導電膜の上部に第 2の フォトレジスト膜を塗布した後、 前記複数個のチップの共通座標に対する前記第 (g) removing the first photoresist film, subsequently applying a second photoresist film on the conductive film, and then applying the second photoresist film to the common coordinates of the plurality of chips;
1および第 2のチップの基準位置と、 前記工程 （c) で計測された前記第 1およ び第 2のチップの位置とのずれ情報に基づいてフォトマスクの位置を補正し、 前 記第 1および第 2のチップの間の前記第 2のフォトレジスト膜を露光する工程、The position of the photomask is corrected based on the information on the shift between the reference positions of the first and second chips and the positions of the first and second chips measured in the step (c). Exposing the second photoresist film between the first and second chips,
(h) 前記工程 （g) を繰り返すことにより、 前記複数個のチップの間の前記第 2のフォトレジスト膜を露光する工程、 (h) repeating the step (g) to obtain the second chip between the plurality of chips; Step of exposing the photoresist film of 2,
( i ) 前記第 2のフォトレジスト膜をマスクにして前記導電膜をパターニングす ることにより、 前記複数個のチップの間に配線を形成する工程。 図面の簡単な説明  (i) forming a wiring between the plurality of chips by patterning the conductive film using the second photoresist film as a mask; BRIEF DESCRIPTION OF THE FIGURES
図 1 ( a ) は、 本発明の実施の形態 1である半導体装置の製造方法を示す斜視 図、 図 1 ( b ) は、 同じく断面図である。  FIG. 1A is a perspective view showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a sectional view of the same.
図 2 ( a ) は、 本発明の実施の形態 1である半導体装置の製造方法を示す斜視 図、 図 2 ( b ) は、 同じく断面図である。  FIG. 2A is a perspective view showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 2B is a sectional view of the same.
図 3は、 本発明の実施の形態 1である半導体装置の製造方法を示す斜視図であ る。  FIG. 3 is a perspective view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 4は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図であ る。  FIG. 4 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 5は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図であ る。  FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 6は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図であ る。  FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 7は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図であ る。  FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 8は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図であ る。  FIG. 8 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 9は、 本発明の実施の形態 1である半導体装置の製造方法を示す斜視図であ る。  FIG. 9 is a perspective view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 1 0は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 10 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 1 1は、 本発明の実施の形態 1である半導体装置の製造方法を示す斜視図で ある。  FIG. 11 is a perspective view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 1 2は、 本発明の実施の形態 1である半導体装置の製造方法を示す斜視図で ある。 図 1 3は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。 FIG. 12 is a perspective view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 13 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 1 4は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 1 5は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 15 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 1 6は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 16 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 1 7は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 17 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 1 8は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 18 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 1 9は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 19 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 2 0は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 20 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 2 1は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 21 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 2 2は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 22 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 2 3は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 23 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 2 4は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で のる。  FIG. 24 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 2 5は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 25 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 2 6は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 26 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 2 7は、 本発明の実施の形態 1である半導体装置の製造方法を示す平面図で ある。 FIG. 27 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. is there.
図 2 8は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 28 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 2 9は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 29 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 3 0は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 30 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 3 1は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 31 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 3 2は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で める。  FIG. 32 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 3 3は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で 図 3 4は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 33 is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 34 is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 3 5は、 本発明の実施の形態 1である半導体装置の製造方法を示す平面図で あ O 0 FIG. 35 is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 3 6は、 本発明の実施の形態 1である半導体装置の製造方法を示す断面図で ある。  FIG. 36 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 3 7は、 本発明の実施の形態 1である半導体装置の製造方法を示す平面図で ある。  FIG. 37 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 3 8は、 本発明の実施の形態 1である半導体装置の製造方法を示す平面図で ある。  FIG. 38 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
図 3 9は、 本発明の実施の形態 1である半導体装置を示す斜視図である。 図 4 0は、 本発明の実施の形態 1である半導体装置を示す断面図である。 図 4 1は、 本発明の実施の形態 1である半導体装置を示す断面図である。 図 4 2は、 本発明の他の実施の形態である半導体装置を示す断面図である。 図 4 3は、 本発明の他の実施の形態である半導体装置を示す平面図である。 図 4 4は、 本発明の他の実施の形態である半導体装置を示す断面図である。 発明を実施するための最良の形態 FIG. 39 is a perspective view showing a semiconductor device according to the first embodiment of the present invention. FIG. 40 is a cross-sectional view illustrating the semiconductor device according to the first embodiment of the present invention. FIG. 41 is a cross-sectional view illustrating the semiconductor device according to the first embodiment of the present invention. FIG. 42 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention. FIG. 43 is a plan view showing a semiconductor device according to another embodiment of the present invention. FIG. 44 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の実施の形態を図面に基づいて詳細に説明する。 なお、 実施の形 態を説明するための全図において、 同一の機能を有するものには同一の符号を付 し、 その繰り返しの説明は省略する。  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same reference numerals are given to components having the same function, and the repeated description thereof will be omitted.
本実施の形態のマルチチップモジュールの製造方法を図 1〜図 4 1を用いてェ 程順に説明する。  A method for manufacturing the multichip module according to the present embodiment will be described in the order of steps with reference to FIGS.
まず、 図 1 ( a ) 、 ( b ) に示すように、 両面に熱可塑性の接着剤 （または粘 着剤） 1を塗布した絶縁シート 2を平坦な支持ベース 3の一面に貼り付ける。 絶 縁シート 2は、 例えば厚さ 2 0〜 3 0 z m程度、 縦 X横 = 4 O mm X 4 O mm程度の ポリイミド樹脂フィルムからなり、 支持ベース 3は、 例えば金属板からなる。 ま た、 接着剤 1は、 支持ベース 3との接着力が後の工程で絶縁シート 2に貼り付け るチップ 4 ( 4 a〜4 c ) との接着力に比べて小さいものを選択する。  First, as shown in FIGS. 1 (a) and 1 (b), an insulating sheet 2 coated with a thermoplastic adhesive (or adhesive) 1 on both sides is attached to one surface of a flat support base 3. The insulation sheet 2 is made of, for example, a polyimide resin film having a thickness of about 20 to 30 zm and a length and width of about 4 Omm X 4 Omm, and the support base 3 is made of, for example, a metal plate. The adhesive 1 is selected so that the adhesive strength with the support base 3 is smaller than the adhesive strength with the chips 4 (4a to 4c) to be attached to the insulating sheet 2 in a later step.
次に、 図 2 ( a ) 、 ( b ) に示すように、 例えばレーザやプラズマ加工により、 絶縁シート 2に直径 2 0 /z m程度のスルーホール 5を形成する。 スルーホール 5 のパターンは、 次の工程で絶縁シート 2に貼り付けるチップ 4のパッドパタ一ン に合わせてレイァゥトする。  Next, as shown in FIGS. 2A and 2B, a through hole 5 having a diameter of about 20 / zm is formed in the insulating sheet 2 by, for example, laser or plasma processing. The pattern of the through hole 5 is laid out in accordance with the pad pattern of the chip 4 to be attached to the insulating sheet 2 in the next step.
次に、 図 3に示すように、 チップマウンタ 6を使って第 1のチップ 4 aを絶縁 シート 2の上方に配置し、 チップ 4 aの主面 （素子形成面） に形成されたパッド 7の位置を第 1のカメラ 8 Aで認識すると共に、 絶縁シート 2に形成されたスル —ホール 5の位置を第 2のカメラ 8 Bで認識する。 図 4に示すように、 チップ 4 aのパッド 7上には、あらかじめ電気的接続用のバンプ電極 9 (または金属柱体） を形成しておいてもよい。バンプ電極 9 (または金属柱体） は、例えば A u (金） 、 A 1 (アルミニウム） 、 表面に N i (ニッケル） メツキや A uメツキを施した C u (銅） などからなる。  Next, as shown in FIG. 3, the first chip 4a is placed above the insulating sheet 2 using the chip mounter 6, and the pads 7 formed on the main surface (element forming surface) of the chip 4a are formed. The position is recognized by the first camera 8A, and the position of the through hole 5 formed in the insulating sheet 2 is recognized by the second camera 8B. As shown in FIG. 4, bump electrodes 9 (or metal pillars) for electrical connection may be formed on the pads 7 of the chip 4a in advance. The bump electrodes 9 (or metal pillars) are made of, for example, Au (gold), A1 (aluminum), Cu (copper) with Ni (nickel) plating or Au plating on the surface.
次に、 上記 2台のカメラ 8 A、 8 Bで認識したパッド 7とスルーホール 5との 位置ずれ情報 （Χ、 Υ、 Θ座標） に基づいてチップマウンタ 6を制御することに より、 図 5に示すように、 チップ 4 aのパッド 7と対応する絶縁シート 2のスル 一ホール 5とを正確に位置合わせした後、 チップ 4 aの主面を絶縁シート 2に貼 り付ける。 続いて、 図 6に示すように、 上記と同様の方法で他のチップ 4 b、 4 cを絶縁シート 2の対応する位置に順次貼り付ける。 その後、 絶縁シート 2を支 持ベース 3から剥離することにより、 図 7に示すように、 複数のチップ 4 a〜4 cが所定の位置に接着された絶縁シート 2を得る。 Next, by controlling the chip mounter 6 based on the positional deviation information (Χ, Υ, Θ coordinates) between the pad 7 and the through hole 5 recognized by the two cameras 8A and 8B, FIG. After the pads 7 of the chip 4a are accurately aligned with the corresponding through holes 5 of the insulating sheet 2 as shown in, the main surface of the chip 4a is attached to the insulating sheet 2. Attach. Subsequently, as shown in FIG. 6, other chips 4b and 4c are sequentially attached to the corresponding positions of the insulating sheet 2 in the same manner as described above. Thereafter, the insulating sheet 2 is peeled from the support base 3 to obtain the insulating sheet 2 in which a plurality of chips 4a to 4c are adhered to predetermined positions as shown in FIG.
チップ 4 a〜 4 cと絶縁シート 2との貼り合わせは、 次のような方法で行うこ ともできる。  The bonding of the chips 4a to 4c and the insulating sheet 2 can be performed by the following method.
まず、 図 8に示すように、 両面に接着剤 1を塗布した絶縁シート 2を透明で平 坦なガラス板 1 0の一面に貼り付け、 前述した方法 （例えばレーザやプラズマ加 ェ） により絶縁シート 2にスルーホール 5を形成する。 絶縁シート 2は、 例えば 光透過性を有するポリイミ ド樹脂からなり、 ガラス板 1 0は、 例えば石英ガラス からなる。 また、 接着剤 1は、 ガラス板 1 0との接着力がチップ 4との接着力に 比べて小さいものを選択する。  First, as shown in FIG. 8, an insulating sheet 2 coated with an adhesive 1 on both sides is attached to one surface of a transparent and flat glass plate 10, and the insulating sheet is formed by the above-described method (for example, laser or plasma processing). A through hole 5 is formed in 2. The insulating sheet 2 is made of, for example, a polyimide resin having optical transparency, and the glass plate 10 is made of, for example, quartz glass. Further, as the adhesive 1, an adhesive whose adhesive strength to the glass plate 10 is smaller than adhesive strength to the chip 4 is selected.
次に、 図 9に示すように、 チップマウンタ 6を使って第 1のチップ 4 aを絶縁 シート 2の上方に配置すると共に、 絶縁シート 2の下方にカメラ 8 Cを配置し、 チップ 4 aの主面に形成されたパッド 7の位置をガラス板 1 0およびスルーホー ル 5を通してカメラ 8 Cで認識する。  Next, as shown in FIG. 9, the first chip 4a is arranged above the insulating sheet 2 using the chip mounter 6, and the camera 8C is arranged below the insulating sheet 2 to form the chip 4a. The position of the pad 7 formed on the main surface is recognized by the camera 8C through the glass plate 10 and the through hole 5.
次に、 上記力メラ 8 Cで認識したパッド 7とスルーホール 5との位置ずれ情報 (Χ、 Υ、 Θ座標） に基づいてチップマウンタ 6を制御することにより、 図 1 0 に示すように、 チップ 4 aのパッド 7と対応する絶縁シート 2のスルーホール 5 とを正確に位置合わせした後、 チップ 4 aの主面を絶縁シート 2に貼り付ける。 続いて、 上記と同様の方法で他のチップ 4 b、 4 cを順次絶縁シ一ト 2の対応す る位置に貼り付けた後、 絶縁シート 2をガラス板 1 0から剥離することにより、 前記図 7に示すような複数のチップ 4 a〜4 cが所定の位置に接着された絶縁シ ート 2を得る。  Next, by controlling the chip mounter 6 based on the positional deviation information (Χ, Υ, Θ coordinates) between the pad 7 and the through hole 5 recognized by the force lens 8 C, as shown in FIG. After accurately aligning the pad 7 of the chip 4 a with the corresponding through hole 5 of the insulating sheet 2, the main surface of the chip 4 a is attached to the insulating sheet 2. Subsequently, the other chips 4b and 4c are sequentially attached to the corresponding positions of the insulating sheet 2 in the same manner as described above, and then the insulating sheet 2 is peeled off from the glass plate 10, whereby As shown in FIG. 7, an insulating sheet 2 in which a plurality of chips 4a to 4c are adhered at predetermined positions is obtained.
チップ 4 a〜 4 cと絶縁シート 2との貼り合わせは、 次のような方法で行うこ ともできる。  The bonding of the chips 4a to 4c and the insulating sheet 2 can be performed by the following method.
まず、 前記図 1に示すように、 両面に接着剤 1を塗布した絶縁シート 2を平坦 な支持ベース 3の一面に貼り付けた後、 図 1 1に示すように、 例えばスクリーン 印刷法により、 絶縁シート 2の表面にチップ搭載位置を示すパターン 1 1 (例え ばチップ 4の外形線など） を形成する。 First, as shown in FIG. 1, an insulating sheet 2 coated with an adhesive 1 on both sides is attached to one surface of a flat support base 3, and then, as shown in FIG. The pattern showing the chip mounting position on the surface of sheet 2 For example, the outline of chip 4) is formed.
次に、 図 1 2に示すように、 チップマウンタ 6を使って第 1のチップ 4 aを絶 縁シート 2の上方に配置し、 チップ 4 aの外形を第 1のカメラ 8 Aで認識すると 共に、 絶縁シート 2に形成された上記パターン 1 1の位置を第 2のカメラ 8 Bで sSM¾ る Q Next, as shown in FIG. 12, the first chip 4a is placed above the insulating sheet 2 using the chip mounter 6, and the outer shape of the chip 4a is recognized by the first camera 8A. , SSM¾ Ru Q a position of the pattern 1 1 formed in the insulating sheet 2 at the second camera 8 B
次に、 上記 2台のカメラ 8 A、 8 Bで認識したチップ 4 aの外形とパターン 1 1との位置ずれ情報 （Χ、 Υ、 Θ座標） に基づいてチップマウンタ 6を制御する ことにより、 図 1 3に示すように、 チップ 4 aと対応するパターン 1 1とを正確 に位置合わせした後、 チップ 4 aの主面を絶縁シート 2に貼り付ける。 続いて、 上記と同様の方法で他のチップ 4 b、 4 cを順次絶縁シート 2の対応する位置に 貼り付けた後、 絶縁シート 2を支持ベース 3から剥離することにより、 前記図 7 に示すような複数のチップ 4 a〜4 cが所定の位置に接着された絶縁シート 2を 得る。  Next, by controlling the chip mounter 6 based on the positional deviation information (Χ, Υ, Θ coordinates) between the outer shape of the chip 4 a and the pattern 11 recognized by the two cameras 8 A and 8 B, As shown in FIG. 13, after the chip 4 a and the corresponding pattern 11 are accurately positioned, the main surface of the chip 4 a is attached to the insulating sheet 2. Subsequently, after the other chips 4 b and 4 c are sequentially attached to the corresponding positions of the insulating sheet 2 in the same manner as described above, the insulating sheet 2 is peeled from the support base 3, as shown in FIG. An insulating sheet 2 in which such a plurality of chips 4a to 4c are adhered to predetermined positions is obtained.
チップ 4 a〜 4 cと絶縁シート 2との貼り合わせは、 次のような方法で行うこ ともできる。  The bonding of the chips 4a to 4c and the insulating sheet 2 can be performed by the following method.
まず、 前記図 1および図 2に示すように、 両面に接着剤 1を塗布した絶縁シー ト 2を平坦な支持ベース 3 (または透明なガラス板 1 0 )の一面に貼り付けた後、 絶縁シート 2にスルーホール 5を形成する。  First, as shown in FIGS. 1 and 2, an insulating sheet 2 coated with an adhesive 1 on both sides is attached to one surface of a flat support base 3 (or a transparent glass plate 10). A through hole 5 is formed in 2.
次に、 図 1 4に示すように、 スルーホール 5の内部に、 支持ベース 3 (または 透明なガラス板 1 0 ) との接着力が絶縁シート 2との接着力に比べて大きい樹脂 1 2を充填する。 なお、 透明なガラス板 1 0を使用する場合は、 榭脂 1 2も光透 過性を有するものを使用する。  Next, as shown in FIG. 14, inside the through hole 5, a resin 12 whose adhesive strength with the support base 3 (or the transparent glass plate 10) is larger than that with the insulating sheet 2 is placed. Fill. When a transparent glass plate 10 is used, a resin 12 having optical transparency is used.
次に、 前記図 5および図 6 (または図 9および図 1 0 ) に示す方法により、 チ ップ 4 a〜4 cを絶縁シート 2の対応する位置に順次貼り付けた後、 図 1 5に示 すように、 絶縁シート 2を支持ベース 3 (またはガラス板 1 0 ) から剥離する。 これにより、 スルーホール 5の内部に充填された樹脂 1 2が支持ベース 3 (また はガラス板 1 0 ) と共に剥離されるため、 前記図 7に示すような絶縁シート 2が 得られる。 この方法は、 絶縁シート 2に形成されるスルーホール 5の径が小さレヽ 力、 または接着剤 1の粘度が小さいために、 チップマウント時にスルーホール 5 が接着剤 1で目詰まりする虞れがあるような場合に有効である。 Next, the chips 4 a to 4 c are sequentially attached to the corresponding positions of the insulating sheet 2 by the method shown in FIGS. 5 and 6 (or FIGS. 9 and 10), and FIG. As shown, the insulating sheet 2 is peeled from the support base 3 (or the glass plate 10). As a result, the resin 12 filled in the through hole 5 is peeled off together with the support base 3 (or the glass plate 10), so that the insulating sheet 2 as shown in FIG. 7 is obtained. In this method, the diameter of the through hole 5 formed in the insulating sheet 2 is small, or the viscosity of the adhesive 1 is small. This is effective when there is a possibility that the adhesive 1 may be clogged.
チップ 4 a〜 4 cと絶縁シート 2との貼り合わせは、 次のような方法で行うこ ともできる。  The bonding of the chips 4a to 4c and the insulating sheet 2 can be performed by the following method.
まず、 図 1 6に示すように、 片面に熱硬化性の接着剤 1を塗布した厚さ 2 0〜 3 0 m程度の光透過性を有する絶縁シート 2と、 石英ガラスなどからなる光透 過窓 1 4の一部に遮光性のターゲットマーク 1 5 Aを形成した支持ステージ 1 6 とを用意し、 絶縁シート 2と支持ステージ 1 6とを重ね合わせてクランプ 1 3な どで機械的に固定 （または粘着テープなどで固定） する。  First, as shown in FIG. 16, a light-transmitting insulating sheet 2 having a thickness of about 20 to 30 m coated with a thermosetting adhesive 1 on one side, and a light-transmitting sheet made of quartz glass or the like Prepare a support stage 16 with a light-shielding target mark 15 A formed in part of the window 14, and superimpose the insulating sheet 2 on the support stage 16 and mechanically fix it with a clamp 13 etc. (Or fix it with adhesive tape).
次に、 図 1 7に示すように、 加熱、 加圧および上下動が可能な X、 Υ、 Θテー ブル 1 7の下面に第 1のチップ 4 aを吸着 '保持し、 これを絶縁シート 2の上面 Next, as shown in FIG. 17, the first chip 4a is held on the lower surface of the X, Υ, Θtable 17 which can be heated, pressurized and moved up and down. Upper surface of
(接着剤 1を塗布した面） の近傍に配置する。 チップ 4 aの主面には、 あらかじ めターゲットマーク 1 5 Bを形成しておく。なお、チップ 4 aのパッド 7上には、 前記図 4に示すような電気的接続用のバンプ電極 9 (または金属柱体） を形成し ておいてもよい。 (The surface to which adhesive 1 has been applied). A target mark 15B is formed on the main surface of the chip 4a in advance. In addition, bump electrodes 9 (or metal pillars) for electrical connection as shown in FIG. 4 may be formed on the pads 7 of the chip 4a.
次に、 図 1 8に示すように、 上記支持ステージ 1 6の下方に配置したカメラ 8 Cを使い、 光透過窓 1 4に形成されたタ一ゲットマ一ク 1 5 Aの位置と、 光透過 窓 1 4を通して見えるチップ 4 aのターゲットマーク 1 5 Bの位置とを認識する。 次に、 上記カメラ 8 Cで認識した 2つのターゲットマーク 1 5 A、 1 5 Bの位 置ずれ情報 （X、 Y、 0座標） に基づいて X、 Υ、 Θテーブル 1 7を制御し、 チ ップ 4 aを絶縁シート 2の所定位置の真上に移動させた後、図 1 9に示すように、 チップ 4 aの主面を絶縁シ一ト 2の上面に押し付けて接着剤 1を加熱硬化するこ とにより、 チップ 4 aを絶縁シート 2に貼り付ける。 続いて、 上記と同様の方法 で他のチップ 4 b、 4 cを順次絶縁シート 2の対応する位置に貼り付けることに より、 図 2 0に示すように、 複数のチップ 4 a〜4 cが所定の位置に接着された 絶緣シート 2を得る。  Next, as shown in FIG. 18, the position of the target mark 15 A formed on the light transmission window 14 and the light transmission Recognize the position of the target mark 15 B of the chip 4 a visible through the window 14. Next, the X, Υ, and Θ tables 17 are controlled based on the displacement information (X, Y, and 0 coordinates) of the two target marks 15A and 15B recognized by the camera 8C, and After the tip 4a is moved right above the predetermined position of the insulating sheet 2, the adhesive 1 is heated by pressing the main surface of the chip 4a against the upper surface of the insulating sheet 2 as shown in FIG. By curing, the chip 4a is attached to the insulating sheet 2. Subsequently, the other chips 4b and 4c are sequentially attached to the corresponding positions of the insulating sheet 2 in the same manner as described above, so that a plurality of chips 4a to 4c are formed as shown in FIG. The insulating sheet 2 adhered to the predetermined position is obtained.
次に、 上記したいずれかの方法でチップ 4 a〜4 cが貼り付けられた絶縁シー ト 2を図 2 1に示すような定盤 1 8 Aの上に置き、 チップ 4 a〜4 cの裏面 （上 面） に高熱伝導性のコンパウンド （または接着剤） 1 9を塗布する。 このとき、 定盤 1 8 Aの上に清浄な樹脂フィルムを敷くなどの方法により、 定盤 1 8 Aの表 面に付着した異物によるチップ 4 a〜4 cの汚染を防ぐようにしてもよい。 Next, the insulating sheet 2 to which the chips 4a to 4c are attached by any of the methods described above is placed on a platen 18A as shown in Fig. 21 and the chips 4a to 4c are Apply a highly thermally conductive compound (or adhesive) 19 to the back (top) surface. At this time, spread the clean resin film on the surface plate 18 A, etc. Contamination of the chips 4a to 4c by foreign matter adhering to the surface may be prevented.
次に、 図 2 2に示すように、 上記チップ 4 a〜4 cの裏面 （上面） に C uや A 1などの金属からなる放熱板 2 0を重ね、 さらにその上部に第 2の定盤 1 8 Bを 重ね合わせて放熱板 2 0をコンパウンド 1 9に押し付けることにより、 チップ 4 a〜4 cの裏面に放熱板 2 0を接着する。 このとき、 2つの定盤 1 8 A、 1 8 B の間にスぺーサ 2 1を挟んでおき、 定盤 1 8 A、 1 8 Bからの過剰な圧力による チップ 4 a〜4 cのダメージを防ぐようにするとよレ、。  Next, as shown in FIG. 22, a heat sink 20 made of a metal such as Cu or A1 is placed on the back surface (upper surface) of the chips 4 a to 4 c, and a second platen is further placed thereon. The heat radiating plate 20 is bonded to the back surfaces of the chips 4 a to 4 c by overlapping the 18 B and pressing the heat radiating plate 20 against the compound 19. At this time, the spacer 21 is sandwiched between the two surface plates 18A and 18B, and the chips 4a to 4c are damaged by excessive pressure from the surface plates 18A and 18B. Let's prevent it.
次に、 図 2 3に示すように、 絶縁シート 2と放熱板 2 0との隙間に高熱伝導性 のアンダフィル樹脂 2 2を充填する。 このとき、 上記隙間に気泡 （ボイ ド） が生 じるような場合は、 例えば 1 0 0 P a程度の減圧雰囲気下でアンダフィル樹脂 2 2を注入するとよレ、。  Next, as shown in FIG. 23, a gap between the insulating sheet 2 and the heat sink 20 is filled with an underfill resin 22 having high thermal conductivity. At this time, if air bubbles (voids) are generated in the gaps, the underfill resin 22 may be injected under a reduced pressure atmosphere of about 100 Pa, for example.
次に、 定盤 1 8 A、 1 8 Bとスぺーサ 2 1とを取り外した後、 前述した方法で 絶縁シート 2にスルーホール 5を形成することにより、 図 2 4に示すように、 チ ップ 4 a〜4 cのパッド 7 (またはバンプ電極 9 ) を露出させる。 なお、 スルー ホール 5は、 チップ 4 a〜4 cを絶縁シート 2に貼り付けた直後に形成してもよ い。 また、 定盤 1 8 A、 1 8 Bとスぺーサ 2 1とを取り外す際に絶縁シート 2の 表面に異物が付着するような場合は、 絶縁シート 2の表面を有機溶剤などで洗浄 した後、 プラズマアツシングなどでクリーニング処理を行うとよい。  Next, after removing the platens 18 A and 18 B and the spacer 21, a through hole 5 is formed in the insulating sheet 2 by the above-described method, thereby forming a chip as shown in FIG. The pads 7 (or the bump electrodes 9) of the steps 4a to 4c are exposed. The through holes 5 may be formed immediately after the chips 4 a to 4 c are attached to the insulating sheet 2. If foreign matter adheres to the surface of the insulating sheet 2 when removing the surface plates 18 A and 18 B and the spacer 21, clean the surface of the insulating sheet 2 with an organic solvent or the like. It is preferable to perform a cleaning process by plasma assing or the like.
次に、 上記絶縁シート 2の上部に次のような方法で配線を形成する。  Next, wiring is formed on the insulating sheet 2 by the following method.
まず、 図 2 5に示すように、 絶縁シ一ト 2の表面に塗布した感光性レジストを 露光、 現像して配線形成用のレジス トパターン 2 3を形成した後、 図 2 6に示す ように、 例えばメツキ法でレジストパターン 2 3の隙間に C u膜を埋め込むこと により、 絶縁シート 2の表面に第 1層目の配線 2 4を形成する。 第 1層目の配線 2 4は、 主としてチップ 4 a〜4 c間を接続する信号配線 （またはバス配線） で ある。  First, as shown in FIG. 25, a photosensitive resist applied to the surface of the insulating sheet 2 is exposed and developed to form a resist pattern 23 for wiring formation, and then as shown in FIG. 26. For example, a first layer wiring 24 is formed on the surface of the insulating sheet 2 by embedding a Cu film in a gap between the resist patterns 23 by a plating method. The first-layer wiring 24 is a signal wiring (or bus wiring) that mainly connects the chips 4a to 4c.
図 2 7は、 上記第 1層目の配線 2 4が形成された絶縁シート 2の全体平面図で ある。 図示のように、 チップ 4 a〜4 f は、 例えば C P U、 コントローラ、 画像 A S I C、 I /O制御、 専用メモリ、 D R AMからなる。 また、 C P Uが形成さ れたチップ 4 aからは、 この C P Uを動作させて他のチップ 4 b〜4 f の良否を 判定するためのテスティングパッド 2 6が配線 2 4を介して引き出されている。 C P Uに内蔵された R O M (またはテスタ内の記憶装置など） に書き込まれたテ スティングプログラムを起動するとチップ 4 b〜4 f のテストが実行され、 その 結果が上記テスティングパッド 2 6から出力される。 そして、 このテストにより 不良チップが検出された場合は、 良品のチップと交換し、 このチップと他のチッ プとを接続する配線 2 4を再度形成する。 FIG. 27 is an overall plan view of the insulating sheet 2 on which the first-layer wirings 24 are formed. As shown, the chips 4a to 4f include, for example, a CPU, a controller, an image ASIC, an I / O control, a dedicated memory, and a DRAM. In addition, from the chip 4a on which the CPU is formed, the CPU is operated to check the quality of the other chips 4b to 4f. A testing pad 26 for determination is drawn through the wiring 24. When the testing program written in the ROM (or the storage device in the tester) built in the CPU is started, the tests of chips 4b to 4f are executed, and the results are output from the above testing pad 26. . If a defective chip is detected by this test, the defective chip is replaced with a good chip, and wiring 24 connecting this chip and another chip is formed again.
チップの交換は、例えば次のような方法で行なう。 まず、 図 2 8に示すように、 不良のチップ （例えば 4 c ) と他のチップ （4 b ) とを接続する配線 2 4をエツ チングして除去する。  The chip is exchanged by the following method, for example. First, as shown in FIG. 28, the wiring 24 connecting the defective chip (for example, 4c) and another chip (4b) is etched and removed.
次に、 図 2 9に示すように、 チップ 4 cを加熱することにより、 チップ 4 cの 上部の絶縁シート 2およびチップ 4 cの周囲のアンダフィル樹脂 2 2を溶融させ る。 このとき、 隣接するチップ 4 bの周囲に熱の影響が及ぶのを防ぐため、 チッ プ 4 cの周囲を熱拡散防止壁 4 0で囲んでおくとよい。  Next, as shown in FIG. 29, the chip 4c is heated to melt the insulating sheet 2 on the chip 4c and the underfill resin 22 around the chip 4c. At this time, it is preferable to surround the chip 4c with a heat diffusion preventing wall 40 in order to prevent the influence of heat on the surrounding of the adjacent chip 4b.
次に、 図 3 0に示すように、 不良のチップ 4 cを放熱板 2 0から剥離し、 次い で放熱板 2 0の表面を洗浄して異物を取り除いた後、 図 3 1に示すように、 良品 のチップ 4 gを放熱板 2 0の上に接着する。  Next, as shown in FIG. 30, the defective chip 4 c is peeled off from the heat sink 20, and then the surface of the heat sink 20 is cleaned to remove foreign matter. Then, as shown in FIG. 31. Then, glue 4 g of a good chip on the heat sink 20.
次に、 図 3 2に示すように、 チップ 4 gの表面および周囲に熱 （または光） 硬 化性の樹脂 4 1を注入し、加熱（または光照射） によって樹脂 4 1を硬化させる。 その後、 図示は省略するが、 チップ 4 gの主面に形成されたパッド 7の上部の樹 脂 4 1にスルーホール 5を形成した後、 例えば前述したメツキ法により、 チップ 4 gとチップ 4 bとを接続する配線 2 4を形成する。  Next, as shown in FIG. 32, heat (or light) curable resin 41 is injected into and around the chip 4 g, and the resin 41 is cured by heating (or light irradiation). After that, though not shown, a through hole 5 is formed in the resin 41 above the pad 7 formed on the main surface of the chip 4 g, and the chip 4 g and the chip 4 b are formed by, for example, the above-mentioned plating method. Is formed to connect the wires 24.
上記したテスティング方法によれば、 チップ 4 a〜4 f を 1個ずつテストする 方法に比べてテスト時間を大幅に短縮することが可能となる。  According to the above-described testing method, it is possible to greatly reduce the test time as compared with the method of testing the chips 4a to 4f one by one.
次に、 図 3 3に示すように、 上記配線 2 4の上部に第 2の絶縁シート 2 7を接 着し、 この絶縁シート 2 7に前述した方法でスルーホール （図示せず） を形成し た後、 絶縁シート 2 7の上部に形成したレジストパターン 2 8.の隙間に前述した 方法で C u膜を埋め込むことにより、 第 2層目の配線 2 5を形成する。 第 2層目 の配線 2 5は、 主として電源配線である。  Next, as shown in FIG. 33, a second insulating sheet 27 is attached to the upper part of the wiring 24, and a through hole (not shown) is formed in the insulating sheet 27 by the method described above. Thereafter, a Cu film is buried in the gap between the resist patterns 28 formed on the insulating sheet 27 by the method described above, thereby forming the second-layer wirings 25. The wiring 25 of the second layer is mainly a power supply wiring.
次に、 図 3 4に示すように、 上記配線 2 5の上部に第 3の絶縁シート 2 9を接 着し、 この絶縁シート 2 9に前述した方法でスルーホール 3 0を形成した後、 そ の上部に半田ボールや A uボールなどからなる外部接続用のバンプ電極 3 1を形 成することにより、 マルチチップモジュール構造のマイコンが略完成する。 Next, as shown in FIG. 34, a third insulating sheet 29 is connected to the upper part of the wiring 25. After forming a through hole 30 on the insulating sheet 29 by the method described above, a bump electrode 31 for external connection composed of a solder ball, an Au ball, or the like is formed on the through hole 30. A microcomputer with a multi-chip module structure is almost completed.
なお、 上記第 2層目の配線 2 5および外部接続用のバンプ電極 3 1を形成する には、 あらかじめ配線 2 5およびスルーホール 2 8が形成された絶縁シート 2 7 を第 1層目の配線 2 4の上部に貼り付け、 次に、 あらかじめスルーホール 3 0が 形成された絶縁シート 2 9を上記絶縁シ一ト 2 7の上部に貼り付けた後、 スルー ホール 3 0の上部にバンプ電極 3 1を形成してもよい。 また、 チップ 4 a〜4 f の上部に形成する配線は、 必要に応じて 3層以上の多層構造にしてもよい。 上記配線 2 4、 2 5は、 次のような方法で形成することもできる。  In order to form the wiring 25 of the second layer and the bump electrode 31 for external connection, the insulating sheet 27 on which the wiring 25 and the through-hole 28 are formed in advance must be connected to the wiring of the first layer. After pasting the insulating sheet 29 on which the through-holes 30 have been formed beforehand on the upper part of the insulating sheet 27, the bump electrode 3 is attached on the upper part of the through-holes 30. One may be formed. Further, the wiring formed above the chips 4a to 4f may have a multilayer structure of three or more layers as necessary. The wirings 24 and 25 can be formed by the following method.
まず、 絶縁シート 2に貼り付けられた各チップ 4 a〜4 f の基準点 （例えばパ ッド 7の位置） をカメラで認識することにより、 絶縁シート 2に対する各チップ 4 a〜 4 f の位置を計測する。  First, the position of each chip 4 a to 4 f with respect to the insulating sheet 2 is determined by recognizing the reference point (for example, the position of the pad 7) of each chip 4 a to 4 f attached to the insulating sheet 2 with the camera. Is measured.
次に、 絶縁シート 2に貼り付けられたすべてのチップ 4 a〜4 f の共通座標に 対するチップ 4 a、 4 bの基準位置と、 上記カメラを使って測定されたチップ 4 a、 4 bの位置とのずれ情報 （Χ、 Υ、 Θ座標） に基づいて描画位置を補正した 後、 図 3 5に示すように、 レーザ直描法または電子線直描法により、 チップ 4 a とチップ 4 bとの間に第 1層目の配線 2 4を形成する。  Next, the reference positions of the chips 4a and 4b with respect to the common coordinates of all the chips 4a to 4f affixed to the insulating sheet 2 and the positions of the chips 4a and 4b measured using the above camera After correcting the drawing position based on the positional deviation information (Χ, Υ, Θ coordinates), as shown in FIG. 35, the chip 4a and the chip 4b are connected by the laser direct writing method or the electron beam direct writing method. A first layer wiring 24 is formed therebetween.
続いて、 上記と同様の方法により、 他のチップ 4 b〜4 f 間を接続する配線 2 4を順次形成することにより、 前記図 2 7に示すような第 1層目の配線 2 4を形 成する。  Subsequently, the wiring 24 connecting the other chips 4 b to 4 f is sequentially formed by the same method as described above, thereby forming the first layer wiring 24 shown in FIG. 27. To achieve.
上記した配線形成方法によれば、 共通座標に対する各チップ 4 a〜4 f の位置 ずれを補正することにより、 1 0 μ ιη程度の微細なピッチを有する配線 2 4を形 成することが可能となる。  According to the wiring forming method described above, it is possible to form the wiring 24 having a fine pitch of about 10 μιη by correcting the displacement of each chip 4 a to 4 f with respect to the common coordinates. Become.
次に、 図 3 6に示すように、 上記配線 2 4の上部に第 2の絶縁シート 2 7を接 着し、 この絶縁シート 2 7に前述した方法でスルーホール 3 2を形成した後、 例 えば絶縁シート 2 7の上部にスパッタリング法で C u膜を堆積し、 一括露光で形 成したフォトレジスト膜をマスクにして C u膜をパターニングすることにより、 絶縁シート 2 7の上部に第 2層目の配線 2 5を形成する。 このとき、 スルーホー ル 3 2の径をチップ 4 a〜4 f の位置ずれの最大値よりも大きくすることにより、 チップ 4 a〜4 f の位置ずれをスルーホール 3 2で吸収することができるので、 前記レ一ザ直描法や電子線直描法よりもスループッ トの高い一括露光方式で第 2 層目の配線 2 5を形成することが可能となる。 Next, as shown in FIG. 36, a second insulating sheet 27 is adhered to the upper part of the wiring 24, and a through hole 32 is formed on the insulating sheet 27 by the method described above. For example, a Cu film is deposited on the insulating sheet 27 by sputtering, and the Cu film is patterned using the photoresist film formed by the batch exposure as a mask, thereby forming a second layer on the insulating sheet 27. The eye wiring 25 is formed. At this time, By making the diameter of the hole 32 larger than the maximum value of the displacement of the chips 4 a to 4 f, the displacement of the chips 4 a to 4 f can be absorbed by the through hole 32, so that The second-layer wiring 25 can be formed by a batch exposure method having a higher throughput than the direct writing method or the electron beam direct writing method.
上記配線 2 4は、 次のような方法で形成することもできる。 この方法は、 絶縁 シート 2の表面を 「チップの主面とその周辺とを含む領域」 として定義される基 準配線領域 （A) と、 「チップとチップの中間領域」 として定義されるチップ間 配線領域 （B ) とに分け、 二段階のステップ露光を行なうことによって配線 2 4 を形成する。  The wiring 24 can be formed by the following method. In this method, the surface of the insulating sheet 2 is defined as a reference wiring area (A) defined as “an area including the main surface of the chip and its periphery”, and an inter-chip area defined as “an intermediate area between the chip and the chip”. The wiring 24 is formed by dividing the wiring region (B) and performing two-step exposure.
具体的には、 まず、 絶縁シート 2に貼り付けられた各チップ 4 a〜4 f の基準 点 （例えばパッド 7の位置） をカメラで認識することにより、 絶縁シート 2に対 する各チップ 4 a〜4 f の位置を計測する。  Specifically, first, the reference points (for example, the positions of the pads 7) of the chips 4a to 4f pasted on the insulating sheet 2 are recognized by the camera, and the respective chips 4a to the insulating sheet 2 are recognized. Measure the position of ~ 4f.
次に、 絶縁シ一ト 2の上部に例えばスパッタリング法で C u膜を堆積し、 続い て C u膜の上部にフォトレジスト膜を塗布した後、 絶縁シート 2に貼り付けられ たすベてのチップ 4 a〜4 f の共通座標に対するチップ 4 aの基準位置と、 上記 カメラを使って測定されたチップ 4 aの位置とのずれ情報 （Χ、 Υ、 Θ座標） に 基づいてフォ トマスクの位置を補正し、 チップ 4 aの基準配線領域 （A) のフォ トレジスト膜を露光する。 次に、 チップ 4 a〜4 f の共通座標に対するチップ 4 bの基準位置と、 上記力メラを使って測定されたチップ 4 bの位置とのずれ情報 ( X、 Y、 0座標） に基づいてフォトマスクの位置を補正し、 チップ 4 bの基準 配線領域 （A) のフォトレジスト膜を露光する。 以下、 同様の方法により、 他の チップ 4 c〜4 f の基準配線領域 （A) およびその周辺領域のフォ トレジスト膜 を順次ステップ露光する。  Next, a Cu film is deposited on the insulating sheet 2 by, for example, a sputtering method. Subsequently, a photoresist film is applied on the Cu film, and then all of the films adhered to the insulating sheet 2 are removed. The position of the photomask based on the deviation information (Χ, Υ, Θ coordinates) between the reference position of chip 4a with respect to the common coordinates of chips 4a to 4f and the position of chip 4a measured using the above camera Is corrected, and the photoresist film in the reference wiring area (A) of the chip 4a is exposed. Next, based on the deviation information (X, Y, 0 coordinates) between the reference position of the chip 4b with respect to the common coordinates of the chips 4a to 4f and the position of the chip 4b measured using the force measurer. Correct the position of the photomask and expose the photoresist film in the reference wiring area (A) of chip 4b. Hereinafter, the photoresist film in the reference wiring area (A) of the other chips 4c to 4f and the peripheral area thereof is sequentially exposed by the same method.
次に、 上記フォトレジスト膜をマスクにして C u膜をパターユングすることに より、 図 3 7に示すように、 各チップ 4 a〜4 f の基準配線領域 （A) に配線 2 4 Aを形成する。  Next, by patterning the Cu film using the photoresist film as a mask, as shown in FIG. 37, wiring 24 A is formed in the reference wiring region (A) of each chip 4 a to 4 f. Form.
次に、 上記フォトレジスト膜を除去した後、 絶縁シート 2の上部に新たなフォ トレジスト膜を塗布する。 そして、 チップ 4 a〜4 f の共通座標に対するチップ 4 a、 4 bの基準位置と、 上記カメラを使って測定されたチップ 4 a、 4 bの位 置とのずれ情報 （X、 Y、 0座標） に基づいてフォトマスクの位置を補正し、 チ ップ 4 a、 4 bのチップ間配線領域（B ) のフォトレジスト膜を露光する。 以下、 同様の方法により、 他のチップ 4 b〜4 f のチップ間配線領域 （B ) のフオトレ ジスト膜を順次ステップ露光した後、 上記フォトレジスト膜をマスクにして C u 膜をパターニングすることにより、 図 3 8に示すように、 各チップ 4 a〜4 f の チップ間配線領域 （B ) に配線 2 4 Bを形成する。 Next, after removing the photoresist film, a new photoresist film is applied on the insulating sheet 2. Then, the reference positions of the chips 4a and 4b with respect to the common coordinates of the chips 4a to 4f, and the positions of the chips 4a and 4b measured using the camera described above. The position of the photomask is corrected based on the displacement information (X, Y, 0 coordinates), and the photoresist film in the inter-chip wiring region (B) of the chips 4a and 4b is exposed. Hereinafter, by the same method, the photoresist film in the inter-chip wiring region (B) of the other chips 4b to 4f is sequentially step-exposed, and then the Cu film is patterned by using the photoresist film as a mask. As shown in FIG. 38, wiring 24B is formed in the inter-chip wiring region (B) of each of the chips 4a to 4f.
上記した配線形成方法によれば、 共通座標に対する各チップ 4 a〜4 f の位置 ずれを補正することにより、 1 0 ju m程度の微細なピッチを有する配線 2 4 ( 2 4 A + 2 4 B ) を形成することができる。 また、上記した配線形成方法によれば、 スループットの低いレーザ直描法や電子線直描法に比べて短時間で配線 2 4を形 成することができる。  According to the above-described wiring forming method, the wiring 24 (24A + 24B) having a fine pitch of about 10 jum is corrected by correcting the displacement of each chip 4a to 4f with respect to the common coordinates. ) Can be formed. Further, according to the above-described wiring forming method, the wiring 24 can be formed in a shorter time than a laser direct writing method or an electron beam direct writing method having a low throughput.
上記したいずれかの方法で配線 2 4、 2 5を形成したマルチチップモジュール は、 各種のパッケージ、 例えば図 3 9に示すような B G A (ボールグリッドァレ ィ） 型のパッケージ、 図 4 0に示すようなソケットピン型のパッケージ、 あるい は図 4 1に示すような T A Bリード型のパッケージなどに封止されて最終製品と なる。  The multi-chip module in which the wirings 24 and 25 are formed by any of the above methods can be used for various packages, for example, a BGA (ball grid array) type package as shown in FIG. It is sealed into a socket pin type package like this, or a TAB lead type package as shown in Fig. 41, and becomes the final product.
以上、 本発明者によってなされた発明を発明の実施の形態に基づき具体的に説 明したが、 本発明は前記実施の形態に限定されるものではなく、 その要旨を逸脱 しない範囲で種々変更可能であることはいうまでもない。  Although the invention made by the inventor has been specifically described based on the embodiment of the invention, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,
前記実施の形態では、 絶縁シートの一面にすべてのチップを貼り付けたが、 例 えば図 4 2に示すように、 絶縁シート 2の一面に一部のチップ （4 a〜4 e ) を 貼り付けてその上部に配線 4 2、 4 3を形成し、 さらにその上部に他のチップ 4 f と配線 4 4とを積層した構造とすることもできる。 この構造によれば、 チップ 4 a〜4 f の間を接続する配線長が短縮されるので、 動作速度の向上したマルチ チップモジュールが得られる。 また、 放熱板 2 0の面積が縮小されるので、 実装 密度の高いマルチチップモジュールが得られる。  In the above embodiment, all the chips are attached to one surface of the insulating sheet. For example, as shown in FIG. 42, some chips (4a to 4e) are attached to one surface of the insulating sheet 2. The wirings 42 and 43 can be formed on the upper part of the chip, and another chip 4f and the wiring 44 can be stacked on the upper part. According to this structure, the length of the wiring connecting the chips 4a to 4f is reduced, so that a multi-chip module with an improved operation speed can be obtained. Also, since the area of the heat radiating plate 20 is reduced, a multi-chip module with a high mounting density can be obtained.
本発明は、 例えば図 4 3、 図 4 4に示すように、 異なる電源電圧で動作する複 数のチップ 4 h、 4 i、 4 jを組み合わせて構成されるマルチチップモジュール などに適用することもできる。 ここで、 チップ 4 hは、 例えば 1 . 8 Vで動作す る集積回路が形成されたシリコンチップ、 チップ 4 iは、 例えば 3 . 3 Vで動作 する集積回路が形成された G a A sチップ、 チップ 4 hは、 例えば 7 . 0 Vで動 作する集積回路が形成された I G B Tチップなどである。 また、 第 1層目の配線 4 5は、 主として信号配線またはバス配線を構成し、 第 2層目の配線 4 6は、 主 として電源配線である。 これら第 2層目の配線 4 6は、 上記複数のチップ 4 h、 4 i、 4 jに異なる電源電圧を供給することができるよう、 電源電圧ごとに分割 された構成になっている。 The present invention can be applied to, for example, a multi-chip module configured by combining a plurality of chips 4 h, 4 i, and 4 j operating at different power supply voltages, as shown in FIGS. 43 and 44, for example. it can. Here, chip 4 h operates at 1.8 V, for example. A silicon chip on which an integrated circuit is formed, a chip 4 i is, for example, a GaAs chip on which an integrated circuit operating at 3.3 V is formed, and a chip 4 h is an integrated circuit, which is operated at, for example, 7.0 V An IGBT chip on which a circuit is formed. The first layer wiring 45 mainly forms a signal wiring or a bus wiring, and the second layer wiring 46 is mainly a power supply wiring. These second-layer wirings 46 are configured to be divided for each power supply voltage so that different power supply voltages can be supplied to the plurality of chips 4h, 4i, and 4j.
上記のようなマルチチップモジュールによれば、 電源配線 4 6がー層で済むの で、 低コストのマルチチップモジュールが得られる。 また、 上層の電源配線 4 6 が下層の信号配線またはバス配線を被覆する構造になっているので、 ノイズに強 いのマノレチチップモジュールが得られる。 産業上の利用可能性  According to the above-described multi-chip module, the power supply wirings 46 need only be one layer, so that a low-cost multi-chip module can be obtained. In addition, since the power supply wiring 46 in the upper layer covers the signal wiring or the bus wiring in the lower layer, a noise-resistant Manoreti chip module can be obtained. Industrial applicability
本発明のマルチチップモジュールは、 チップ同士の間隔を著しく縮小すること ができるので、 集積度の高いマルチチップ ·モジュールを容易に実現することが でき、 例えば携帯情報機器、 ディジタルカメラ、 ノートパソコンといった小型軽 量電子機器を始めとする各種電子機器への実装に広く適用することができる。  The multi-chip module of the present invention can significantly reduce the distance between chips, so that a highly integrated multi-chip module can be easily realized. It can be widely applied to mounting on various electronic devices such as lightweight electronic devices.

Claims

請 求 の 範 囲 The scope of the claims
1 . 動作電源電圧の異なる集積回路が形成された複数個のチップを組み合わせて 構成されたマルチチップモジュールを有する半導体装置であって、 チップ間を電 気的に接続する第 1層配線の上部に、 前記チップに電源を供給する第 2層配線が 配置され、 前記第 2層配線は、 前記複数個のチップに異なる電源電圧を供給する ことができるよう、電源電圧ごとに分割されていることを特徴とする半導体装置。1. A semiconductor device having a multi-chip module configured by combining a plurality of chips on which integrated circuits having different operation power supply voltages are formed, wherein a semiconductor device is provided above a first layer wiring for electrically connecting the chips. A second layer wiring for supplying power to the chip is arranged, and the second layer wiring is divided for each power supply voltage so that different power supply voltages can be supplied to the plurality of chips. Characteristic semiconductor device.
2 . C P Uを含む複数個のチップを組み合わせて構成されたマルチチップモジュ ールを有する半導体装置であって、 チップ間を電気的に接続する第 1層配線の上 部に、 前記チップに電源を供給する第 2層配線が配置され、 前記 C P Uに接続さ れた前記第 1層配線には、 他のチップの動作をテストするためのパッドが接続さ れていることを特徴とする半導体装置。 2. A semiconductor device having a multi-chip module configured by combining a plurality of chips including a CPU, and a power supply to the chips is provided above a first layer wiring for electrically connecting the chips. A semiconductor device, wherein a second layer wiring to be supplied is arranged, and a pad for testing an operation of another chip is connected to the first layer wiring connected to the CPU.
3 . 以下の工程を含むことを特徴とする半導体装置の製造方法；  3. A method for manufacturing a semiconductor device, comprising the following steps:
( a ) 両面に接着剤を塗布した絶縁シートを支持ベースの一面に貼り付けた後、 前記絶縁シートにスルーホールを形成する工程、  (a) after attaching an insulating sheet coated with an adhesive on both sides to one surface of the support base, forming a through hole in the insulating sheet;
( b ) 前記絶縁シー卜の近傍に配置した第 1のチップの位置と前記スルーホール の位置とを計測する工程、  (b) measuring a position of the first chip and a position of the through hole arranged near the insulating sheet;
( c ) 前記第 1のチップと前記スルーホールとの位置ずれ情報に基づいて前記第 (c) the first chip and the through-hole based on positional displacement information between the first chip and the through-hole;
1のチップの位置を補正した後、 前記第 1のチップの主面を前記絶縁シートの一 面に貼り付ける工程、 After correcting the position of the first chip, affixing the main surface of the first chip to one surface of the insulating sheet;
( d ) 前記工程 （b ) 、 ( c ) を繰り返すことにより、 前記絶縁シートの一面に 複数個のチップを貼り付ける工程、  (d) a step of attaching a plurality of chips to one surface of the insulating sheet by repeating the steps (b) and (c);
( e ) 前記絶縁シートの他面に配線を形成し、 前記スルーホールを通じて前記配 線と前記チップとを電気的に接続する工程。  (e) forming a wiring on the other surface of the insulating sheet, and electrically connecting the wiring and the chip through the through hole.
4 . 以下の工程を含むことを特徴とする半導体装置の製造方法；  4. A method for manufacturing a semiconductor device, comprising the following steps:
( a ) 両面に接着剤を塗布した絶縁シートを支持ベースの一面に貼り付けた後、 前記絶縁シートの一面にチップ搭載位置を示すパターンを形成する工程、  (a) a step of forming a pattern indicating a chip mounting position on one surface of the insulating sheet after attaching an insulating sheet coated with an adhesive on both surfaces to one surface of the support base
( b ) 前記絶縁シートの近傍に配置した第 1のチップの位置と前記パタ一ンの位 置とを計測する工程、 (c) 前記第 1のチップと前記パターンとの位置ずれ情報に基づいて前記第 1の チップの位置を補正した後、 前記第 1のチップの主面を前記絶縁シートの一面に 貼り付ける工程、 (b) measuring the position of the first chip and the position of the pattern arranged near the insulating sheet, (c) after correcting the position of the first chip based on positional deviation information between the first chip and the pattern, attaching a main surface of the first chip to one surface of the insulating sheet;
(d) 前記工程 （b) 、 （c) を繰り返すことにより、 前記絶縁シートの一面に 複数個のチップを貼り付ける工程、  (d) a step of attaching a plurality of chips to one surface of the insulating sheet by repeating the steps (b) and (c);
(e) 前記絶縁シートの他面に配線を形成し、 スルーホールを通じて前記配線と 前記チップとを電気的に接続する工程。  (e) forming a wiring on the other surface of the insulating sheet, and electrically connecting the wiring and the chip through through holes;
5. 以下の工程を含むことを特徴とする半導体装置の製造方法；  5. A method for manufacturing a semiconductor device, comprising the following steps:
(a) 一面に接着剤を塗布した絶縁シートを支持ステージに固定する工程、 (b) 前記絶縁シートの近傍に配置した第 1のチップに形成されたターゲットマ 一クの位置と前記支持ステージに形成されたターゲットマークの位置とを計測す る工程、  (a) a step of fixing an insulating sheet coated with an adhesive on one surface to a supporting stage; (b) a position of a target mark formed on a first chip arranged near the insulating sheet and the supporting stage. Measuring the position of the formed target mark,
(c) 前記第 1のチップに形成されたターゲットマークと前記支持ステージに形 成されたターゲットマークとの位置ずれ情報に基づいて前記第 1のチップの位置 を補正した後、 前記第 1のチップの主面を前記絶縁シートの一面に貼り付けるェ 程、  (c) correcting the position of the first chip based on positional deviation information between a target mark formed on the first chip and a target mark formed on the support stage; Attaching the main surface of the insulating sheet to one surface of the insulating sheet,
(d) 前記工程 （b) 、 (c) を繰り返すことにより、 前記絶縁シートの一面に 複数個のチップを貼り付ける工程、  (d) a step of attaching a plurality of chips to one surface of the insulating sheet by repeating the steps (b) and (c);
(e) 前記複数個のチップの裏面に支持ベースを固定する工程、  (e) fixing a support base to the back surface of the plurality of chips,
( f ) 前記絶縁シートの他面に配線を形成し、 スルーホールを通じて前記配線と 前記チップとを電気的に接続する工程。  (f) forming a wiring on the other surface of the insulating sheet, and electrically connecting the wiring and the chip through through holes;
6. 以下の工程を含むことを特徴とする半導体装置の製造方法；  6. A method for manufacturing a semiconductor device, comprising the following steps:
(a) 絶縁シートの一面に複数個のチップの主面を貼り付ける工程、  (a) attaching a plurality of chip main surfaces to one surface of an insulating sheet,
( b ) 前記複数個のチップの裏面に支持べ一スを固定する工程、  (b) fixing a support base to the back surface of the plurality of chips,
(c) 前記絶縁シートに対する前記複数個のチップの位置を計測する工程、 (c) measuring the positions of the plurality of chips with respect to the insulating sheet,
( d ) 前記複数個のチップの共通座標に対する第 1および第 2のチップの基準位 置と、 前記工程 （c) で計測された前記第 1および第 2のチップの位置とのずれ 情報に基づいて描画位置を補正した後、レーザ直描法または電子線直描法により、 前記第 1のチップと前記第 2のチップとの間に配線を形成する工程、 (e) 前記工程 （d) を繰り返すことにより、 複数個のチップ間に配線を形成す る工程。 (d) Based on information on the deviation between the reference positions of the first and second chips with respect to the common coordinates of the plurality of chips and the positions of the first and second chips measured in the step (c). Forming a wiring between the first chip and the second chip by laser direct writing or electron beam direct writing after correcting the drawing position by (e) a step of forming wiring between a plurality of chips by repeating the step (d).
7. 以下の工程を含むことを特徴とする半導体装置の製造方法；  7. A method for manufacturing a semiconductor device, comprising the following steps:
( a ) 絶縁シートの一面に複数個のチップの主面を貼り付ける工程、  (a) attaching a main surface of a plurality of chips to one surface of an insulating sheet,
(b) 前記複数個のチップの裏面に支持ベースを固定する工程、  (b) fixing a support base to the back surface of the plurality of chips,
(c) 前記絶縁シートに対する前記複数個のチップの位置を計測する工程、 (c) measuring the positions of the plurality of chips with respect to the insulating sheet,
(d) 前記絶縁シートの他面に導電膜を形成し、 続いて前記導電膜の上部に第 1 のフォトレジスト膜を塗布した後、 前記複数個のチップの共通座標に対する第 1 のチップの基準位置と、 前記工程 （c) で計測された前記第 1のチップの位置と のずれ情報に基づいてフォトマスクの位置を補正し、 前記第 1のチップの主面上 の前記第 1のフォ トレジスト膜を露光する工程、 (d) forming a conductive film on the other surface of the insulating sheet, subsequently applying a first photoresist film on the conductive film, and then referencing the first chip with respect to the common coordinates of the plurality of chips. Correcting the position of the photomask based on the positional information of the position of the first chip and the position of the first chip measured in the step (c); and correcting the position of the first photoresist on the main surface of the first chip. Exposing the film,
(e) 前記工程 （d) を繰り返すことにより、 前記複数個のチップの主面上の前 記第 1のフォ トレジスト膜を露光する工程、  (e) exposing the first photoresist film on the main surfaces of the plurality of chips by repeating the step (d);
(f ) 前記第 1のフォトレジスト膜をマスクにして前記導電膜をパターニングす ることにより、 前記複数個のチップの主面上に配線を形成する工程、  (f) forming a wiring on the main surface of the plurality of chips by patterning the conductive film using the first photoresist film as a mask,
(g) 前記第 1のフォトレジスト膜を除去し、 続いて前記導電膜の上部に第 2の フォトレジスト膜を塗布した後、 前記複数個のチップの共通座標に対する前記第 1および第 2のチップの基準位置と、 前記工程 （c) で計測された前記第 1およ び第 2のチップの位置とのずれ情報に基づいてフォトマスクの位置を補正し、 前 記第 1および第 2のチップの間の前記第 2のフォトレジスト膜を露光する工程、 (g) removing the first photoresist film, subsequently applying a second photoresist film on top of the conductive film, and then applying the first and second chips to a common coordinate of the plurality of chips; The position of the photomask is corrected based on the deviation information between the reference position of the first chip and the position of the first and second chips measured in the step (c). Exposing the second photoresist film during
(h) 前記工程 （g) を繰り返すことにより、 前記複数個のチップの間の前記第 2のフォトレジスト膜を露光する工程、 (h) exposing the second photoresist film between the plurality of chips by repeating the step (g);
( i ) 前記第 2のフォトレジスト膜をマスクにして前記導電膜をパターニングす ることにより、 前記複数個のチップの間に配線を形成する工程。  (i) forming a wiring between the plurality of chips by patterning the conductive film using the second photoresist film as a mask;
8. 請求項 3〜 7のいずれか 1項に記載の半導体装置の製造方法であって、 前記 配線は、 2以上の配線層に形成され、 第 1層配線は、 前記複数個のチップの間を 接続する配線を含み、 第 2層配線は、 前記複数個のチップに電源を供給する配線 を含むことを特徴とする半導体装置の製造方法。  8. The method for manufacturing a semiconductor device according to claim 3, wherein the wiring is formed in two or more wiring layers, and the first-layer wiring is formed between the plurality of chips. A method of manufacturing a semiconductor device, comprising: wiring for supplying power to the plurality of chips.
9. 請求項 8記載の半導体装置の製造方法であって、 前記複数個のチップ間を電 気的に接続する前記第 1層配線を形成した後、 前記複数個のチップの不良選別を 行なう工程を含むことを特徴とする半導体装置の製造方法。 9. The method of manufacturing a semiconductor device according to claim 8, wherein a voltage is applied between the plurality of chips. A method of manufacturing a semiconductor device, comprising: after forming the first-layer wiring to be connected to each other, performing a defect selection of the plurality of chips.
1 0 . 請求項 9記載の半導体装置の製造方法であって、 前記不良チップの上部の 前記第 1層配線を除去した後、 前記不良チップを前記支持ベースから除去し、 次 いで新たな良品チップを前記支持ベースに搭載した後、 前記良品チップ上に新た な第 1層配線を形成する工程を含むことを特徴とする半導体装置の製造方法。 10. The method for manufacturing a semiconductor device according to claim 9, wherein after removing the first layer wiring on the defective chip, the defective chip is removed from the support base, and then a new good chip is formed. Mounting a semiconductor device on the support base, and then forming a new first layer wiring on the non-defective chip.
1 1 . 請求項 3〜 7のいずれか 1項に記載の半導体装置の製造方法であって、 前 記複数個のチップは、 異なる電源電圧で動作するチップを含むことを特徴とする 半導体装置の製造方法。 11. The method for manufacturing a semiconductor device according to any one of claims 3 to 7, wherein the plurality of chips include chips operating at different power supply voltages. Production method.
1 2 . 請求項 3〜 7のいずれか 1項に記載の半導体装置の製造方法であって、 前 記絶縁シートと前記支持ベースとの隙間にアンダフィル樹脂を充填することを特 徴とする半導体装置の製造方法。  12. The method for manufacturing a semiconductor device according to any one of claims 3 to 7, wherein a gap between the insulating sheet and the support base is filled with an underfill resin. Device manufacturing method.
1 3 . 請求項 3〜 7のいずれか 1項に記載の半導体装置の製造方法であって、 前 記支持ベースは、 放熱板であることを特徴とする半導体装置の製造方法。  13. The method for manufacturing a semiconductor device according to any one of claims 3 to 7, wherein the support base is a heat sink.
1 4 . 請求項 3〜 7のいずれか 1項に記載の半導体装置の製造方法であって、 前 記複数個のチップのパッド上に電気的接続用のバンプ電極または金属柱体を形成 することを特徴とする半導体装置の製造方法。  14. The method for manufacturing a semiconductor device according to any one of claims 3 to 7, wherein a bump electrode or a metal pillar for electrical connection is formed on the pads of the plurality of chips. A method for manufacturing a semiconductor device, comprising:
PCT/JP1998/004463 1998-10-02 1998-10-02 Semiconductor device and method for manufacturing the same WO2000021135A1 (en)

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JP2014096609A (en) * 2014-02-14 2014-05-22 Renesas Electronics Corp Electronic apparatus
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JP2005286345A (en) * 2004-03-26 2005-10-13 Inapac Technology Inc Semiconductor device with a plurality of ground planes
JP2007294863A (en) * 2006-03-31 2007-11-08 Sanyo Electric Co Ltd Circuit apparatus
JP2009194113A (en) * 2008-02-14 2009-08-27 Toshiba Corp Integrated semiconductor device
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JP2014096609A (en) * 2014-02-14 2014-05-22 Renesas Electronics Corp Electronic apparatus
EP4020531A1 (en) * 2020-12-22 2022-06-29 Hitachi Energy Switzerland AG Power semiconductor module, method for manufacturing the same and electrical converter
WO2022136086A1 (en) * 2020-12-22 2022-06-30 Hitachi Energy Switzerland Ag Power semiconductor module, method for manufacturing the same and electrical converter

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