JPH09260581A - Method for manufacturing composite semiconductor device - Google Patents

Method for manufacturing composite semiconductor device

Info

Publication number
JPH09260581A
JPH09260581A JP6245196A JP6245196A JPH09260581A JP H09260581 A JPH09260581 A JP H09260581A JP 6245196 A JP6245196 A JP 6245196A JP 6245196 A JP6245196 A JP 6245196A JP H09260581 A JPH09260581 A JP H09260581A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
semiconductor device
substrate
composite
composite semiconductor
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6245196A
Other languages
Japanese (ja)
Inventor
Masaru Miyazaki
Hiroshi Okabe
Akio Takahashi
Koji Yamada
Kiichi Yamashita
Matsuo Yamazaki
勝 宮▲崎▼
松夫 山▲崎▼
喜市 山下
宏治 山田
寛 岡部
昭雄 高橋
Original Assignee
Hitachi Ltd
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

Abstract

PROBLEM TO BE SOLVED: To uninformize characteristics by a method wherein a semiconductor element is fixed to a composite semiconductor device substrate with resin to be flatted, and the substrate of an assembly jig is detached from the composite semiconductor device substrate.
SOLUTION: An assembly jig 10 is attached to semiconductor elements 4A, 4B. An adhesive layer 5 is formed on a face, and marks of the semiconductor elements 4A, 4B conform to positions of marks 3, 3' of a substrate 1 so that they are arranged, pressed and connected. On a substrate 21 of a composite semiconductor device 20, polyimide resin 22 is applied more thickly than thicknesses of the semiconductor elements 4A, 4B. The assembly jig 10 is counter to the composite semiconductor device 20, which is applied static pressure while the polyimide resin is hardened, and the substrate 1 of assembly jig is separated. Thereby, a wire dimension is reduced and the composite semiconductor device can be arranged with high density and high precision.
COPYRIGHT: (C)1997,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、基板上に複数個の半導体素子を実装してなる複合半導体装置の製造に使用する組み立て用組立て治具及びこれを用いて複合半導体装置を製造する方法に関する。 The present invention relates to relates to a method for manufacturing a composite semiconductor device using the assembly jig and which for assembly used in the production of made to implement a plurality of semiconductor elements on a substrate a composite semiconductor device .

【0002】 [0002]

【従来の技術】電子装置の小形化と高性能化に伴って、 Along with the miniaturization and high performance of the Prior Art In electronic devices,
半導体素子を直接、基板上に実装して回路を構成する、 A semiconductor element directly to form a circuit mounted on a substrate,
いわゆるマルチチップモジュール(以下複合半導体装置と呼ぶ)が検討されている。 So-called multi-chip module (hereinafter referred to as the composite semiconductor device) has been studied. ICやLSIの半導体素子を基板に接続する方式には、(1)アップサイドアップと(2)アップサイドダウンがある。 The method of connecting the semiconductor element of the IC or LSI to a substrate, there is (1) upside-up and (2) upside down. (1)の方式は半導体素子の表面が基板表面と同じ向きにあり、従来技術では、両者の電極間をボンデングワイヤにより接続する技術が多く使われている。 Method (1) is in the same direction as the surface of the semiconductor element substrate surface, in the prior art, a technique for connecting between both of the electrodes by Bonn dengue wires are often used. また、基板に凹みを設け、半導体素子を埋め込んで表面を平坦にして配線層を形成する技術が、例えば特開平5−47856号公報で述べられている。 Further, a recess in the substrate provided a technique of forming a wiring layer in the flat surface embedding the semiconductor element, for example, described in JP-A-5-47856 JP. (2)の方式は半導体素子の表面を基板表面と対向させ、半田ボール等の導電性材料で電極を接続し、固定するものである。 Method (2) is a surface of the semiconductor element to face the substrate surface, connecting the electrode with a conductive material such as solder balls, is intended to fix. これは、従来から広く用いられている技術である。 This is a technique has been widely used.

【0003】 [0003]

【発明が解決しようとする課題】従来技術のアップサイドアップ方式による複合半導体装置は(1)ボンデングワイヤ配線は高周波特性が悪く、ボンデングの処理時間が長い、(2)半導体素子埋め込み用凹みを基板に短時間で精度良く形成することが難しい、(3)基板に素子を取付け、この表面を平坦に仕上げることが難しい等、 [Problems that the Invention is to provide a prior art composite semiconductor device according upside-up system of (1) Bonn dengue wire wiring high frequency characteristics is poor, a long processing time Bondengu, a recess for embedding (2) a semiconductor element it is difficult in a short time accurately formed on a substrate, (3) attaching the element to the substrate, it is difficult to finish the surface flat, etc.,
製造上の欠点があった。 There is a disadvantage in manufacturing. また、アップサイドダウン方式は放熱性が悪いので発熱量の多い半導体素子の実装には使用されていなかった。 Further, Upside-down system has not been used for the implementation of more semiconductor device heat value because poor heat dissipation.

【0004】本発明の目的は、半導体素子を基板上に精度良く配置し、かつこの表面を平坦化して特性の揃った複合半導体装置を製造することにある。 An object of the present invention, precisely placing a semiconductor element on a substrate, and is the surface to produce a uniform composite semiconductor device planarity to characteristics.

【0005】 [0005]

【課題を解決するための手段】上記の目的を達成するために本発明では、複合半導体装置用基板にアルミナ,A In the present invention in order to achieve the above object a means for solving], alumina composite semiconductor device substrate, A
lN,SiC等の絶縁体やSi,GaAs等の半導体を用いる。 l N, insulators and Si such as SiC, a semiconductor such as GaAs is used. これらの形状、サイズは半導体製造装置に使うウエーハ形である。 These shapes, sizes are wafer shaped using the semiconductor manufacturing apparatus. 本発明では(1)複合半導体装置用基板上に半導体素子を配列するための治具(以下、組立て治具と略す)を用い、(2)この組立て治具を用いて複合半導体装置の基板上に設けた樹脂に半導体素子を埋め込んで、ウエーハの表面を平坦にし、(3)ホトリソグラフィの技術によりこのウエーハ上で素子間を接続する配線層を形成すること、により複合半導体装置を一括製造することを特徴としている。 In the present invention (1) Osamu for arranging a semiconductor element on the composite semiconductor device on a substrate for device (hereinafter, referred to as assembly jig) used, (2) substrate of the assembly fixture composite semiconductor device using embed semiconductor elements in the resin provided on the surface of the wafer is flattened, (3) forming a wiring layer connecting the elements in this on-wafer by photolithography technique, by collectively manufacturing a composite semiconductor device it is characterized in that.

【0006】通常、0.2mm程度の厚さの半導体素子を、アップサイドアップで複合半導体装置用基板に取付けホトリソグラフィの技術で基板上の電極と半導体素子の電極を配線接続するよう、本発明ではこの表面の凹凸を10μm以内に平坦化する技術が開発されている。 [0006] Normally, the semiconductor device of about 0.2mm thick, so that the wiring connecting the electrode of the electrode and the semiconductor devices on the substrate in the composite semiconductor device substrate with upside up mounting photolithography techniques, the present invention in a technique for planarizing the unevenness of the surface within 10μm it has been developed. 本発明の組立て治具は、アップサイドアップの方式に対して以下の2通りの基本構成がある。 Assembling jig of the present invention, there is the basic structure of the following two relative method upside up. (a)この組立て治具は複合半導体装置基板に取付ける半導体素子を直接配列した構造で、これらの素子を一括、複合半導体装置基板上の樹脂に転写し表面を平坦にする。 (A) The assembly jig in structure having an array of semiconductor elements attached to the composite semiconductor device substrate directly, collectively these elements, to flatten the transfer surface to the resin of the composite semiconductor device substrate. (b)この組立て治具はSOIウエーハ等の基板に半導体製造技術で凸形状の金型を形成した構造で、複合半導体装置基板上の樹脂にこの治具を加圧し凹みを作り半導体素子を配列して表面を平坦にする。 (B) This assembly jig SOI substrate wafer such as a structure to form a mold having a convex shape in the semiconductor manufacturing technology, array semiconductor elements form a recess pressurizes the jig resin composite semiconductor device substrate to flatten the surface is. またアップサイドダウンの素子に放熱板を取付ける製造方法として本発明の組立て治具を利用する。 The use of the assembly jig of the present invention as a manufacturing method of mounting the heat sink element upside down. このような組立て治具を用いることによって複合半導体装置基板上に多数の複合半導体装置が一括に形成されるので特性の揃った均一なものが大量に生産される特徴がある。 Since such an assembly jig number of the composite semiconductor device in a composite semiconductor device substrate by using a is formed simultaneously has the characteristic that is uniform with uniform properties is produced in large quantities. なお、本発明で言う半導体素子とは半導体製造技術で形成された素子全般の呼称であって、通常のICやLSIのほか、単体のトランジスタやダイオードと受動素子(コイル、抵抗やコンデンサ)またはこれらの複合体をいう。 Note that a semiconductor device in the present invention there is provided a designation of the device in general formed by semiconductor manufacturing technology, in addition to conventional IC and LSI, a single transistor or a diode and passive components (coils, resistors and capacitors), or any of these It refers to the complex. 又、本発明で用いる組立て治具は最新の半導体製造技術によって形成するので、加工精度が高い特徴がある。 Moreover, the assembly jig used in the present invention because it forms by modern semiconductor fabrication techniques, processing accuracy is high features.

【0007】 [0007]

【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION

実施例1 図1に本発明の一実施例である構造の組立て治具を用いて複合半導体装置を製造する工程の主要部を示す。 Example 1 Figure 1 using the assembly jig of the structure according to an embodiment of the present invention showing a main part of a process for manufacturing a composite semiconductor device. 複合半導体装置に使われる半導体素子4A,4Bは組み立て治具10の一部の側断面図、図1(a)と(b)に示すように取付けられる。 The semiconductor device 4A used in composite semiconductor device, 4B is part of the side cross-sectional view of the assembly jig 10 is attached as shown in FIG. 1 and (a) (b). これを以下に説明する。 This will be described below. 組立て治具の基板1には約0.5mm厚さのSOI(Si on The substrate 1 of the assembly jig about 0.5mm thickness of SOI (Si on
Insulator)型Siウエーハを用いる。 Insulator) type Si wafer is used. Si Si
O2膜2上のSi厚さは約1μmで、これに通常の半導体リソグラフィとドライエッチの技術でSiマーク3、 O2 film Si thickness on 2 is about 1 [mu] m, this Si mark 3 in a conventional semiconductor lithography and dry etching techniques,
3´を形成する。 To form a 3 '. これは半導体素子4A,4Bを位置合わせして乗せるためのマークである。 This is a mark for placing in register semiconductor device 4A, and 4B position. 続いてこの表面に接着層5(熱加塑性接着材、例えば日立化成工業株式会社製ハイマル、ガラス転移温度230℃)を回転塗布法により約2μmの厚さで形成する。 Subsequently the adhesive layer 5 (hot-press plastic adhesive, for example, Hitachi Chemical Co., Ltd. Haimaru, glass transition temperature 230 ° C.) to the surface formed with a thickness of about 2μm by spin coating method. パターン認識機構を有する専用チップ取付け機を用いて半導体素子4A、4 Semiconductor devices 4A, using a dedicated chip mounting machine having a pattern recognition mechanism 4
B(大きさ約1.5mm□、厚さ約0.15mm)の目印と基板1のマーク3、3´をそれぞれ位置合わせして配列し、約250℃で加圧接合する。 B (size about 1.5 mm □, the thickness of about 0.15mm is) arranged in alignment respectively mark and the mark 3,3' the substrate 1, to pressure bonding at about 250 ° C.. 保護層で覆われた半導体素子4A、4Bの表面側が接着層5と密着する構成である。 The semiconductor device 4A is covered with the protective layer, the surface side of the 4B is configured to contact with the adhesive layer 5. 次に、半導体素子付き組立て治具10を用いて複合半導体装置20の基板21表面に半導体素子を平坦化埋め込みする手順を図1(c)と(d)により説明する。 It will now be described by the procedure of embedding planarizing a semiconductor element on the substrate 21 surface of the composite semiconductor device 20 using the semiconductor device with the assembly jig 10 Figure 1 (c) (d). 複合半導体装置20の基板21にはアルミナを使い、この上に例えばポリイミド樹脂22を半導体素子4 Use of alumina in the substrate 21 of the composite semiconductor device 20, the semiconductor element 4 on the example a polyimide resin 22
A、4Bの厚さ(0.15mm)以上に厚く塗る。 A, slather the thickness of 4B (0.15 mm) or more. 組立て治具10と複合半導体装置20を対向させ平行に加圧できる専用装置により静圧200を加えながら約280 About 280 while applying static pressure 200 by a dedicated device the assembly jig 10 and the composite semiconductor device 20 can be parallel to the pressure are opposed
℃に加熱し、ポリイミド樹脂(ガラス転移温度約250 ℃ heated to, polyimide resin (glass transition temperature of about 250
℃)を硬化させ、組立て治具の基板1を分離する。 ° C.) to cure the to separate the substrate 1 of the assembly fixture. これによって半導体素子4A、4Bが複合半導体装置20の基板21上の樹脂層22内に埋み込まれ、組立て治具の鏡面で押さえられた平坦な表面構造ができる。 This semiconductor device 4A, 4B are incorporated seen embedded in the resin layer 22 on the substrate 21 of the composite semiconductor device 20, it is a flat surface structure that has been pressed by the mirror surface of the assembly fixture. 組立て治具10から半導体素子4A、4Bを容易に取り外せるよう熱加塑性接着材を用いた例を述べたがこれに限定されるものではなく、高温で接着力が低下する瞬間接着材や、熱剥離性の接着材を用いてもよい。 And not the assembly jig 10 from the semiconductor device 4A, has been described an example using NetsuKa plastic adhesive to 4B easily removable is not limited thereto, and instant adhesive the adhesive strength at high temperatures is lowered, heat the peelable adhesive may be used. 半導体素子を移植した後のマーク付組立て治具基板1はこの複合半導体装置の製造部品として再生使用ができるので極めて経済的である。 Marked assembly jig substrate 1 following transplantation of the semiconductor device is extremely economical since it is reproduced using a manufacturing component of the composite semiconductor device. 半導体素子を平坦に埋め込む樹脂材には、高熱伝導率、低膨張係数、低誘電率および導電性樹脂等の特性を持ったものが用意でき、複合半導体装置の使用目的に応じて選択される。 The resin material to embed the semiconductor element flat, high thermal conductivity, low coefficient of expansion, one having properties such as low dielectric constant and conductive resin ready, is selected according to the intended use of the composite semiconductor device. また樹脂の種類も上記以外に、 The type of resin in addition to the above,
エポキシ系やシリコーン系等の熱硬化性および化学反応性等と選択が可能である。 Thermosetting epoxy-based or silicone-based and it is possible to select a chemical reaction resistance. このほか、埋め込む樹脂材には熱可塑性樹脂や、光を透過する基板を使った場合、紫外線硬化型樹脂の適用も可能である。 In addition, and thermoplastic resin is a resin material to embed, when using a substrate which transmits light, application of the ultraviolet curable resin is also possible.

【0008】図2は本発明によって製造された複合半導体装置のウエーハ全体の概念図を示す。 [0008] Figure 2 shows a conceptual diagram of the entire wafer composite semiconductor device manufactured by the present invention. 図2(a)に複数個の半導体素子4(4個の例)を用いて構成された複合半導体装置7が複合半導体装置の基板20に多数埋め込まれた模様を、図2(b)と(c)に異種類の複合半導体装置に対応して半導体素子を埋め込んだ、それぞれの部分図を示す。 A plurality of semiconductor elements 4 (four examples) combined semiconductor device 7 constituted by using the multiple embedded pattern on the substrate 20 of the composite semiconductor device in FIG. 2 (a), FIG. 2 (b) ( embedded semiconductor device in response to different kinds of composite semiconductor device in c), indicating the respective partial view. この後ウエーハ基板上で部品や配線層が形成、接続され、複合半導体装置が完成する。 Parts and wiring layer at the after wafer substrate is formed, is connected, the composite semiconductor device is completed. この基板を個々の複合半導体装置に分割して使用するが、分割しやすいよう区分線7(樹脂の厚さを薄くする)を付けるが、これは、組み立て治具の方に形成してある。 Although it used by dividing the substrate into individual composite semiconductor device, although attaching the divided easily as separation line 7 (the thickness of the resin), which is formed toward the assembly jig.

【0009】図3は本発明の特徴の一つを説明すためのものである。 [0009] FIG. 3 is for explaining the feature of the present invention. 複合半導体装置に用いる半導体素子は例えばGaAsICとSiICのように別々のプロセスや材料で作られた厚さの異なる半導体素子を用いることが多い。 Combined semiconductor element used in the semiconductor device is often to use a semiconductor device having different thicknesses made in a separate process and materials such as, for example GaAsIC and Si IC. 厚さの異なる半導体素子24A(厚さ0.2m The thickness of different semiconductor device 24A (thickness 0.2m
m)、24B(厚さ0.15mm)を図1と同様の組立て治具10によって複合半導体装置の基板21と樹脂層22に埋め込んだ後の断面構造図を図3に示す。 m), it shows 24B cross-sectional view after embedded in the substrate 21 and the resin layer 22 of the composite semiconductor device by the same assembling jig 10 and FIG. 1 (thickness 0.15 mm) in FIG. 2素子の厚さの差D(この例では0.05mm)は、埋め込み樹脂層22によって吸収され、複合半導体装置の仕上り表面は平坦になることがわかる。 The thickness of the difference D 2 element (0.05 mm in this example) is absorbed by the embedded resin layer 22, the finished surface of the composite semiconductor device is seen to become flat. これによってウエーハ表面の段差がないので後続する配線工程に問題が無くなり、性能向上と大幅なコスト低減効果が達成される。 Thus since there is no step difference of the wafer surface there is no problem in subsequent wiring process, significant cost reduction and performance improvement is achieved.

【0010】図4は図1の製造方法で作製した無線通信用高周波回路の複合半導体装置40の断面構造図である。 [0010] FIG. 4 is a cross-sectional view of a composite semiconductor device 40 of the wireless communication frequency circuit fabricated by the manufacturing method of FIG. 高出力GaAsIC4Aと低出力SiIC4Bをアルミナ基板41上に配列し、樹脂で平坦化した後、ホトリソグラフィ技術によって第一の層間絶縁膜44上に、 The high output GaAsIC4A and low output SiIC4B arranged on the alumina substrate 41, after planarizing a resin, on the first interlayer insulating film 44 by photolithography,
第一の配線金属45を、第二の層間絶縁膜46上に、第二の配線金属47を形成し2層配線を行ったものである。 A first interconnect metal 45, on the second interlayer insulating film 46 is obtained by performing the second formed two-layer wiring of the wiring metal 47. 本発明の製造方法では平坦化した複合半導体装置のウエーハ表面は全面にわたって数μm以内がえられ半導体素子を配線する配線層の最小幅は約2μmと通常のウエーハ上と同程度の微細パターンまで対応が可能になった。 Wafer surface of the composite semiconductor device planarization of the production method of the present invention corresponds to the minimum width of approximately 2μm and the normal wafer comparable fine pattern wiring layer for wiring the semiconductor elements within are example number μm over the entire surface It has become possible. 高周波用なので図4のように、導電層43により半導体素子裏面の電位を固定する必要があり、このため図1(b)の工程の後に、組立て治具表面にAuを蒸着して用い、半導体素子埋め込み時に導電層43を樹脂内に形成した。 Since high frequency as shown in FIG. 4, it is necessary to fix the potential of the back surface the semiconductor element by a conductive layer 43, after the process of this for FIG. 1 (b), the reference by depositing Au on the assembly jig surface, the semiconductor the conductive layer 43 element upon implantation was formed in the resin.

【0011】実施例2 図5に本発明の他の実施例である複合半導体装置を製造する工程の主要部を示す。 [0011] showing a main part of a process for manufacturing a composite semiconductor device according to another embodiment of the present invention in Example 2. FIG. これはフェイスダウンボンデングされた半導体素子の裏面に他の構造の組立て治具を用いて放熱板を取付けた構造の複合半導体装置の製造方法である。 This is a method for manufacturing a composite semiconductor device mounting structure in which a heat radiating plate using an assembly jig other structures on the rear surface of facedown Bonn dengue semiconductor device. 本発明に用いる組立て治具50は実施例1と同様の基板51を用い、これにSiマーカ53、53´ Assembly jig 50 used in the present invention using the same substrate 51 as that in Example 1, this Si marker 53,53'
を形成し、接着層55を形成する。 It is formed and to form the adhesive layer 55. 続いてCuからなる放熱板(大きさ2mm□、厚さ0.1mm)54A、5 Subsequently a Cu radiator plate (size 2 mm □, 0.1 mm thickness) 54A, 5
4Bを組立て治具基板51の表面にマーク合わせで接合し組立て治具50とする(図5(a)と(b))。 4B joined by mark alignment on the surface of the assembly jig substrate 51 and the assembly jig 50 (FIG. 5 and (a) (b)). 半導体素子(大きさ1.5mm□、厚さ0.4mm)64 A semiconductor element (size 1.5 mm □, 0.4 mm thickness) 64
A、64Bが複合半導体装置の基板61に半田ボール6 A, solder on the substrate 61 of the 64B is a composite semiconductor device ball 6
5によってフェイスダウンボンデングされ、これに樹脂62を乗せ、上記組立て治具50の放熱板54A、54 5 is facedown Bonn dengue by which to place the resin 62, the heat radiating plate 54A, 54 of the assembly jig 50
Bを半導体素子64A、64Bに位置合わせして加圧2 B the semiconductor device 64A, in alignment to 64B pressurized 2
00する(図5(c))。 00 (FIG. 5 (c)). 図6はこの後、組立て治具5 6 After this, the assembly jig 5
0の基板51を取り外し、電磁シールド効果のAuの金属被膜69を形成して複合半導体装置を完成した概念断面図である。 Remove the 0 of the substrate 51 is a conceptual cross-sectional view of the completed composite semiconductor device by forming an Au metal film 69 of the electromagnetic shielding effect. 同図から、樹脂層62によって半導体素子64A、64Bに密着してそれぞれの放熱板54A、5 From the figure, the semiconductor element 64A with a resin layer 62, in close contact with the 64B each radiator plate 54A, 5
4Bが固定されるので、半導体素子からの放熱特性が従来より大幅に改善される。 Since 4B is fixed, the heat dissipation characteristics of the semiconductor element is significantly improved than before. 樹脂材は熱伝導性の優れているものを用いた。 Resin were used as superior thermal conductivity. ウエーハ上に形成した複合半導体装置を個別のものに分割しやすくし、上記の実施例では各素子毎に放熱板を取り付けた例を示したが、大きな面積の放熱板を複数個の素子に共用して取付けてもよく、放熱板の材質はCuに限るものでもない。 The composite semiconductor device formed on the wafer easily divided into those individual, in the above embodiment showed the example in which the heat radiating plate for each element, share heatsink large area into a plurality of elements It may be attached to the material of the heat sink nor limited to Cu.

【0012】実施例3 図7と図8に基づいて本発明による別の実施例を図9と図10で説明する。 [0012] Based on the Embodiment 3 Figure 7 and Figure 8 illustrates another embodiment according to the present invention in FIGS. 9 and 10. 図7と図8は本発明による複合半導体装置の製造工程において、複合半導体装置の基板に半導体素子を挿入する樹脂材の凹みを形成するために使う組立て治具である。 In the manufacturing process of the composite semiconductor device according to Figures 7 and 8 present invention, an assembled jig used to form a recess of the resin material for inserting a semiconductor element on a substrate of a compound semiconductor device. 図7の組立て治具70はSOI Assembly jig 70 of FIG. 7 SOI
(Si on Insulator)型Siウエーハ(厚さ約600μm)によりSi基板71上のSiO2 (Si on Insulator) type by Si wafer (thickness: about 600 .mu.m) on the Si substrate 71 SiO2
層(厚さ約1μm)72をドライエッチング停止層として使い、上部Si層を凸型形状パターン74A、74 Use layer (thickness of about 1 [mu] m) 72 as a dry etching stopper layer, the upper Si layer convex shape patterns 74A, 74
B、76、77に加工した構造である。 B, and processed structure 76 and 77. 上部Si層の厚さは約150μmで塩素系ガスを用いたマイクロ波励起の異方性ドライエッチングによって垂直形状にする。 The thickness of the upper Si layer is a vertical shape by anisotropic dry etching of microwave excitation using a chlorine-based gas at about 150 [mu] m. 同図の凸部74A、74Bは半導体素子用、また凸部76 Protrusions 74A of FIG, 74B is a semiconductor device, also the convex portions 76
は複合半導体装置の基板電極と導通を取るスルーホール形成用、および凸部77は個々の複合半導体装置分割用、の樹脂材凹み形成用である。 The through holes formed to take a conducting substrate electrode of the composite semiconductor device, and the convex portion 77 is individual composite semiconductor device splitting, for indentations of the resin formed. 図7では凸部の断面形状は垂直である例を述べたが、図8に示すようにウエットエッチング等を併用して最適化した条件で、断面形状の一部にテーパをもつ凸部84A、84B、87の組み立て治具も使われる。 Has been described an example cross-sectional shape is vertical protrusions 7, under the conditions optimized in combination of wet etching or the like as shown in FIG. 8, the convex portion 84A having a tapered portion of the cross-sectional shape, 84B, 87 of the assembly jig is also used. 凸部74A,74Bと84A,8 Protrusions 74A, 74B and 84A, 8
4Bの寸法(W×L×T)は、これを使って成型した樹脂材の凹みに挿入する半導体素子の寸法と等しいかやや大きめにする。 4B dimensions (W × L × T) is equal to or slightly larger the dimensions of the semiconductor device to be inserted into the recess of the resin material was molded using this. 組立て治具70、80の凸部側は、Si Convex side of the assembly fixture 70, 80, Si
O2等の絶縁膜や金属膜等で覆って表面保護し、この形状劣化を防止している。 Surface protection is covered with an insulating film or a metal film of O2, etc., to prevent the deterioration in shape. SOI構造ウエーハ基板を用いているので、凸部の高さTは半導体素子の厚さに正確に合わせることができ、しかも組立て治具(ウエーハ)全体の厚さばらつきは1μm以下に制御できる特徴がある。 Since an SOI structure wafers substrate, the height T of the convex portion can be matched exactly to the thickness of the semiconductor device, moreover the thickness variation in the entire assembly fixture (wafer) is characterized that can be controlled to 1μm or less is there. また凸部パターンの配列精度はホトリソグラフィ技術によって決まるもので、現状では0.5μm以下が得られており、極めて高精度の治具を実現することができる。 The sequence accuracy of the convex portion pattern intended to depend photolithography, at present has been obtained 0.5μm or less, it is possible to achieve very high accuracy of the jig. さらに上記基板は熱膨張係数が小さく、数100℃ Further the substrate has a small thermal expansion coefficient, the number 100 ° C.
の高温にも安定である特徴がある。 It is characterized in a stable high temperature. 本発明の製造で用いる組立て治具は樹脂層に凹型を成型する用途のみなので劣化することがなく繰り返し使用ができるので経済的である。 Assembly jig used in the production of the present invention is economical because it is because only applications for molding the concave repeatedly without degrading used in the resin layer. この実施例では組立て治具の基板材にSOI型S SOI-type S to the substrate material of the assembly fixture in this embodiment
iウエーハを用いて説明したが、厚さが約50μm以下と薄い半導体素子を実装する場合には、加工誤差が大きくならないのでSOI基板材に限定することなく、Si Has been described with reference to i wafer, when the thickness is mounted about 50μm thinner than the semiconductor element is not limited to the SOI substrate material since machining errors does not become large, Si
基板材を精密にドライエッチする方法やNi厚メッキ法等で凸部パターン作ってもよい。 Substrate material may be made protrusion pattern precisely by dry etching methods or Ni thickness plating method.

【0013】図7と図8の組立て治具を用いて本発明による複合半導体装置の製造方法の他の例を図9と図10 [0013] Figure 9 another example of a method for manufacturing a composite semiconductor device according to the present invention using an assembly jig of Figure 7 and Figure 8 and Figure 10
で説明する。 In the description. 図9は複合半導体装置の製造工程のうち、 9 in the manufacturing process of the composite semiconductor device,
特に半導体素子74A,74Bを挿入するための凹み9 Depressions 9 for particular insertion semiconductor device 74A, the 74B
5A,95B形成する実施例を示す。 5A, it shows an embodiment of 95B formed. 複合半導体装置9 Composite semiconductor device 9
0の基板91はSiウエーハで、この表面に液状のポリイミド系熱硬化性樹脂(例えば日立化成工業株式会社製PIX−8540)92を0.2mm以上の厚さで塗布する。 0 of the substrate 91 is Si wafer, is coated on the surface of the polyimide-based thermosetting resin (e.g., Hitachi Chemical Co., Ltd. PIX-8540) 92 of the liquid at above 0.2mm thickness. 図7と同様の組立て治具70の表面には成型後、 After molding to the surface of the same assembly jig 70 and FIG. 7,
樹脂から分離を容易にするためSi系離型剤が使われる(図中省略、(図9(a))。続いて、加熱と加圧機構をもった専用装置で両者を平行に加圧200する(図9 Si-based mold release agent to facilitate separation from the resin is used (in the figure is omitted, (FIG. 9 (a)). Then, in parallel to each other pressure 200 by a dedicated device having a heating and pressing mechanism to (Figure 9
(b))。 (B)). 熱硬化性樹脂層92を硬化させ、組立て治具70を取り除くとSiウエーハ基板91上に凹み(深さ約150μm)95A、95Bが形成される(図9 Curing the thermosetting resin layer 92, when removing the assembly jig 70 recessed on the Si wafer substrate 91 (depth of about 150 [mu] m) 95A, 95B are formed (FIG. 9
(c))。 (C)).

【0014】図10は図8と同様な組立て治具を用いて形成した基板100の樹脂材凹み105に半導体素子1 [0014] Figure 10 is a semiconductor element 1 in the resin material recess 105 of the substrate 100 formed using the same assembly jig and 8
04を入れる状態の断面構造を示す。 Shows a cross-sectional structure of the state put 04. 凹み105の断面構造は、テーパが付き、半導体素子(大きさ約1mm Cross-sectional structure of the recess 105, a taper is, the semiconductor element (size about 1mm
□,厚さ約0.15mm)104より大きい。 □, about 0.15 mm) greater than 104 thick. 半導体素子の表面を上にして所定の凹み105に配列して行く。 The surface of the semiconductor device in the above go arranged in a predetermined recess 105.
この工程でSiウエーハ基板100に上下、左右方向の微振動を与えると半導体素子を凹み105内に確実に挿入できる。 Vertical in this step the Si wafer substrate 100 can be reliably inserted into the 105 recess the semiconductor device given a slight vibration in the lateral direction. この後、樹脂を約2μmの厚さで塗布し、さらに平板によりウエーハ基板100の表面を加圧(加熱)して半導体素子を樹脂で固定し、表面を平坦化する。 Thereafter, it was applied in a thickness of about 2μm resin, further the surface of the wafer substrate 100 by pressure (heating) the semiconductor element fixed with resin by flat to flatten the surface. ポリイミド樹脂は、最終的に温度を約350℃まであげて処理する。 Polyimide resin will eventually processed by raising the temperature to about 350 ° C..

【0015】本発明による製造法では凹みの寸法形成が高精度にでき、廉価な製造装置で半導体素子を定位置に挿入し、これによって配線寸法の縮小がはかれ、高密度、高精度に配列された複合半導体装置がえられるようになった。 [0015] can be a dimension forming high precision indentations in the production process according to the invention, by inserting the semiconductor elements in place at an inexpensive manufacturing apparatus, thereby reducing wiring dimensions Hakare, high density, arranged with high precision composite semiconductor device has come to be e.

【0016】実施例4 高周波用複合半導体装置では半導体素子裏面の電位を固定する必要から、実施例3の製造方法を一部変更した工程の実施例を図11に示す。 [0016] the need to fix the potential of the back surface the semiconductor device in the embodiment 4 frequency composite semiconductor device, illustrating an embodiment of a process, which is a partial modification of the method of Example 3 in FIG. 11. 凹部樹脂層122の表面に導電層126を形成するため図8と同様の組立て治具1 Assembly similar to FIG. 8 to form a conductive layer 126 on the surface of the concave resin layer 122 jig 1
10の凸部114A,114B形状をテーパ状にし、この表面全面にSiO2膜を被着し(図中省略)、Auの導電層116を厚さ約200nm、蒸着によって形成した(図11(a))。 10 of the convex portion 114A, the 114B shape tapered, and the whole surface deposited an SiO2 film (figure omitted), a conductive layer 116 having a thickness of about 200nm of Au, were formed by vapor deposition (FIG. 11 (a) ). その後、基板121上の樹脂層1 Thereafter, the resin layer 1 on the substrate 121
22に組み立て治具を加圧、成型し、組立て治具110 The assembly jig pressure, and molded into 22, the assembly jig 110
の表面の、SiO2と剥がれ易いAu層116を樹脂層122の表面に導電層126として転写した(図11 The surface of the transfer of the prone Au layer 116 peeled off and SiO2 as a conductive layer 126 on the surface of the resin layer 122 (FIG. 11
(b))。 (B)). なお、導電層126は他の金属であってもよい。 The conductive layer 126 may be other metals. また、導電層の形成方法も、凹型に成型した樹脂層に直接、以下の技術を用いて導電層を形成してもよい。 The formation method of the conductive layer is also directly to the resin layer is molded into a concave shape may be formed a conductive layer using the following techniques. (1)金属層を真空蒸着する、(2)導電樹脂層を塗布し、同じ組立て治具を用いて成型して導電層形成する、(3)無電解メッキする。 (1) vacuum deposition of metal layer, (2) conducting the resin layer was coated, molded to form a conductive layer using the same assembly jig, electroless plating (3).

【0017】以上本発明の基本的製造方法を実施例で述べたが、本発明の主旨から組立て治具の材料はSOIに限らず、Si基板、セラミックス、金属等、精密な加工ができるものであればよい。 [0017] The basic production method of above invention has been described in the examples, the material of the assembly fixture from the gist of the present invention is not limited to SOI, Si substrate, a ceramic, a metal or the like, as it can be precisely machined it is sufficient. また複合半導体装置用基板は、上記で述べた例の他、WCu等の金属であってもよい。 The substrate composite semiconductor device, another example described above, may be a metal such as WCu.

【0018】 [0018]

【発明の効果】複合半導体装置を製造する工程に以上述べた組立て治具を用いることによって以下の効果が得られた。 [Effect of the Invention] The following effects by using the assembly jig described above to the step of producing a composite semiconductor device was obtained.

【0019】(1)組立て治具につけた半導体素子を一括して複合半導体装置基板に埋め込む方法では、各半導体素子の厚さがばらついていても、埋め込んだ基板表面が平坦化でき、これによって配線寸法の縮小がはかれ、 [0019] (1) In the method of embedding a semiconductor element attached to the assembly jig collectively composite semiconductor device substrate, even if variations in thickness of the semiconductor elements, can flatten a substrate surface embedded, whereby wiring reduction of dimensions Hakare,
高密度、高精度に配列された複合半導体装置がえられるようになった。 Dense, complex semiconductor devices arranged in a high accuracy came to be e.

【0020】(2)組立て治具につけた放熱板の部品を一括して半導体素子の裏面に取付ける製造方法により、 [0020] (2) by the method of attaching the rear surface of the semiconductor device are collectively part of the heat sink attached to the assembly jig,
放熱のよい、信頼性の高い複合半導体装置を安く提供できるようになった。 Good heat dissipation, it becomes possible to provide cheap and reliable compound semiconductor device.

【0021】(3)加工精度と配列精度の優れた組立て治具により樹脂層に半導体素子を埋め込むための凹部を形成して、これによって小型化された複合半導体装置を安く提供できるようになった。 [0021] (3) forming a recess for embedding a semiconductor element in the resin layer by excellent assembling jig machining accuracy and sequence accuracy, thereby has become possible to provide cheap composite semiconductor device miniaturized .

【0022】(4)組立て治具の適用によって複合半導体装置の製造方法は、ウエーハの一括処理が出来るようになって大量生産による低価格化を達成できるようになった。 [0022] (4) A method of manufacturing a compound semiconductor device by application of the assembly jig, was able to achieve a cost reduction through mass production so as batch processing of the wafer is possible.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の実施例1に用いる複合半導体装置組立て治具とこれを使った製造の主要工程における複合半導体装置の断面構造図である。 1 is a sectional view of a composite semiconductor device in a composite semiconductor device assembling jig and the main steps of the manufacturing using this used in Example 1 of the present invention.

【図2】本発明の実施例1に用いる複合半導体装置組立て治具を使って形成した半導体素子配列の上面全体図である。 2 is a top overall view of a semiconductor device array formed using the composite semiconductor device assembling jig used in Example 1 of the present invention.

【図3】本発明の実施例1に用いる複合半導体装置組立て治具を使って膜厚の異なる半導体素子を樹脂層に埋め込み形成をした工程における複合半導体装置基板の断面構造図である。 3 is a sectional view of a composite semiconductor device substrate in the step of the composite semiconductor device assembly jig with the film different semiconductor devices thicknesses was buried in the resin layer used in Example 1 of the present invention.

【図4】本発明の実施例1に用いる複合半導体装置のウエーハ製造工程終了における複合半導体装置単体の断面構造図である。 4 is a sectional view of a composite semiconductor device itself in wafer fabrication step is completed composite semiconductor device used in Example 1 of the present invention.

【図5】本発明の実施例2に用いる複合半導体装置の放熱板用組立て治具とこれを使った一製造工程における複合半導体装置の断面構造図である。 5 is a sectional view of a composite semiconductor device in a radiator plate for assembly jig one manufacturing step using this composite semiconductor device used in the second embodiment of the present invention.

【図6】本発明の実施例2に用いる複合半導体装置の放熱板用組立て治具で作った最終製造工程における複合半導体装置単体の断面構造図である。 6 is a sectional view of a composite semiconductor device itself in the final production step made with the heat radiating plate for the assembly jig composite semiconductor device used in the second embodiment of the present invention.

【図7】本発明の実施例3に用いる複合半導体装置用組立て治具の一部分の断面構造図である。 7 is a sectional view of a portion of a composite semiconductor device for assembling jig used in Example 3 of the present invention.

【図8】本発明の実施例3に用いる複合半導体装置用組立て治具の他の一部分の断面構造図である。 8 is a sectional view of another portion of the composite semiconductor device for assembling jig used in Example 3 of the present invention.

【図9】本発明の実施例3に用いる複合半導体装置用組立て治具を使って形成した半導体素子の埋め込み用樹脂層形成工程における複合半導体装置基板の一部分の断面構造図である。 9 is a sectional view of a portion of a composite semiconductor device substrate in the potting layer forming step of a semiconductor element formed using a composite semiconductor device for assembling jig used in Example 3 of the present invention.

【図10】本発明の実施例3に用いる複合半導体装置用組立て治具を使って形成した半導体素子の埋め込み用樹脂層に半導体素子を挿入する概念を示す複合半導体装置の一部分の断面構造図である。 [10] In the cross-sectional structure view of a portion of a composite semiconductor device illustrating the concept of inserting a semiconductor device in a potting layer of a semiconductor element formed using a composite semiconductor device for assembling jig used in Example 3 of the present invention is there.

【図11】本発明の実施例4に用いる複合半導体装置用組立て治具を使って形成した導電層付半導体素子の埋め込み用樹脂層の一部分の断面構造図である。 11 is a sectional view of a portion of the potting layer of the conductive layer with the semiconductor element formed using a composite semiconductor device for assembling jig used in Example 4 of the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

10、50、70、80、110…複合半導体装置用組立て治具、21、41、61、91、101、121… 10,50,70,80,110 ... composite semiconductor device for assembling jig 21,41,61,91,101,121 ...
複合半導体装置用基板、20、40、60、90、10 Composite semiconductor device substrate, 20,40,60,90,10
0、120…製造途中の複合半導体装置、74、76、 0,120 ... manufacture the middle of the complex semiconductor devices, 74 and 76,
77、84、87…複合半導体装置用組立て治具の凸部、4、4A、4B、24A、24B…半導体素子、2 77,84,87 ... convex portion of the composite semiconductor device assembly jig, 4, 4A, 4B, 24A, 24B ... semiconductor device, 2
2、42、62、92、102、122…複合半導体装置基板上の樹脂層凹部、43、116、126…導電層。 2,42,62,92,102,122 ... composite semiconductor device resin layer recesses on the substrate, 43,116,126 ... conductive layer.

フロントページの続き (72)発明者 山▲崎▼ 松夫 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 岡部 寛 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 高橋 昭雄 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 Of the front page Continued (72) inventor mountain ▲ Saki ▼ Matsuo Tokyo Kokubunji Higashikoigakubo 1-chome 280 address Hitachi, Ltd. center within the Institute (72) inventor Hiroshi Okabe Tokyo Kokubunji Higashikoigakubo 1-chome 280 address Hitachi, Ltd. in the central Research Institute (72) inventor Akio Takahashi Hitachi City, Ibaraki Prefecture Omika-cho, seven chome No. 1 Co., Ltd. Hitachi, Ltd. Hitachi within the Institute

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】複数個の半導体素子を接着してなる組立て治具により、上記半導体素子を複合半導体装置用基板に樹脂により固定する工程と、樹脂によってこの表面を平坦にする工程と、上記組立て治具の基板を複合半導体装置用基板から取り外す工程を有することを特徴とした複合半導体装置の製造方法。 The method according to claim 1] made by bonding a plurality of semiconductor elements assembly fixture, and fixing the resin the semiconductor element to the composite semiconductor device substrate, a step of flattening the surface by resin, the assembly method for manufacturing a composite semiconductor device comprising the step of removing the substrate jig from the composite semiconductor device substrate.
  2. 【請求項2】複数個の放熱板を接着してなる組立て治具により、フェイスダウンの組み立てからなる複合半導体装置用基板の半導体素子の裏面に上記放熱板を樹脂により固定する工程と、組立て治具の基板を複合半導体装置用基板から取り外す工程と有することを特徴とした複合半導体装置の製造方法。 By 2. A formed by bonding a plurality of heat radiating plate assembly fixture, comprising the steps of the heat radiating plate on the back surface of the semiconductor element of the composite semiconductor device substrate made of the assembly of the face-down fixed by the resin, the assembly jigs method for manufacturing a composite semiconductor device, comprising the step of removing the substrate of the sushi from the composite semiconductor device substrate.
  3. 【請求項3】複数個の凸型形状をもつ組立て治具により、複合半導体装置用基板上に置かれた樹脂に上記組み立て治具の形状を加圧によって形成する工程と、組立て治具を複合半導体装置用基板から取り外す工程と、複合半導体装置の樹脂からなる複数個の凹型形状に複数個の半導体素子を挿入する工程と、樹脂によりこの表面を平坦にする工程と有することを特徴とした複合半導体装置の製造方法。 By wherein assembling jig having a plurality of convex shape, and forming the shape of the pressure of the assembly jig to the resin placed in the composite semiconductor device substrate, the assembly jig composite a step of removing from the substrate for a semiconductor device, and characterized by comprising the steps of: inserting a plurality of semiconductor elements into a plurality of concave shape made of a resin composite semiconductor device, the step of flattening the surface of a resin composite the method of manufacturing a semiconductor device.
JP6245196A 1996-03-19 1996-03-19 Method for manufacturing composite semiconductor device Granted JPH09260581A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6245196A JPH09260581A (en) 1996-03-19 1996-03-19 Method for manufacturing composite semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6245196A JPH09260581A (en) 1996-03-19 1996-03-19 Method for manufacturing composite semiconductor device

Publications (1)

Publication Number Publication Date
JPH09260581A true true JPH09260581A (en) 1997-10-03

Family

ID=13200592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6245196A Granted JPH09260581A (en) 1996-03-19 1996-03-19 Method for manufacturing composite semiconductor device

Country Status (1)

Country Link
JP (1) JPH09260581A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10304777A1 (en) * 2003-02-05 2004-08-19 Infineon Technologies Ag A process for producing a chip benefits by means of a heat and pressure process using a thermoplastic material
US6836025B2 (en) 2002-05-31 2004-12-28 Fujitsu Limited Semiconductor device configured to be surface mountable
JP2007214545A (en) * 2006-01-10 2007-08-23 Semiconductor Energy Lab Co Ltd Semiconductor device, method for manufacturing therefor, and rfid tag
JP2013016842A (en) * 2012-09-07 2013-01-24 Shinko Electric Ind Co Ltd Semiconductor package
US8404525B2 (en) 2006-01-10 2013-03-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method of semiconductor device, and RFID tag
US8835221B2 (en) 2001-12-31 2014-09-16 Qualcomm Incorporated Integrated chip package structure using ceramic substrate and method of manufacturing the same
US9030029B2 (en) * 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate
JPWO2013179765A1 (en) * 2012-05-30 2016-01-18 オリンパス株式会社 Method of manufacturing a method of manufacturing a semiconductor device and the imaging apparatus
JPWO2013179767A1 (en) * 2012-05-30 2016-01-18 オリンパス株式会社 Method of manufacturing a method of manufacturing a semiconductor device and the imaging apparatus

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8835221B2 (en) 2001-12-31 2014-09-16 Qualcomm Incorporated Integrated chip package structure using ceramic substrate and method of manufacturing the same
US9030029B2 (en) * 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate
US9136246B2 (en) 2001-12-31 2015-09-15 Qualcomm Incorporated Integrated chip package structure using silicon substrate and method of manufacturing the same
US6836025B2 (en) 2002-05-31 2004-12-28 Fujitsu Limited Semiconductor device configured to be surface mountable
DE10304777A1 (en) * 2003-02-05 2004-08-19 Infineon Technologies Ag A process for producing a chip benefits by means of a heat and pressure process using a thermoplastic material
DE10304777B4 (en) * 2003-02-05 2006-11-23 Infineon Technologies Ag A process for producing a chip benefits by means of a heat and pressure process using a thermoplastic material and apparatus for carrying out the method
JP2007214545A (en) * 2006-01-10 2007-08-23 Semiconductor Energy Lab Co Ltd Semiconductor device, method for manufacturing therefor, and rfid tag
US8404525B2 (en) 2006-01-10 2013-03-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method of semiconductor device, and RFID tag
JPWO2013179767A1 (en) * 2012-05-30 2016-01-18 オリンパス株式会社 Method of manufacturing a method of manufacturing a semiconductor device and the imaging apparatus
JPWO2013179765A1 (en) * 2012-05-30 2016-01-18 オリンパス株式会社 Method of manufacturing a method of manufacturing a semiconductor device and the imaging apparatus
US9698195B2 (en) 2012-05-30 2017-07-04 Olympus Corporation Method for producing image pickup apparatus and method for producing semiconductor apparatus
JP2013016842A (en) * 2012-09-07 2013-01-24 Shinko Electric Ind Co Ltd Semiconductor package

Similar Documents

Publication Publication Date Title
US5481133A (en) Three-dimensional multichip package
US7312521B2 (en) Semiconductor device with holding member
US6853060B1 (en) Semiconductor package using a printed circuit board and a method of manufacturing the same
US5789278A (en) Method for fabricating chip modules
US5274270A (en) Multichip module having SiO2 insulating layer
US6306680B1 (en) Power overlay chip scale packages for discrete power devices
US6770971B2 (en) Semiconductor device and method of fabricating the same
US6836025B2 (en) Semiconductor device configured to be surface mountable
US5134539A (en) Multichip module having integral decoupling capacitor
US6399897B1 (en) Multi-layer wiring substrate
US6730997B2 (en) Method of transferring ultra-thin substrates and application of the method to the manufacture of a multi-layered thin film device
US20010020739A1 (en) Flip chip type semiconductor device and method for manufacturing the same
US4070230A (en) Semiconductor component with dielectric carrier and its manufacture
US6717252B2 (en) Semiconductor device
US5986338A (en) Assembly of semiconductor device
US20100013101A1 (en) Method for Manufacturing a Multichip Module Assembly
US6603191B2 (en) Semiconductor device and method of manufacturing the same
US3903590A (en) Multiple chip integrated circuits and method of manufacturing the same
US3757175A (en) Tor chips mounted on a single substrate composite integrated circuits with coplnaar connections to semiconduc
US7425464B2 (en) Semiconductor device packaging
US4466181A (en) Method for mounting conjoined devices
US5221642A (en) Lead-on-chip integrated circuit fabrication method
US5866952A (en) High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate
US7202107B2 (en) Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method
US5448450A (en) Lead-on-chip integrated circuit apparatus