JPS62285432A - Micro formation of electric contact material - Google Patents

Micro formation of electric contact material

Info

Publication number
JPS62285432A
JPS62285432A JP61128656A JP12865686A JPS62285432A JP S62285432 A JPS62285432 A JP S62285432A JP 61128656 A JP61128656 A JP 61128656A JP 12865686 A JP12865686 A JP 12865686A JP S62285432 A JPS62285432 A JP S62285432A
Authority
JP
Japan
Prior art keywords
conductive adhesive
electrodes
fine
film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61128656A
Other languages
Japanese (ja)
Inventor
Yoshihiro Bessho
芳宏 別所
Yasuhiko Horio
泰彦 堀尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61128656A priority Critical patent/JPS62285432A/en
Publication of JPS62285432A publication Critical patent/JPS62285432A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Abstract

PURPOSE:To facilitate applying conductive contact material to a group of electrodes on a substrate only by a method wherein surface inactive photopolymer layers are formed on the conductive adhesive surface of a film with conductive adhesive except the parts corresponding to a group of fine terminal electrodes. CONSTITUTION:A sheet with conductive adhesive is composed of a carrier film 1 and heat reactivating conductive adhesive 2 applied to the carrier film 1. The whole surface of the sheet is coated with photoresist 3. Then the resist 3 is exposed and developed by photolithography so as to remove the parts of the resist 3 corresponding to transparent terminal electrodes 5 of a group of electrodes 5 formed on a glass substrate 4. After that, the resist 3 is made to face the substrate 4 on which the electrodes 5 are formed, which is prepared separately, and subjected to thermocompression bonding by hot rolls 6. Then, if the film 1 is removed, the adhesive 2 is transcribed precisely onto the electrodes 5 only. With this constitution, conductive material for electric contact can be applied to terminal electrodes which are formed with extra-fineness and extra high density selectively and precisely.

Description

【発明の詳細な説明】 3、発明の詳細な説明 産業上の利用分野 本発明は、ICチップに代表されるチップ状の電子部品
を基板、上の端子電極群と接続するために、電気的接続
材料を基板上の端子電極上のみに正確に形成する電気的
接読材料のマイクロ形成方法に関するものである。
Detailed Description of the Invention 3. Detailed Description of the Invention Industrial Field of Application The present invention provides an electrical method for connecting a chip-shaped electronic component, typified by an IC chip, to a group of terminal electrodes on a substrate. The present invention relates to a micro-forming method of electrical readout material in which connecting material is precisely formed only on terminal electrodes on a substrate.

従来の技術 従来、電子部品の接’4a端子と基板上の回路パターン
端子との接続には半田付けがよく利用されていたが、近
年たとえばICフラットパッケージ等の小型化と、接続
端子の増加により、接vt端子間、いわゆるピッチ間隔
が次第に狭くなり従来の半田付は技術で対処することが
次第に困難になってきた。また、最近では電卓、電子時
計あるいは液晶ディスプレイ等にあっては、裸のICチ
ップをガラス基板上の電極に直付けして実装面積の効率
的使用を図ろうとする動きがあり、半田付けに代わる有
効かつ微細な電気的接続手段が強く望まれている。裸の
ICチップをガラス基板の透明電極と電気的に接続する
方法としては、たとえば特公昭51−114439号公
報に示されているように、粒径1粒子形状、配合量等を
適宜調節した種々の金属粉末を熱硬化性樹脂中に均一に
分散させて導電性接着剤を得、これをガラス電極上−面
に塗布したのち、ICチップのバンブと、透明端子電極
とを一致させたのち圧接して導電性接着剤を硬化させる
ことにより、バンブ部分にのみ導電性を発現させて、電
気的接続する方法が提案されている。
Conventional technology In the past, soldering was often used to connect the 4A terminals of electronic components and the circuit pattern terminals on the board, but in recent years, with the miniaturization of IC flat packages and the increase in the number of connection terminals, soldering has become increasingly popular. , the so-called pitch interval between the contact and VT terminals has become progressively narrower, and it has become increasingly difficult to handle conventional soldering techniques. In addition, recently, in the case of calculators, electronic watches, liquid crystal displays, etc., there has been a movement to try to use the mounting area more efficiently by directly attaching bare IC chips to electrodes on glass substrates, replacing soldering. Effective and fine electrical connection means are highly desired. As a method for electrically connecting a bare IC chip to a transparent electrode on a glass substrate, there are various methods in which the particle size, particle shape, blending amount, etc. are appropriately adjusted, as shown in Japanese Patent Publication No. 51-114439. A conductive adhesive is obtained by uniformly dispersing metal powder in a thermosetting resin, and this is applied to the top surface of the glass electrode.The bumps of the IC chip are aligned with the transparent terminal electrodes, and then pressure bonded. A method has been proposed in which electrical connection is achieved by curing the conductive adhesive to make only the bump portions conductive.

発明が解決しようとする問題点 しかしながら斯かる方法においては、電極が微細になり
、また、電極密度が高くなればなる程、隣接する透明端
子電極間あるいはチップ上の電極同志の電流リークが生
じやすいものであった。この電流リークを避けるために
は、透明端子電極群上のみへ、従来技術のスクリーン印
刷法を用いて選択的に導電性接着剤を印刷する方法も考
えられるが、ICチップの直付けを行なうために、透明
端子電極群が、ICチップのパッド状に100μm口、
200μmピンチで形成されている現状では、従来の印
刷技術ではとても不可能に近いと考えられる。
Problems to be Solved by the Invention However, in such a method, the finer the electrodes and the higher the electrode density, the more likely current leakage occurs between adjacent transparent terminal electrodes or between electrodes on a chip. It was something. In order to avoid this current leak, it is possible to selectively print a conductive adhesive only on the transparent terminal electrode group using the conventional screen printing method, but since the IC chip is directly attached, A group of transparent terminal electrodes is formed into a 100 μm opening in the pad shape of an IC chip.
At present, it is considered that it is almost impossible to form with a 200 μm pinch using conventional printing technology.

本発明は上記の問題点に鑑みてなされたものであり、そ
の目的とする所は微細かつ密に電子部品の電極パッドと
基板上の電極群とを信頼性良く直付けするために、基板
上の電極群、あるいは電子部品、たとえばICチップの
電極パッド上のみに導電性接続材料を信頼性良く形成し
ようとすることにある。
The present invention has been made in view of the above-mentioned problems, and its purpose is to directly connect the electrode pads of electronic components and the electrode group on the board with high reliability in a fine and dense manner. The object of the present invention is to form a conductive connecting material with high reliability only on electrode groups of electronic components, or electrode pads of electronic components, such as IC chips.

問題点を解決するための手段 本発明は上記の問題点を解決するため、キャリアフィル
ム上に塗工した導電性接着剤付フィルムの導電性接着剤
面に表面非活性なフォトポリマー層を形成したのち、微
細ピッチ、微細端子電極が形成されている基板の微細端
子電極群に対応するフォトポリマーのみを、フォトリソ
グラフィー技術により除去したのち、別に用意した前記
微細ピッチ、微細端子電極が形成されている基板の微細
端子電極群を含む一面を、導電性接着剤付フィルムのフ
ォトポリマー層が形成された面に合わせ、熱圧着する。
Means for Solving the Problems In order to solve the above problems, the present invention forms a surface-inactive photopolymer layer on the conductive adhesive surface of a conductive adhesive film coated on a carrier film. After that, only the photopolymer corresponding to the fine terminal electrode group of the substrate on which the fine pitch and fine terminal electrodes are formed is removed by photolithography technology, and then the separately prepared fine pitch and fine terminal electrodes are formed. One surface of the substrate containing the fine terminal electrode group is aligned with the surface of the conductive adhesive-attached film on which the photopolymer layer is formed, and bonded by thermocompression.

しかる後に導電性接着剤付フィルムを#I#して微細端
子電極群上のみに導電接着剤を転写することを特徴とし
て電気的接続材料のマイクロ形成を実現しようとするも
のである。
Thereafter, a film with a conductive adhesive is applied to #I#, and the conductive adhesive is transferred only onto a group of fine terminal electrodes, thereby realizing micro-formation of an electrical connection material.

作用 しかして本発明の上記した方法によれば、導電性接着剤
付フィルムの導電性接着剤面には微細端子電極群に対応
する部分以外は表面非活性なフォトポリマー層が形成さ
れているので、導電性接着剤付フィルムを微細ピンチ、
微細端子電極が形成されている基板に熱圧着しても微細
端子電極群以外には転写されない、またフォトポリマー
を用いることにより微細でかつ密な転写が可能となり、
転写された導電性接着剤がそれぞれ独立して存在するの
で隣接する電極間で電流リークのない接続が可能となる
Function: According to the above-described method of the present invention, a photopolymer layer is formed on the conductive adhesive surface of the conductive adhesive-attached film, the surface of which is inactive except for the portion corresponding to the fine terminal electrode group. , micro-pinch the film with conductive adhesive,
Even if it is thermocompressed to a substrate on which fine terminal electrodes are formed, it will not be transferred to anything other than the fine terminal electrode group, and by using a photopolymer, fine and dense transfer is possible.
Since the transferred conductive adhesives exist independently, connection without current leakage is possible between adjacent electrodes.

実施例 以下、本発明の一実施例の電気的接続材料のマイクロ形
成方法について図面に基づいて詳細に説明する。
EXAMPLE Hereinafter, a method for micro-forming an electrical connection material according to an example of the present invention will be described in detail with reference to the drawings.

第1図から第5図は本発明の第1の実施例を示す工程断
面図であり、第6図から第11図は本発明の第2の実施
例を示す工程断面図である。また、第12図、第13図
は本発明の電気的接続材料のマイクロ形成方法を用いて
ICチップを基板上に実装した時の断面図を示す。
1 to 5 are process sectional views showing a first embodiment of the invention, and FIGS. 6 to 11 are process sectional views showing a second embodiment of the invention. Further, FIGS. 12 and 13 show cross-sectional views when an IC chip is mounted on a substrate using the micro-forming method of electrical connection material of the present invention.

図においてlはキャリアフィルム、2は熱再活性導電性
接着剤、3は表面非活性なフォトレジスト、4はガラス
基板、5は透明端子電極(ITO電極) 、6は熱ロー
ル、7はシリコンウェハ、8はICチップの電極パッド
、9はICチップである。
In the figure, l is a carrier film, 2 is a heat-reactivated conductive adhesive, 3 is a surface-inactive photoresist, 4 is a glass substrate, 5 is a transparent terminal electrode (ITO electrode), 6 is a hot roll, and 7 is a silicon wafer. , 8 is an electrode pad of an IC chip, and 9 is an IC chip.

本発明の第1の実施例では、まず第1図に示すようなキ
ャリアフィルム1上に熱再活性導電性接着剤2を20〜
30μm厚形成した導電性接着剤付シート全面に、第2
図に示すような表面非活性のフォトレジスト3をコーテ
ィングする。この時に用いるフォトレジスト3は、たと
えばシリコーン樹脂系のように表面非活性であり、その
−例としてKJR−803O3(信越シリコーン株式会
社製)がある。しかしシリコーン樹脂系に限定する必要
はなく、表面非活性なフォトレジスト3であれば他の樹
脂系でも差し仕えない。
In a first embodiment of the present invention, a heat reactivable conductive adhesive 2 is first applied on a carrier film 1 as shown in FIG.
A second layer was applied to the entire surface of the sheet with conductive adhesive formed to a thickness of 30 μm.
The surface is coated with a non-active photoresist 3 as shown in the figure. The photoresist 3 used at this time is surface-inactive, such as silicone resin, and an example thereof is KJR-803O3 (manufactured by Shin-Etsu Silicone Co., Ltd.). However, it is not necessary to limit it to a silicone resin type, and other resin types can be used as long as the photoresist 3 is surface-inactive.

次に第3図に示すように、フォトリソグラフィー技術を
用いて、フォトレジスト3を露光、現像することにより
、たとえば200μmピッチ、100μm口のTTOt
極群が形成されたガラス基板lのITO電極5に対応す
るフォトレジスト3を除去する。その後、第4図に示し
たように、別に用意された前記ITO電極5が形成され
たガラス基板1を、前記、フォトレジスト3面と対向さ
せ熱ロール6を用いて熱圧着する。その後、第5図に示
すようにキャリアフィルム1を剥すと、ITO電極5上
のみに熱再活性導電性接着剤2がマイクロ転写される。
Next, as shown in FIG. 3, by exposing and developing the photoresist 3 using photolithography technology, for example, TTOt with a pitch of 200 μm and a width of 100 μm is formed.
The photoresist 3 corresponding to the ITO electrode 5 of the glass substrate l on which the electrode group is formed is removed. Thereafter, as shown in FIG. 4, a separately prepared glass substrate 1 on which the ITO electrode 5 is formed is placed facing the surface of the photoresist 3 and bonded by thermocompression using a hot roll 6. Thereafter, as shown in FIG. 5, when the carrier film 1 is peeled off, the heat-reactivated conductive adhesive 2 is microtransferred only onto the ITO electrode 5.

また、第2の実施例では、基板の代わりのICチップを
多数個含むシリコンウェハ7上に導電性接着剤をマイク
ロ転写する方法を示しており、その方法として、まず第
6図に示すようなキャリアフィルム1上に熱再活性導電
性接着剤2を20〜30μm厚形成した導電性接着剤付
シートの全面に、第7図に示すように、第1の実施例と
同様に、表面非活性なフォトレジスト3をコーティング
する。次に、第8図に示すようにフォトリソグラフィー
技術を用いて、フォトレジスト3を露光、現像すること
により100μm口のICチップの電極パッド8に対応
するフォトレジスト3を除去する。次いで第9図に示す
ように、ICチップを多数個含むシリコンウェハ7を、
前記、フォトレジスト3面と対向させ熱ロール6を用い
て熱圧着する。その後、第10図に示すようにキャリア
フィルムlを剥すと、ICチップの電極パッド8上のみ
に熱再活性導電性接着剤2がマイクロ転写される。
In addition, the second embodiment shows a method of micro-transferring a conductive adhesive onto a silicon wafer 7 containing a large number of IC chips instead of a substrate. As shown in FIG. 7, the entire surface of a sheet with a conductive adhesive, in which a heat-reactivated conductive adhesive 2 is formed to a thickness of 20 to 30 μm on a carrier film 1, is coated with a surface inactivation layer as in the first embodiment. Coat with photoresist 3. Next, as shown in FIG. 8, the photoresist 3 is exposed and developed using a photolithography technique, thereby removing the photoresist 3 corresponding to the electrode pad 8 of the IC chip having a diameter of 100 μm. Next, as shown in FIG. 9, a silicon wafer 7 containing a large number of IC chips is
The above-mentioned photoresist 3 is placed facing the photoresist 3 and bonded by thermocompression using a hot roll 6. Thereafter, as shown in FIG. 10, when the carrier film 1 is peeled off, the heat-reactivated conductive adhesive 2 is microtransferred only onto the electrode pads 8 of the IC chip.

なお、第1の実施例で得たガラス基板4上の透明端子電
極5の上に形成された熱再活性導電性接着剤2とICチ
ップ9の電極パッド8とを対向させ熱圧着すると、第1
2図に示すようなICチップとガラス基板との接続がで
きる。
Note that when the heat-reactivated conductive adhesive 2 formed on the transparent terminal electrode 5 on the glass substrate 4 obtained in the first example and the electrode pad 8 of the IC chip 9 are faced and thermocompressed, the first 1
The IC chip and the glass substrate can be connected as shown in Figure 2.

また、第2の実施例で得たICチップの電極パッド8上
に熱再活性導電性接着剤2付きのシリコンウェハ7は第
11図に示すように点線部を切断して個別のICチップ
9とし、第13図に示すようにガラス基板と接続するこ
とができる。
In addition, the silicon wafer 7 with the thermally reactivated conductive adhesive 2 on the electrode pad 8 of the IC chip obtained in the second example was cut along the dotted line as shown in FIG. 11 to form individual IC chips 9. It can be connected to a glass substrate as shown in FIG.

発明の効果 以上に説明したように、本発明の電気的接続材料のマイ
クロ形成方法によれば、基板上あるいは電子部品、たと
えばICチップの電極部に導電性材料を転写により形成
できるので、従来、印刷では不可能だった、超微細で超
密に形成された端子電極群上に選択的に精度よく、電気
接続用の導電材料を形成することができ、ICチップの
ガラス基板上の1を掻接続に限らず各種基板への各種電
子部品の電気的接続において、半田付は接続が困難な超
微細接続に効果を発揮するので、掻めて実用価債が高い
Effects of the Invention As explained above, according to the method of micro-forming an electrical connection material of the present invention, a conductive material can be formed on a substrate or on an electrode part of an electronic component, such as an IC chip, by transfer. It is possible to selectively and accurately form conductive materials for electrical connections on ultra-fine and ultra-densely formed terminal electrode groups, which was impossible with printing, and it is possible to form conductive materials for electrical connections with high precision by scratching 1 on the glass substrate of an IC chip. Not only in connection but also in the electrical connection of various electronic components to various substrates, soldering is effective for ultra-fine connections that are difficult to connect, so it has a high practical value.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図、第3図、第4図、第5図は第1の実施
例を示す工程断面図、第6図、第7図。 第8図、第9図、第10図、第11図は第2の実施例を
示す工程断面図、また、第12図、第13図はそれぞれ
第1および第2の実施例に基づきICチップを基板上へ
実装した時の断面図である。 1・・・・・・キャリアフィルム、2・・・・・・熱再
活性導電性接着剤、3・・・・・・表面非活性なフォト
レジスト、4・・・・・・ガラス基板、5・・・・・・
透明端子電極(ITOt極) 、6・・・・・・熱ロー
ル、7・・・・・・シリコンウェハ、8・・・・・・I
Cチップの1!掻パツド、9・・・・・・ICチップ。 代理人の氏名 弁理士 中尾敏男 はか1名第1図 第  2   f”l             3・
−&I!D静オ+生rJ7.rlL、ジλト第3図 第5図 第6図 第10図
FIG. 1, FIG. 2, FIG. 3, FIG. 4, and FIG. 5 are process sectional views showing the first embodiment, and FIGS. 6 and 7. 8, 9, 10, and 11 are process cross-sectional views showing the second embodiment, and FIGS. 12 and 13 are IC chips based on the first and second embodiments, respectively. FIG. DESCRIPTION OF SYMBOLS 1... Carrier film, 2... Heat-reactivated conductive adhesive, 3... Surface inactive photoresist, 4... Glass substrate, 5・・・・・・
Transparent terminal electrode (ITOt electrode), 6... Heat roll, 7... Silicon wafer, 8... I
C chip 1! 9...IC chip. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1 2 f”l 3.
-&I! D Shizuo + raw rJ7. Figure 3 Figure 5 Figure 6 Figure 10

Claims (1)

【特許請求の範囲】[Claims]  キャリアフィルム上に塗工した導電性接着剤付フィル
ムの導電性接着剤面に表面非活性なフォトポリマー層を
形成する工程と、微細ピッチ、微細端子電極が形成され
ている基板の微細端子電極群に対応する前記フォトポリ
マーのみをフォトリソグラフィー技術により除去する工
程と、別に用意した、前記微細ピッチ、微細端子電極が
形成されている基板の微細端子電極群を含む一面を、前
記導電性接着剤付フィルムのフォトポリマー層が形成さ
れた面に合わせ、熱圧着する工程と、前記導電性接着剤
付フィルムを剥離して微細端子電極群上のみに導電性接
着剤を転写する工程とを含むことを特徴とする電気的接
続材料のマイクロ形成方法。
The process of forming a surface-inactive photopolymer layer on the conductive adhesive surface of the conductive adhesive film coated on the carrier film, and the fine terminal electrode group of the substrate on which the fine pitch and fine terminal electrodes are formed. A step of removing only the photopolymer corresponding to the above using a photolithography technique, and applying the conductive adhesive to one side of the separately prepared substrate on which the fine pitch and fine terminal electrodes are formed, including the fine terminal electrode group. The process includes the steps of thermally pressing the film to the surface on which the photopolymer layer is formed, and peeling off the conductive adhesive-attached film and transferring the conductive adhesive only onto the fine terminal electrode group. Characteristic micro-forming method for electrical connection materials.
JP61128656A 1986-06-03 1986-06-03 Micro formation of electric contact material Pending JPS62285432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61128656A JPS62285432A (en) 1986-06-03 1986-06-03 Micro formation of electric contact material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61128656A JPS62285432A (en) 1986-06-03 1986-06-03 Micro formation of electric contact material

Publications (1)

Publication Number Publication Date
JPS62285432A true JPS62285432A (en) 1987-12-11

Family

ID=14990201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61128656A Pending JPS62285432A (en) 1986-06-03 1986-06-03 Micro formation of electric contact material

Country Status (1)

Country Link
JP (1) JPS62285432A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0276224A (en) * 1988-09-10 1990-03-15 Fujitsu Ltd Manufacture of compound semiconductor device
US5286335A (en) * 1992-04-08 1994-02-15 Georgia Tech Research Corporation Processes for lift-off and deposition of thin film materials
US5401983A (en) * 1992-04-08 1995-03-28 Georgia Tech Research Corporation Processes for lift-off of thin film materials or devices for fabricating three dimensional integrated circuits, optical detectors, and micromechanical devices
US5465009A (en) * 1992-04-08 1995-11-07 Georgia Tech Research Corporation Processes and apparatus for lift-off and bonding of materials and devices
JP2007305160A (en) * 2007-08-10 2007-11-22 Dainippon Printing Co Ltd Non-contact type ic card and base body for non-contact type ic card

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0276224A (en) * 1988-09-10 1990-03-15 Fujitsu Ltd Manufacture of compound semiconductor device
US5286335A (en) * 1992-04-08 1994-02-15 Georgia Tech Research Corporation Processes for lift-off and deposition of thin film materials
US5401983A (en) * 1992-04-08 1995-03-28 Georgia Tech Research Corporation Processes for lift-off of thin film materials or devices for fabricating three dimensional integrated circuits, optical detectors, and micromechanical devices
US5465009A (en) * 1992-04-08 1995-11-07 Georgia Tech Research Corporation Processes and apparatus for lift-off and bonding of materials and devices
JP2007305160A (en) * 2007-08-10 2007-11-22 Dainippon Printing Co Ltd Non-contact type ic card and base body for non-contact type ic card
JP4602382B2 (en) * 2007-08-10 2010-12-22 大日本印刷株式会社 Non-contact type IC card, base for non-contact type IC card

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