JP2600161B2 - Substrate for transfer bump - Google Patents
Substrate for transfer bumpInfo
- Publication number
- JP2600161B2 JP2600161B2 JP62030349A JP3034987A JP2600161B2 JP 2600161 B2 JP2600161 B2 JP 2600161B2 JP 62030349 A JP62030349 A JP 62030349A JP 3034987 A JP3034987 A JP 3034987A JP 2600161 B2 JP2600161 B2 JP 2600161B2
- Authority
- JP
- Japan
- Prior art keywords
- bump
- conductor
- comb
- substrate
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体素子の電極とフィルムリードを接合す
る際に、フィルムリード側にバンプ（金属突起）を形成
するいわゆる転写バンプ実装方式の前記バンプを形成す
る転写バンプ用基板に関するもので、基板の構成が簡単
でバンプの剥離性の高い基板を提供するものである。The present invention relates to a so-called transfer bump mounting method in which a bump (metal projection) is formed on a film lead side when an electrode of a semiconductor element is bonded to a film lead. The present invention relates to a substrate for a transfer bump, and provides a substrate having a simple structure and high releasability of a bump.
従来の技術 転写バンプ実装方式は、特開昭57−152147号公報にも
開示されているように、あらかじめバンプを別の基板上
に電解めっき法で形成しておき、このバンプとフィルム
リードとを位置合せし、加圧，加熱して前記バンプをフ
ィルムリード側に転写，接合し、基板上からバンプを剥
離する方法である。この時、例えばバンプがAuで構成さ
れ、Cuで形成したフィルムリード上にSnがめっき処理さ
れておれば、Au・Snの合金でバンプとフィルムリードと
は接合される事になる。2. Description of the Related Art As disclosed in Japanese Patent Application Laid-Open No. 57-152147, a transfer bump mounting method is to previously form a bump on another substrate by an electrolytic plating method and to connect the bump and a film lead. In this method, the bumps are transferred to and bonded to the film lead side by aligning, pressing and heating, and the bumps are peeled off from the substrate. At this time, if, for example, the bumps are made of Au and Sn is plated on the film leads formed of Cu, the bumps and the film leads will be joined with an alloy of Au and Sn.
次いで、前記バンプが転写，接合されたフィルムリー
ドのバンプと半導体素子の電極とを位置合せし、加圧，
加熱する。これによって、フィルムリードは半導体素子
の電極と前記バンプを介して接合されるものである。こ
の時、半導体素子の電極がアルミニウムで構成されるな
らば、バンプと半導体素子の電極とはAu・Alの合金で接
合される。Next, the bumps of the film lead to which the bumps have been transferred and bonded are aligned with the electrodes of the semiconductor element,
Heat. Thereby, the film lead is bonded to the electrode of the semiconductor element via the bump. At this time, if the electrode of the semiconductor element is made of aluminum, the bump and the electrode of the semiconductor element are joined with an Au / Al alloy.
従来、この様な転写バンプ実装方式に用いる基板１は
第５図に示す様に、耐熱性ガラス板２上に全面にめっき
用の電極となりかつめっきで形成するバンプが付着する
導電層３を形成する。ついで導電層３上にSiO2,Si3N4あ
るいは有機膜等のめっき用のマスクとなる絶縁膜４を設
け、半導体素子の電極に対応した位置に開孔部５を設け
た構造である。バンプ６は開孔部５の導電層３上に電解
めっき法により、形成される。Conventionally, as shown in FIG. 5, a substrate 1 used in such a transfer bump mounting method is formed on a heat-resistant glass plate 2 by forming a conductive layer 3 on the entire surface which serves as an electrode for plating and to which a bump formed by plating adheres. I do. Next, an insulating film 4 serving as a plating mask such as SiO 2 , Si 3 N 4 or an organic film is provided on the conductive layer 3, and an opening 5 is provided at a position corresponding to the electrode of the semiconductor element. The bump 6 is formed on the conductive layer 3 in the opening 5 by an electrolytic plating method.
発明が解決しようとする問題点 この様なバンプ形成用基板にあっては、導電層３が基
板１の全面に形成されているために、絶縁膜４にピンホ
ールやクラックが発生していると、めっき時に、ここに
も不必要なバンプが形成される。このため、所定の電流
密度でめっき処理を行なってもバンプの高さにバラツキ
が発生し、接合の安定性を失なわしめたり、あるいは、
これらピンホールやクラック7,8にも不要なバンプが形
成され、これが開孔部５の近傍に発生する。これら不必
要なバンプもフィルムリード側に転写されるためこれに
より半導体素子を損傷したりあるいは電極間の短絡をま
ねくものであった。Problems to be Solved by the Invention In such a substrate for forming a bump, since the conductive layer 3 is formed on the entire surface of the substrate 1, if the insulating film 4 has pinholes or cracks, At the time of plating, unnecessary bumps are also formed here. For this reason, even if the plating process is performed at a predetermined current density, the height of the bumps varies, and the bonding stability is lost, or
Unnecessary bumps are also formed on these pinholes and cracks 7 and 8, which occur near the opening 5. These unnecessary bumps are also transferred to the film lead side, thereby damaging the semiconductor element or causing a short circuit between the electrodes.
また、絶縁膜の開孔部５は数千個を設ける必要がある
ため、開孔部５の中には形状が変形したものも発生し、
使用できない開孔部が発生したり、あるいはバンプのフ
ィルムリードへの転写時に開孔部の周縁を損傷してしま
い、これもまた使用できない開孔部を発生させ、バンプ
の形成歩留りの低下が生じていた。Further, since it is necessary to provide thousands of holes 5 in the insulating film, some of the holes 5 are deformed in shape.
Unusable holes may be generated, or the periphery of the holes may be damaged during transfer of the bumps to the film leads, which may also cause unusable holes and reduce the bump formation yield. I was
問題点を解決するための手段 本発明の転写バンプ用基板は、絶縁性基板上に半導体
チップの電極に対応し、外周から前記電極に対応する位
置まで延在した櫛状の導体と、前記絶縁性基板および前
記導体上に形成され、前記櫛状の導体の一部の領域のみ
を露出させた絶縁体層を有し、前記櫛状導体の露出領域
に電解めっき法により形成した金属突起を剥離するもの
である。Means for Solving the Problems The transfer bump substrate of the present invention has a comb-shaped conductor corresponding to an electrode of a semiconductor chip on an insulating substrate and extending from an outer periphery to a position corresponding to the electrode; An insulating layer formed on the conductive substrate and the conductor, exposing only a part of the comb-shaped conductor, and peeling off metal projections formed on the exposed region of the comb-shaped conductor by electrolytic plating. Is what you do.
作 用 本発明によれば、導体が櫛状をなし、かつ絶縁体層に
より導体の一部を露出する構造とし、この部分にバンプ
を形成するものであるため、従来のごとく全面に導体が
なく、ほぼバンプ形成に必要な部分にのみ導体を形成で
き、絶縁膜にピンホールやクラックが発生してもその下
には導体がない部分が多く、不必要なバンプの発生を最
低限に押さえることが可能となる。また絶縁膜の開孔を
導体の辺を横断する如く形成すると、バンプを形成し、
これをフィルムリードへ転写接合しても、開孔部を損傷
する割合が著じるしく小さくなる。According to the present invention, the conductor has a structure in which the conductor has a comb shape and a part of the conductor is exposed by the insulator layer, and the bump is formed in this part. The conductor can be formed almost only in the area necessary for bump formation, and even if pinholes or cracks occur in the insulating film, there are many parts without conductors underneath, minimizing the occurrence of unnecessary bumps Becomes possible. Also, when the opening of the insulating film is formed so as to cross the side of the conductor, a bump is formed,
Even when this is transferred and bonded to a film lead, the rate of damage to the opening is significantly reduced.
実施例 第１図で本発明の実施例を説明す。Embodiment An embodiment of the present invention will be described with reference to FIG.
耐熱性ガラスあるいはセラミック有機材で構成された
基台２上には、バンプを形成する領域に櫛形状に突出し
た導電層11が形成され、この上に付着された絶縁膜12の
開孔13は、□字形状の櫛形状の導電層11の２辺を横断す
る如く形成される。バンプが形成される領域（開孔部）
は、絶縁膜12の開孔13の部分に露出した導電層11Aの部
分である。導電層11はTi−Pt,Ti−PdあるいはITO等で形
成され隣接する開孔部13と一体に接がっているものであ
る。この様な構成にあっては、バンプを形成するために
必要な開孔部13以外に形成される導電層部分は少なく、
さらに開孔部13で囲まれた内側の領域に存在する導電層
部分は著じるしく小さいので、導電層11上の絶縁膜12の
ピンホールかクラックによる不要バンプの発生を極端に
小さく押えることができる。実際の実験結果では、従
来、ピンホールが原因で使用できないバンプが約8.5％
発生していたが、第１図の構成では0.023％に減少し
た。またバンプの高さの変動も従来の構成であると30μ
ｍ厚に対し±2.7μｍの変動があったがこの構成では±
0.85μｍになり、安定したバンプ14を形成できた。On the base 2 made of heat-resistant glass or ceramic organic material, a conductive layer 11 protruding in a comb shape is formed in a region where a bump is formed, and an opening 13 of an insulating film 12 attached thereon is formed. , Are formed so as to cross two sides of the conductive layer 11 having a □ -shaped comb shape. Area where bumps are formed (opening)
Is a portion of the conductive layer 11A exposed at the portion of the opening 13 of the insulating film 12. The conductive layer 11 is made of Ti-Pt, Ti-Pd, ITO, or the like, and is integrally connected to the adjacent opening 13. In such a configuration, the conductive layer portion formed other than the opening 13 necessary for forming the bump is small,
Furthermore, since the conductive layer portion existing in the inner region surrounded by the opening 13 is extremely small, the generation of unnecessary bumps due to pinholes or cracks in the insulating film 12 on the conductive layer 11 must be extremely small. Can be. According to actual experimental results, bumps that cannot be used due to pinholes are about 8.5%
Although it occurred, it decreased to 0.023% in the configuration of FIG. Also, the variation in bump height is 30μ with the conventional configuration.
There was a variation of ± 2.7 μm with respect to the
0.85 μm, and a stable bump 14 could be formed.
第２図に他の実施例を示す。この構成においては、櫛
形状に形成された導電層11の先端部11Bのみが露出する
様に開孔部13を有する絶縁膜12が導電層11上と基台２上
に設けられており、先端部11Bが開孔部13に位置するも
のである。この領域11Bに第２図（ｂ）の如くバンプ14
が電解めっきされるものである。この構成にあっては櫛
形状の導電層11の一辺を絶縁膜12の開孔部13が横断する
ことになり、絶縁膜12の開孔部13のパターン形成も単純
であるから著じるしく容易に製作できる。この構成での
不良バンプの発生は0.011％であった。FIG. 2 shows another embodiment. In this configuration, an insulating film 12 having an opening 13 is provided on the conductive layer 11 and the base 2 so that only the tip 11B of the comb-shaped conductive layer 11 is exposed. The portion 11B is located at the opening 13. In this area 11B, as shown in FIG.
Is to be electroplated. In this configuration, the opening 13 of the insulating film 12 traverses one side of the comb-shaped conductive layer 11, and the pattern formation of the opening 13 of the insulating film 12 is also remarkable because it is simple. Can be easily manufactured. The occurrence of defective bumps in this configuration was 0.011%.
第１図，第２図の両方の構成においては、導電層11の
櫛形状の巾と絶縁膜12の横断する位置がバンプを形成す
るためめっき処理される寸法となる。In both configurations of FIGS. 1 and 2, the width of the comb shape of the conductive layer 11 and the position where the insulating film 12 crosses have dimensions to be plated to form bumps.
また、導電層上の絶縁膜のパターン断面の形状は第３
図に示す如く、導電層11上に設けられた絶縁膜12の断面
は少なくとも傾斜30を有するもので、図中のθは40゜以
上が望ましく、ここに傾斜30を設ける事により、めっき
中に発生するバンプ内の応力を小さくでき、導電層11か
らのバンプ14の剥離を容易ならしめるものである。The shape of the pattern cross section of the insulating film on the conductive layer is the third.
As shown in the figure, the cross section of the insulating film 12 provided on the conductive layer 11 has at least a slope 30. In the figure, θ is desirably 40 ° or more, and by providing the slope 30 here, during plating, The generated stress in the bump can be reduced, and the peeling of the bump 14 from the conductive layer 11 can be facilitated.
第４図の例は、基台２に傾斜を有する凹部2Aを設けた
構造で、この場合のθも40゜以上が望ましいものであ
る。バンプ14は凹部2A上に形成される。FIG. 4 shows an example in which the base 2 is provided with an inclined concave portion 2A. The bump 14 is formed on the recess 2A.
こうしてバンプ作成された基板上に、多数の導体リー
ドを有するフィルムキャリア（図示せず）が移送され、
バンプ14とリードが加熱，加圧されて接合され、リード
の弾性力にてリードにバンプ14が接合された状態でバン
プ14が基板２からはくりされ、しかるのち、バンプ14の
形成されたリードがたとえば半導体素子の電極上に位置
合せされ、バンプ14と半導体素子の電極が加熱加圧され
て接合される。このようにして、フィルムキャリアのリ
ードと半導体素子の電極との接合工程いわゆる転写バン
プ実装が行われる。A film carrier (not shown) having a large number of conductor leads is transferred onto the substrate thus bumped,
The bump 14 and the lead are joined by being heated and pressurized, and the bump 14 is peeled off from the substrate 2 in a state where the bump 14 is joined to the lead by the elastic force of the lead. Thereafter, the lead on which the bump 14 is formed is formed. Are positioned on, for example, an electrode of a semiconductor element, and the bump 14 and the electrode of the semiconductor element are joined by being heated and pressed. In this way, a bonding step between the lead of the film carrier and the electrode of the semiconductor element, that is, the so-called transfer bump mounting is performed.
発明の効果 本発明では、導電層が櫛形状でめっき処理される開
孔部で囲まれる内側領域にほとんど存在しないばかり
か、必要最小限の領域にしか形成していないので、絶縁
膜のピンホールやクラックによる不必要なバンプの形成
がない。このために均一な安定したバンプ形成が歩留り
高くできる。According to the present invention, since the conductive layer hardly exists in the inner region surrounded by the opening to be plated in a comb shape and is formed only in the minimum necessary region, the pinhole of the insulating film is formed. No unnecessary bumps are formed due to cracks or cracks. For this reason, uniform and stable bump formation can be achieved at a high yield.
また、開孔部を形成するための絶縁膜のパターンが
従来５〜30μｍ□の形状のものを多数個形成する必要が
あり、このために、パターンの形状不良が発生する度合
が高かったが、本発明においては絶縁膜の開孔パターン
寸法が大きく、かつ単純なパターンであるため、パター
ンの形状不良が発生せず、簡単にパターン形成を実施で
きるものである。In addition, it is necessary to form a large number of insulating film patterns of 5 to 30 μm square in the related art for forming the opening, and for this reason, the degree of occurrence of pattern shape defects was high, In the present invention, since the size of the opening pattern of the insulating film is large and the pattern is simple, pattern formation does not occur and pattern formation can be easily performed.
導電層上での絶縁膜の横断する辺数が１〜２辺であ
るため、形成されたバンプをフィルムリード側へ剥離転
写する時に、絶縁膜の断面に加わる応力が小さくなるた
め、絶縁膜のパターンが損傷される度合が小さくなり、
転写バンプ用基板の耐久度が著じるしく高まるものであ
る。Since the number of traversing sides of the insulating film on the conductive layer is one or two, when the formed bump is peeled and transferred to the film lead side, the stress applied to the cross section of the insulating film is reduced. The degree to which the pattern is damaged is reduced,
The durability of the transfer bump substrate is significantly increased.
第１図（ａ），第２図（ａ）は本発明の実施例の転写バ
ンプ基板の概略平面図、第１図（ｂ），第２図（ｂ）は
それぞれ第１図（ａ），第２図（ａ）のＩ−Ｉ′,II−I
I′線断面図、第３図，第４図は本発明のさらに他の実
施例でバンプ形成領域の断面図、第５図（ａ）は従来の
同基板の平面図、第５図（ｂ）は第５図（ａ）のＶ−
Ｖ′線断面図である。 ２……絶縁基板、11……導電層、12……絶縁膜、13……
開孔部、14……バンプ。1 (a) and 2 (a) are schematic plan views of a transfer bump substrate according to an embodiment of the present invention, and FIGS. 1 (b) and 2 (b) are FIGS. 1 (a) and 1 (b), respectively. II ', II-I in FIG.
FIGS. 3 and 4 are cross-sectional views of a bump formation region according to still another embodiment of the present invention. FIG. 5 (a) is a plan view of the conventional substrate, and FIG. ) Is V- in FIG. 5 (a).
It is V 'line sectional drawing. 2 ... insulating substrate, 11 ... conductive layer, 12 ... insulating film, 13 ...
Opening, 14 ... bump.
Claims (5)
し、外周から前記電極に対応する位置まで延在した櫛状
の導体と、前記絶縁性基板および前記導体上に形成さ
れ、前記櫛状の導体の一部の領域のみを露出させた絶縁
体層を有し、前記櫛状導体の露出領域に電解めっき法に
より形成した金属突起を剥離するように構成した転写バ
ンプ用基板。A comb-shaped conductor corresponding to an electrode of a semiconductor chip on an insulating substrate and extending from an outer periphery to a position corresponding to the electrode; and a comb-shaped conductor formed on the insulating substrate and the conductor. A transfer bump substrate, comprising: an insulator layer that exposes only a part of a conductor in a shape of a conductor; and a metal bump formed by an electrolytic plating method on an exposed region of the comb-like conductor.
において、導体の一辺もしくは二辺を絶縁体層が覆って
いる特許請求の範囲第１項記載の転写バンプ用基板。2. The transfer bump substrate according to claim 1, wherein one or two sides of the conductor are covered with an insulator layer in an exposed region of the comb-shaped conductor forming the metal protrusion.
特許請求の範囲第１項記載の転写バンプ用基板。3. The transfer bump substrate according to claim 1, wherein the width of the comb-shaped conductor regulates the width of the metal projection.
て、前記絶縁体層の断面が傾斜している特許請求の範囲
第１項記載の転写バンプ用基板。4. The transfer bump substrate according to claim 1, wherein a cross section of the insulator layer is inclined at a boundary between the exposed conductor and the insulator layer.
凹部である特許請求の範囲第１項記載の転写バンプ用基
板。5. The transfer bump substrate according to claim 1, wherein the region where the metal protrusion of the comb-shaped conductor is formed is a concave portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62030349A JP2600161B2 (en) | 1987-02-12 | 1987-02-12 | Substrate for transfer bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62030349A JP2600161B2 (en) | 1987-02-12 | 1987-02-12 | Substrate for transfer bump |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63197349A JPS63197349A (en) | 1988-08-16 |
| JP2600161B2 true JP2600161B2 (en) | 1997-04-16 |
Family
ID=12301369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62030349A Expired - Lifetime JP2600161B2 (en) | 1987-02-12 | 1987-02-12 | Substrate for transfer bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2600161B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07303322A (en) * | 1991-10-21 | 1995-11-14 | Hitachi Cable Ltd | Method for laying cable in trough |
-
1987
- 1987-02-12 JP JP62030349A patent/JP2600161B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63197349A (en) | 1988-08-16 |
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