JPH01238148A - Semiconductor device - Google Patents

Abstract

PURPOSE:To hold the parallelism of a chip with respect to a semiconductor substrate and to improve the connecting strength against a twist or the like by surrounding the periphery of a bump electrode disposed substantially at an equal interval at the center of the chip with a dummy bump wholly in contact with the chip and the substrate. CONSTITUTION:Bump electrodes 2 are so provided at the center of a chip 1 as to connect circuit elements in the chip to wiring conductors of a supporting board at positions occupying the vertexes of regular triangular shapes. Accordingly, the intervals between the adjacent electrodes 2 are substantially equal. Dummy bumps 3 are provided substantially at equal intervals at the peripheral edges of the chip 1 around the electrodes 2, and further surrounded by resin 4. Accordingly, the parallelism between the chip 1 by the bumps 3 and a circuit board 9 is reinforced to improve its strength against a distortion such as a twist, a thermal stress or the like.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an insulating film on a circuit element portion formed on a semiconductor chip in order to mount a semiconductor chip on a support substrate using a wireless bonding method. The present invention relates to a semiconductor device in which a wiring conductor and bumps i and ti are provided.

[Conventional technology]

When a wireless bonding method is used to mount a semiconductor chip on a support substrate using bump electrodes, bump electrodes are placed on pads (not shown) around the chip 1 as shown in Figure 2 for stable support. It is well known that forming 8i2 is catalytic.

[Problem to be solved by the invention]

However, as the area of the chip 1 increases, the maximum distance between the bump electrodes 2 increases, which is caused by the difference in thermal expansion coefficient between the semiconductor material and the supporting substrate material such as ceramic, and the thermal stress during one cycle. As a result, failures such as damage or destruction of the bump electrode connection portion occur, resulting in a disadvantage that the reliability of the semiconductor device is reduced. In order to eliminate this drawback, as described in Japanese Patent Application No. 62-279676 filed by the present applicant, bump electrodes are arranged so that the spacing between the bump electrodes adjacent to the center of the chip is approximately equal. It is proposed to arrange it so that

An object of the present invention is to further improve the reliability of the semiconductor device proposed above.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention provides a semiconductor chip surface bonding method using a wireless bonding method using bump electrodes arranged at the center of one surface of a semiconductor chip with substantially equal spacing between adjacent bump electrodes. In a semiconductor device to which a conductor on the support substrate surface facing the upper conductor is connected, the conductor connected to the conductor is not present on at least one of the semiconductor chip surface and the support 1 & plate surface over the entire periphery of the semiconductor nap. It is assumed that a plurality of dummy bumps are provided that contact the opposing surface and are covered with resin.

[Effect]

For mounting a semiconductor chip, bump electrodes arranged at approximately equal intervals in the center of the chip are surrounded by dummy bumps that contact the chip and the semiconductor substrate over the entire area, thereby maintaining parallelism between the chip and the substrate. The connection strength against twisting etc. is improved. Furthermore, the connection strength is further increased by reinforcing the dummy bumps with resin coating.

〔Example〕

FIG. 1 shows the arrangement of bump electrodes in an embodiment of the present invention,
Bump electrodes 2 are provided at the center of the chip 1 at positions occupying the vertices of an equilateral triangle for connecting each circuit element within the chip to the wiring conductor of the support substrate. Therefore, the distances between adjacent bump electrodes 2 are approximately equal. Dummy bumps 3 are provided at approximately equal intervals on the periphery of the chip 1, surrounding these bump electrodes 2, and are further surrounded by resin 4.

FIG. 3 is an enlarged view of a part of the chip 1, in which low-temperature CVD oxide is formed on the first wiring conductor 61 made of M, which contacts the GM region 11 of the chip 1 at the opening of the oxide film 51. A second wiring conductor 62 is formed through the glabellar insulation 11!52, and is in contact with the first wiring conductor 61 at the opening of the insulation [52]. Insulation II above and between the eyebrows of this second wiring conductor 62
! 52 is covered with a passivation layer made of nitride.
8 and photoetching to provide an opening on the second wiring conductor 62 and near the outer periphery of the chip l. Further Cr
, Cu, and AuM4 are laminated to form the base metal layer 7, patterned by photoetching, solder is deposited on the base metal layer 7 by solder plating, and the ball is softened by heating to about 350°C. A bump electrode 2 and a dummy bump 3 having a slightly larger diameter are formed. The solder adhesion is
It may also be vacuum deposited to a thickness of about 50 mm.

FIG. 4 (al, (bl) shows the mounting process of one embodiment of the present invention, in which the semiconductor chip l is placed facing downward on the wiring support substrate 9 as shown in FIG. 2 or 3. At the time of aL, a preliminary solder layer lO with a thickness that compensates for the difference in height between the dummy bump 3 and the bump electrode 2 is deposited on the wiring of the base Fi9.After this, the solder is reflowed, but the diameter is The small bump electrode 3 melts first and adheres to the preliminary solder layer, and the bump electrode 2 becomes a solder column with a height equal to the distance between the chip 1 and the M plate 9, which is kept constant by the dummy bump 3 with a large diameter. After a while, the dummy bumps 3 melt and the substrate 9 and the outer periphery of the chip 1 are bonded together.

In order to improve the adhesion of the dummy bumps 3, a conductive layer may be provided independently on the Mi9 or the chip 1 at the dummy bump contact portion in advance, and a preliminary solder layer may be provided. for example,
The diameter of bump electrode 2 is 50 mm.

If the In of the dummy bump 3 is 62N, the volume of the dummy bump will be twice that of the bump electrode, and if the heat soaking including the reflow time is constant, the volume will be approximately twice that, so the bump electrode 3 will have an elongated columnar shape as described above. Since the height is long compared to the cross section, the stress due to the difference in thermal expansion coefficient between the chip 1 and the substrate 9 is dispersed, and the connecting portion is not damaged or destroyed.

Furthermore, by covering the dummy bumps 3 with a resin 4 such as epoxy 4JA resin and fixing them as shown in the 4th outlet), the parallel holding of the chip 1 and the wiring board (anti-9) by the dummy bumps 3 is reinforced and twisted. , the strength against distortions such as thermal stress is improved.

〔Effect of the invention〕

According to the present invention, in order to reduce thermal stress due to the difference in thermal expansion coefficient between the P-conductor material and the mounting support substrate material, if the bumps ml are arranged at approximately equal intervals in the center of the chip, no electrodes are provided. By providing dummy bumps around the entire circumference of the chip, the chip and mounting board are fixed not only in the center but also in the periphery, ensuring that they are held parallel to each other.Furthermore, by covering the dummy bumps with resin, The connection strength in the periphery, which is subject to a large thermal stress load, becomes stronger, making a large contribution to improving the reliability of mounting.Also, by making the diameter of the dummy bump formed on the chip larger than the diameter of the bump, the bump electrode It is also possible to form a columnar shape stretched between the chip and the substrate, which makes it possible to disperse stress within the bump electrode and further improve reliability.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor chip according to an embodiment of the present invention, FIG. 2 is a plan view of a conventional semiconductor chip, and FIG. 3 is a sectional view of essential parts of a semiconductor chip according to an embodiment of the present invention before mounting. , FIG. 4 (al, (bl) are sectional views sequentially showing the mounting process of an embodiment of the present invention. l Two-handed conductor chip, 2: bump electrode, 3: dummy bump, 4: resin, 9: wiring board. Representative Patent Attorney Gen. Yamaguchi ') 2ba 2τ (takus1 figure' 7 112 figure

Claims (1)

[Claims] 1) Bump electrodes adjacent to the center of one surface of the semiconductor chip are arranged with approximately equal spacing between the bump electrodes, and the conductor on the surface of the semiconductor chip is bonded to the surface of the support substrate opposite to the surface of the support substrate using a wireless bonding method. In a device to which a conductor is connected, a plurality of surfaces covered with resin contact the opposing surface at a location where there is no conductor connected to the conductor on at least one of the semiconductor chip surface and the support substrate surface over the entire periphery of the semiconductor chip. A semiconductor device characterized by being provided with dummy bumps.