JPS621249A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS621249A JPS621249A JP60139566A JP13956685A JPS621249A JP S621249 A JPS621249 A JP S621249A JP 60139566 A JP60139566 A JP 60139566A JP 13956685 A JP13956685 A JP 13956685A JP S621249 A JPS621249 A JP S621249A
- Authority
- JP
- Japan
- Prior art keywords
- openings
- insulating film
- protective insulating
- plating
- projecting electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
Landscapes
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体チップの外部接
続用電極に突起型電極構造を用いる半導体装置に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a protruding electrode structure for external connection electrodes of a semiconductor chip.
従来、バンプと称される突起型電極を有する半導体装置
は、半導体チップ上の配線層のアルミニウムパッド上に
金等の金属材で突起電極を形成した構成となつており、
この突起電極とアルミニウムパッドとの接着性を高める
一方で相互間での拡散を防ぐために両者間に接着層やバ
リア層を介挿している。例えば、第3図および第4図は
その一例であり、半導体基板l主面の絶縁膜2上にアル
ミニウムパッド3を形成し、その上に保護絶縁膜4を被
着してその一部を開口し、かつ露呈されたアルミニウム
パッド3上に接着層およびバリア層としてのTi−Pt
やCr−Cu等の多層構造のバリアメタル層5を形成し
、その上に厚膜の合材からなる突起電極6を形成してい
る。Conventionally, a semiconductor device having a protruding electrode called a bump has a structure in which the protruding electrode is formed of a metal material such as gold on an aluminum pad of a wiring layer on a semiconductor chip.
An adhesive layer or barrier layer is interposed between the protruding electrodes and the aluminum pads in order to enhance their adhesion and prevent diffusion between them. For example, FIGS. 3 and 4 are examples of this, in which an aluminum pad 3 is formed on the insulating film 2 on the main surface of the semiconductor substrate l, a protective insulating film 4 is deposited on it, and a part of it is opened. and Ti--Pt as an adhesive layer and a barrier layer on the exposed aluminum pad 3.
A barrier metal layer 5 having a multilayer structure such as Cr--Cu or the like is formed, and a protruding electrode 6 made of a thick film composite material is formed thereon.
そして、通常では保護絶縁膜4はアルミニウムパッド3
の周囲をオーバラップするような形にしており、これは
保護絶縁膜4を開口する際のエツチングにおいてアルミ
ニウムパッド3がストッパとして作用することを利用す
るためである1、また、突起電極6は保護絶縁膜4の周
囲をオーバラップする構成としているが、これは下地の
バリアメタル層5のエツチング時にマスクとしての突起
電極6の周囲からエツチング液がアルミニウムパッド3
にまで侵入してアルミニウムパッド3を損傷することを
防止するためである。Usually, the protective insulating film 4 is the aluminum pad 3.
This is to utilize the fact that the aluminum pad 3 acts as a stopper during etching when opening the protective insulating film 41, and the protruding electrode 6 is shaped so as to overlap the protective insulating film 4. The structure is such that the periphery of the insulating film 4 overlaps the periphery of the insulating film 4. This is because the etching solution is applied to the aluminum pad 3 from around the protruding electrode 6 serving as a mask when etching the underlying barrier metal layer 5.
This is to prevent the aluminum pad 3 from being damaged by penetrating into the aluminum pad 3.
上述した従来の突起電極構造では、保護絶縁膜4および
突起電極6が夫々周囲部分においてオーバラップしてい
るため、保護絶縁膜4の開口4a周辺では段差が生じる
ことになり、この段差がメッキ法等により形成した突起
電極6の上面に現れて中央部に対して周辺部6aが高い
形状となる。In the conventional protruding electrode structure described above, since the protective insulating film 4 and the protruding electrode 6 overlap in their respective peripheral portions, a step is generated around the opening 4a of the protective insulating film 4, and this step is removed by the plating method. It appears on the upper surface of the protruding electrode 6 formed by etching, etc., and has a shape in which the peripheral portion 6a is higher than the central portion.
このため、突起電極6に対してインナリード(銅に錫メ
ッキしたリード或いは金リード)7を熱圧着法によって
接続すると、突起電極6の周辺部6aが中央部よりも突
出していることから、周辺部6aにおける熱応力が他の
部分よりも特に強くなり、この応力がそのまま直下の保
護絶縁膜4等に加えられ、保護絶縁膜4、アルミニウム
パッド3下の絶縁膜2更に半導体基板lにクランクを発
生させる。この突起電極6下でのクランクは突起電極6
ごとリード7が剥がれる現象を引き起こすため、引っ張
り強度は殆どなく、信頼性の評価以前に半導体装置の不
良となる問題を生じている。Therefore, when the inner lead (copper tin-plated lead or gold lead) 7 is connected to the protruding electrode 6 by thermocompression bonding, the peripheral part 6a of the protruding electrode 6 protrudes more than the central part. Thermal stress in the portion 6a is particularly stronger than in other portions, and this stress is directly applied to the protective insulating film 4, etc. directly below, causing cranking to the protective insulating film 4, the insulating film 2 under the aluminum pad 3, and the semiconductor substrate l. generate. The crank under this protruding electrode 6 is the protruding electrode 6
This causes a phenomenon in which the leads 7 are peeled off, so that there is almost no tensile strength, resulting in a problem that the semiconductor device becomes defective before the reliability can be evaluated.
本発明の半導体装置は、突起電極上面を平坦化して突起
電極下でのクラックの発生を防止し、突起電極はもとよ
り半導体装置としての信頼性の向上を図るもので、保護
絶縁膜に形成して下地のアルミニウムパッドを露呈させ
る開口を平面配置した複数個の小さな開口によって構成
し、かつ保護絶縁膜上にこの開口を通して突起電極を形
成するように構成している。The semiconductor device of the present invention flattens the upper surface of the protruding electrode to prevent the occurrence of cracks under the protruding electrode, and improves the reliability of the protruding electrode as well as the semiconductor device. The opening exposing the underlying aluminum pad is composed of a plurality of small openings arranged in a plane, and the projecting electrode is formed on the protective insulating film through the opening.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図、および第2図は本発明の一実施例を示しており
、第1図は突起電極16の平面図、°第2図はそのAA
線断面図である。シリコン等の半導体基板11の主面に
絶縁膜12を形成し、その上にアルミニウムパッド13
を所定のパターンで形成し、更にこのこのアルミニウム
パッド13の上にはこれを覆うように保護絶縁膜14を
被着している。この保護絶縁膜14には、突起電極の形
成箇所に複数個の小さい開口14aを平面配置し、各開
口14aにおいて夫々前記アルミニウムバッド13を露
呈させている。そして、これらの開口14aを含む保護
絶縁膜14上にはT i −P tやCr−Cu等の多
層構造のバリアメタル層15を形成し、その上に合材を
厚く被着した突起電極16を形成している。1 and 2 show an embodiment of the present invention, in which FIG. 1 is a plan view of the protruding electrode 16, and FIG. 2 is an AA view thereof.
FIG. An insulating film 12 is formed on the main surface of a semiconductor substrate 11 made of silicon or the like, and an aluminum pad 13 is formed on it.
is formed in a predetermined pattern, and a protective insulating film 14 is deposited on the aluminum pad 13 so as to cover it. In this protective insulating film 14, a plurality of small openings 14a are arranged in a plane at locations where protruding electrodes are to be formed, and the aluminum pads 13 are exposed in each opening 14a. A barrier metal layer 15 having a multilayer structure such as Ti-Pt or Cr-Cu is formed on the protective insulating film 14 including these openings 14a, and a protruding electrode 16 is formed on the barrier metal layer 15 with a thick layer of composite material. is formed.
なお、この突起電極16の形成に際しては、バリアメタ
ル15層を全面に被着した後これをメッキ用電極として
その上に金を厚くメッキし、この金を図外のフォトレジ
ストを利用したフォトリソグラフィ技術によっそパター
ンにする方法を用いる点はこれまでと同じである。また
、この突起電極16をマスクとしてバリアメタル層15
をエツチングすることも同じである。更に、前記開口1
4aもフォトリソグラフィ技術によって形成しているが
、各開口14aの大きさく面積)は突起電極16の厚さ
に比較して小さくすることが肝要であり、また開口周縁
がなるべくテーパ状となるように形成することが好まし
い。In addition, when forming the protruding electrode 16, after coating the entire surface with the barrier metal 15 layer, this is used as a plating electrode, and a thick layer of gold is plated thereon, and this gold is coated with photolithography using a photoresist (not shown). The method of creating patterns using technology is the same as before. Further, using this protruding electrode 16 as a mask, the barrier metal layer 15 is
The same goes for etching. Furthermore, the opening 1
4a is also formed by photolithography technology, but it is important that the size and area of each opening 14a be small compared to the thickness of the protruding electrode 16, and that the periphery of the opening be as tapered as possible. It is preferable to form.
以°上の構成によれば、突起電極16は複数個の開口1
4aを含む領域に亘ってメッキ形成されるが、開口14
aがメッキ厚さに対して小さいために、メッキ上面には
開口14aに対応する極小さな凹部20が生ずるものの
全体としては平坦に形成され、したがって完成された突
起電極16の上面も平坦化される。これにより、インナ
リード17を熱圧着法で接続する場合にも、インナリー
ド17が突起電極、16に均一に接触されることになり
、熱応力の偏り乃至集中を防止して下地の絶縁膜12や
半導体基板11のクラックを未然に防止し、突起電極1
6の強度を向上して半導体装置の信頼性の向上を達成す
ることができる。According to the above configuration, the protruding electrode 16 has a plurality of openings 1
Although plating is formed over the area including 4a, the opening 14
Since a is small relative to the plating thickness, a very small recess 20 corresponding to the opening 14a is formed on the top surface of the plating, but the entire surface is flat, and therefore the top surface of the completed bump electrode 16 is also flat. . As a result, even when the inner leads 17 are connected by thermocompression bonding, the inner leads 17 are brought into uniform contact with the protruding electrodes 16, thereby preventing thermal stress from being uneven or concentrated. This prevents cracks in the semiconductor substrate 11 and the protruding electrode 1 from occurring.
By improving the strength of No. 6, it is possible to improve the reliability of the semiconductor device.
ここで、開口14aの数や平面形状は実施例のものに限
定されるものではなく、種々の変更が可能である。Here, the number and planar shape of the openings 14a are not limited to those in the embodiment, and various changes are possible.
以上説明したように本発明は、アルミニウムバラド上に
設けた保護絶縁膜に形成する開口を、平面配置した複数
個の小さな開口によって構成し、これらの開口を含む領
域上に突起電極を形成しているので、メッキ形成する突
起電極の上面の平坦化を図ることができ、インナリード
との接続時における熱応力の均一化を図って突起電極下
でのクランクの発生を防止し、突起電極強度を向上して
半導体装置の信顛性を向上することができる効果がある
。As explained above, in the present invention, the opening formed in the protective insulating film provided on the aluminum barrier is formed by a plurality of small openings arranged in a plane, and the projecting electrode is formed on the area including these openings. This makes it possible to flatten the upper surface of the protruding electrode to be plated, and to equalize thermal stress when connecting with the inner lead, preventing cranking under the protruding electrode and increasing the strength of the protruding electrode. This has the effect of improving the reliability of the semiconductor device.
第1図は本発明の一実施例の平面図、第2図は第1図の
AA線に沿う断面図、第3図は従来構造の平面図、第4
図は第3図のBB線断面である。
1.11・・・半導体基板、2.12・・・絶縁膜、3
゜13・・・アルミニウムパッド、4.14・・・保護
絶縁膜、4a、14a・・・開口、5.15・・・バリ
アメタル層、6.16・・・突起電極、7.17・・・
インナリード、20・・・凹部。
第1図FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a sectional view taken along line AA in FIG. 1, FIG. 3 is a plan view of a conventional structure, and FIG.
The figure is a cross section taken along line BB in FIG. 1.11... Semiconductor substrate, 2.12... Insulating film, 3
゜13... Aluminum pad, 4.14... Protective insulating film, 4a, 14a... Opening, 5.15... Barrier metal layer, 6.16... Protruding electrode, 7.17...・
Inner lead, 20... recess. Figure 1
Claims (1)
護絶縁膜を被着し、この保護絶縁膜に設けた開口を通し
て前記金属パッドを露呈させ、この金属パッドを含む領
域上にバリアメタル層および突起電極を形成した半導体
装置において、前記保護絶縁膜に形成する開口は突起電
極の厚さに比較して小さくするとともに、突起電極の形
成領域に亘って複数個を平面配置したことを特徴とする
半導体装置。1. A protective insulating film is deposited to cover the metal pad formed on the semiconductor substrate, the metal pad is exposed through an opening provided in the protective insulating film, and a barrier metal layer and a barrier metal layer are formed on the area including the metal pad. A semiconductor device in which a protruding electrode is formed, characterized in that the opening formed in the protective insulating film is smaller than the thickness of the protruding electrode, and a plurality of openings are arranged in a plane over the area where the protruding electrode is formed. Semiconductor equipment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60139566A JPS621249A (en) | 1985-06-26 | 1985-06-26 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60139566A JPS621249A (en) | 1985-06-26 | 1985-06-26 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS621249A true JPS621249A (en) | 1987-01-07 |
Family
ID=15248248
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60139566A Pending JPS621249A (en) | 1985-06-26 | 1985-06-26 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS621249A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06333929A (en) * | 1993-05-21 | 1994-12-02 | Nec Corp | Semiconductor device and its manufacture |
JPH07161722A (en) * | 1993-12-03 | 1995-06-23 | Nec Corp | Pad structure of semiconductor device |
JP2008235786A (en) * | 2007-03-23 | 2008-10-02 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
USRE40819E1 (en) | 1995-12-21 | 2009-07-07 | Micron Technology, Inc. | Semiconductor device with improved bond pads |
-
1985
- 1985-06-26 JP JP60139566A patent/JPS621249A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06333929A (en) * | 1993-05-21 | 1994-12-02 | Nec Corp | Semiconductor device and its manufacture |
JPH07161722A (en) * | 1993-12-03 | 1995-06-23 | Nec Corp | Pad structure of semiconductor device |
USRE40819E1 (en) | 1995-12-21 | 2009-07-07 | Micron Technology, Inc. | Semiconductor device with improved bond pads |
JP2008235786A (en) * | 2007-03-23 | 2008-10-02 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
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