USRE40819E1 - Semiconductor device with improved bond pads - Google Patents

Semiconductor device with improved bond pads Download PDF

Info

Publication number
USRE40819E1
USRE40819E1 US09/438,692 US43869299A USRE40819E US RE40819 E1 USRE40819 E1 US RE40819E1 US 43869299 A US43869299 A US 43869299A US RE40819 E USRE40819 E US RE40819E
Authority
US
United States
Prior art keywords
semiconductor device
bonding surface
openings
bond
bond pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/438,692
Inventor
Rodney C. Langley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Bank NA
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to US09/438,692 priority Critical patent/USRE40819E1/en
Application granted granted Critical
Publication of USRE40819E1 publication Critical patent/USRE40819E1/en
Anticipated expiration legal-status Critical
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT reassignment MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT PATENT SECURITY AGREEMENT Assignors: MICRON TECHNOLOGY, INC.
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Assignors: MICRON TECHNOLOGY, INC.
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20105—Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20106—Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20107—Temperature range 250 C=<T<300 C, 523.15K =<T< 573.15K

Definitions

  • the invention relates to semiconductor devices having bond pads for connection to an external circuit and, more particularly, to an improved bond pad having openings in the bonding surface of the bond pad.
  • bond pads are select areas of the interconnect wiring pattern left exposed after formation of the passivation layer which covers the semiconductor die.
  • the active circuits in the die are connected to the interconnect wiring and accessed through the bond pads.
  • Thin wires are bonded to the bond pads. These bond wires electrically connect the bond pads to metal leads which, after the die/lead assembly has been enclosed within a sealed package, are inserted into or otherwise attached to a printed circuit board.
  • a heat block heats the die and the leads to a temperature of about 150° C. to 350° C.
  • the end of the bond wire is heated by an electrical discharge or a hydrogen torch to a molten state, thus forming a ball of molten metal on the end of the bond wire.
  • the molten ball is pressed by a bonding capillary tool against the heated bond pad, sometimes in combination with ultrasonic vibration, to alloy the metallic elements of the wire and the metal bond pad and thereby bond the wire to the pad.
  • the bonding capillary tool is then moved to a bonding site on the appropriate lead.
  • the wire is pressed against the heated lead to bond the wire to the lead.
  • the bond wire is then tensioned and sheared. The process is repeated for each bond pad on the die.
  • the bonding surface of conventional bond pads is substantially flat.
  • the present invention is directed in general to an improved bond pad and, more specifically, to a bond pad having openings formed in the bonding surface of the bond pad. It is believed that forming openings in the bonding surface of the bond pad may, in some instances, improve the strength of the wire bond.
  • a semiconductor device that includes a bond pad electrically connected to an active circuit in the semiconductor device and at least one opening formed in the bonding surface of the bond pad.
  • the opening(s) may include recesses extending partially into the bonding surface or channels that extend entirely through the bond pad.
  • Various shapes and configurations of the openings may be used and tailored to specific device requirements.
  • the openings may be a pattern of rectangular channels disposed about the center of the bonding surface or an array of holes.
  • FIG. 1 is a top down plan view of a bond pad having a series of rectangular channels arranged parallel to one another.
  • FIG. 2 is a cross section view taken along the line A—A in FIG. 1 wherein the openings extend through the bond pad.
  • FIG. 3 is a cross section view taken along the line A—A in FIG. 1 wherein the openings extend only partially into the bond pad.
  • FIG. 4-6 are top down plan views of alternative embodiments of the invented bond pad having various configurations of openings.
  • FIGS. 7-9 are cross section views of the device of FIG. 1 at various stages of fabrication.
  • FIG. 10 is an expanded view of the bond between a bond wire and the bond pad of FIG. 1 .
  • FIGS. 1 and 2 are a top down plan view and a cross section view, respectively, of one of the preferred embodiments of the present invention.
  • semiconductor device 10 can be any integrated circuit device, such as a random access memory (RAM), a programmable read only memory (PROM), a logic circuit or any type of application specific integrated circuit device.
  • the active circuits (not shown), which are formed in a main region 12 of the semiconductor device 10 , are electrically connected to bond pads 14 .
  • Bond pads 14 constitute select areas of a wiring pattern exposed through holes 16 in passivation layer 18 .
  • the wiring pattern and, correspondingly, bond pads 14 are formed on thick insulating layer 20 . Openings 22 are formed in the bonding surface 24 of bond pads 14 .
  • openings 22 extend through bond pads 14 , as shown in FIG. 1 .
  • openings 22 may be recesses that extend only partially into bonding surface 24 , as shown in FIG. 3 .
  • Openings 22 comprise a series rectangular channels arranged parallel to one another as shown in FIG. 1 .
  • Other shapes and configurations may also be used and tailored to specific device requirements.
  • openings 22 may comprise a pattern of radiating channels disposed about the center of bonding surface 24 as illustrated in FIGS. 4 , an array of L shaped channels as shown in FIG. 5 , or an array of holes as shown in FIG. 6 .
  • the center portion of bonding surface 24 may be left free of openings.
  • openings are believed to promote a more robust bond by increasing the surface area available for bonding, but without increasing the size of the bond pad.
  • sidewalls of openings 22 collapse during the bonding process, thereby further increasing bond strength.
  • semiconductor device 10 is formed using conventional fabrication processes and materials well known in the art, including etching predetermined patterns into the various layers of material. Such etching is referred to herein for convenience as “patterning and etching.” Photolithography and reactive ion etching, for example, are commonly used pattern and etch processes. These or other pattern and etch processes, well known to those skilled in the art, may be used to implement the present invention. Referring first to FIG. 7 , active circuits (not shown) are formed in a main region 12 of semiconductor device 10 .
  • Thick insulating layer 20 is formed over the active circuits and usually extends into the periphery to cover the entire upper surface of the device. Insulating layer 20 is patterned and etched, and this etch may continue down through inferior layers of material, to open contact vias (not shown) to the active circuits. A layer of metal 26 , typically aluminum, is deposited over insulating layer 20 and into the contact vias.
  • metal layer 26 is patterned and etched to form an interconnect wiring pattern.
  • openings 22 are formed in select areas of the wiring pattern at the desired locations of the bond pads 14 .
  • passivation layer 18 typically made of phosphosilicate glass or silicon nitride, is then deposited over the entire surface of the device and patterned and etched to form holes 16 and thereby expose the select areas of the wiring pattern in which openings 22 were previously formed. Those areas of the wiring pattern exposed through holes 16 in passivation layer 18 constitute bond pads 14 .
  • openings 22 extend through bond pads 14
  • a portion of the material comprising passivation 18 will typically be left in the bottom of the openings 22 . If, and to what extent, such material remains in openings 22 will depend on the duration and selectively of the passivation layer etch.
  • bond wire 30 is bonded to bond pad 14 .
  • Bond wire 30 serves as an electrode for connection to an external circuit.
  • this wire bond connection is made by forming a molten ball on the end of bond wire 30 and pressing the molten ball against bond pad 14 , which has been heated to a temperature 150° C. and 350° C., in the presence of ultrasonic vibration to alloy the metallic elements of bond wire 30 and bond pad 14 . It is believed that the bonding process causes the sidewalls of openings 22 to collapse resulting in the bond shown in FIG. 10 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor device with improved bond pads. The semiconductor device includes bond pads electrically connected to an active circuit in the device and openings formed in the bonding surface of the bond pads. The opening(s) may include recesses extending partially into the bonding surface or channels that extend entirely through the bond pads. Various shapes and configurations of the openings may be used, such as a pattern of channels radiating from the center of the bonding surface, a series of spaced apart rectangular channels arranged parallel to one another, an array of L shaped channels arranged around the center of the bonding surface, or an array of holes.

Description

FIELD OF THE INVENTION
The invention relates to semiconductor devices having bond pads for connection to an external circuit and, more particularly, to an improved bond pad having openings in the bonding surface of the bond pad.
BACKGROUND OF THE INVENTION
Many semiconductor devices utilize bond pads as the terminals for electrically connecting active circuits in the device to an external circuit. The bond pads are select areas of the interconnect wiring pattern left exposed after formation of the passivation layer which covers the semiconductor die. The active circuits in the die are connected to the interconnect wiring and accessed through the bond pads. Thin wires are bonded to the bond pads. These bond wires electrically connect the bond pads to metal leads which, after the die/lead assembly has been enclosed within a sealed package, are inserted into or otherwise attached to a printed circuit board.
During the wire bonding process, a heat block heats the die and the leads to a temperature of about 150° C. to 350° C. The end of the bond wire is heated by an electrical discharge or a hydrogen torch to a molten state, thus forming a ball of molten metal on the end of the bond wire. The molten ball is pressed by a bonding capillary tool against the heated bond pad, sometimes in combination with ultrasonic vibration, to alloy the metallic elements of the wire and the metal bond pad and thereby bond the wire to the pad. The bonding capillary tool is then moved to a bonding site on the appropriate lead. The wire is pressed against the heated lead to bond the wire to the lead. The bond wire is then tensioned and sheared. The process is repeated for each bond pad on the die.
The bonding surface of conventional bond pads is substantially flat. The present invention is directed in general to an improved bond pad and, more specifically, to a bond pad having openings formed in the bonding surface of the bond pad. It is believed that forming openings in the bonding surface of the bond pad may, in some instances, improve the strength of the wire bond.
SUMMARY OF THE INVENTION
Accordingly, it is one object of the invention to improve the strength of the bond between the bond wire and the bond pad formed during the fabrication of semiconductor devices.
It is another object of the invention to increase the surface area of the bond pad without also increasing the size of the bond pad.
According to the present invention, these and other objects are achieved by a semiconductor device that includes a bond pad electrically connected to an active circuit in the semiconductor device and at least one opening formed in the bonding surface of the bond pad. The opening(s) may include recesses extending partially into the bonding surface or channels that extend entirely through the bond pad. Various shapes and configurations of the openings may be used and tailored to specific device requirements. For example, the openings may be a pattern of rectangular channels disposed about the center of the bonding surface or an array of holes.
Additional objects, advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a top down plan view of a bond pad having a series of rectangular channels arranged parallel to one another.
FIG. 2 is a cross section view taken along the line A—A in FIG. 1 wherein the openings extend through the bond pad.
FIG. 3 is a cross section view taken along the line A—A in FIG. 1 wherein the openings extend only partially into the bond pad.
FIG. 4-6 are top down plan views of alternative embodiments of the invented bond pad having various configurations of openings.
FIGS. 7-9 are cross section views of the device of FIG. 1 at various stages of fabrication.
FIG. 10 is an expanded view of the bond between a bond wire and the bond pad of FIG. 1.
 DETAILED DESCRIPTION OF THE INVENTION
FIGS. 1 and 2 are a top down plan view and a cross section view, respectively, of one of the preferred embodiments of the present invention. Referring to FIGS. 1 and 2, semiconductor device 10 can be any integrated circuit device, such as a random access memory (RAM), a programmable read only memory (PROM), a logic circuit or any type of application specific integrated circuit device. The active circuits (not shown), which are formed in a main region 12 of the semiconductor device 10, are electrically connected to bond pads 14. Bond pads 14 constitute select areas of a wiring pattern exposed through holes 16 in passivation layer 18. The wiring pattern and, correspondingly, bond pads 14 are formed on thick insulating layer 20. Openings 22 are formed in the bonding surface 24 of bond pads 14.
Preferably, openings 22 extend through bond pads 14, as shown in FIG. 1. Alternatively, openings 22 may be recesses that extend only partially into bonding surface 24, as shown in FIG. 3. Openings 22 comprise a series rectangular channels arranged parallel to one another as shown in FIG. 1. Other shapes and configurations may also be used and tailored to specific device requirements. For example, openings 22 may comprise a pattern of radiating channels disposed about the center of bonding surface 24 as illustrated in FIGS. 4, an array of L shaped channels as shown in FIG. 5, or an array of holes as shown in FIG. 6. To facilitate probing and testing, the center portion of bonding surface 24 may be left free of openings.
The openings are believed to promote a more robust bond by increasing the surface area available for bonding, but without increasing the size of the bond pad. In addition, it is believed that the sidewalls of openings 22 collapse during the bonding process, thereby further increasing bond strength.
The formation of semiconductor device 10 will now be described with reference to FIGS. 7-9. Semiconductor device 10 is formed using conventional fabrication processes and materials well known in the art, including etching predetermined patterns into the various layers of material. Such etching is referred to herein for convenience as “patterning and etching.” Photolithography and reactive ion etching, for example, are commonly used pattern and etch processes. These or other pattern and etch processes, well known to those skilled in the art, may be used to implement the present invention. Referring first to FIG. 7, active circuits (not shown) are formed in a main region 12 of semiconductor device 10. Thick insulating layer 20, typically made of phosphosilicate glass, is formed over the active circuits and usually extends into the periphery to cover the entire upper surface of the device. Insulating layer 20 is patterned and etched, and this etch may continue down through inferior layers of material, to open contact vias (not shown) to the active circuits. A layer of metal 26, typically aluminum, is deposited over insulating layer 20 and into the contact vias.
Referring now to FIG. 8, metal layer 26 is patterned and etched to form an interconnect wiring pattern. Preferably during this same pattern and etch step, openings 22 are formed in select areas of the wiring pattern at the desired locations of the bond pads 14. Referring to FIG. 9, passivation layer 18, typically made of phosphosilicate glass or silicon nitride, is then deposited over the entire surface of the device and patterned and etched to form holes 16 and thereby expose the select areas of the wiring pattern in which openings 22 were previously formed. Those areas of the wiring pattern exposed through holes 16 in passivation layer 18 constitute bond pads 14. For those embodiments of the invention wherein openings 22 extend through bond pads 14, a portion of the material comprising passivation 18 will typically be left in the bottom of the openings 22. If, and to what extent, such material remains in openings 22 will depend on the duration and selectively of the passivation layer etch.
Referring to FIG. 10, bond wire 30 is bonded to bond pad 14. Bond wire 30 serves as an electrode for connection to an external circuit. As is known in the art, this wire bond connection is made by forming a molten ball on the end of bond wire 30 and pressing the molten ball against bond pad 14, which has been heated to a temperature 150° C. and 350° C., in the presence of ultrasonic vibration to alloy the metallic elements of bond wire 30 and bond pad 14. It is believed that the bonding process causes the sidewalls of openings 22 to collapse resulting in the bond shown in FIG. 10.
There has been shown and described a semiconductor device having an improved bond pad wherein openings are formed in the bond pad to help create a more robust bond between the bond pad and an electrode. The particular embodiments shown in the drawings and described herein are for purposes of example and should not be construed to limit the invention as set forth in the appended claims.

Claims (17)

1. A semiconductor device having an improved bond pad, the semiconductor device comprising:
a. a bond pad electrically connected to an active circuit in the semiconductor device;
b. a substantially flat bonding surface on the bond pad; and
c. an opening extending partially into the bonding surface.
2. A semiconductor device according to claim 1, further comprising a plurality of openings in the bonding surface of the bond pad.
3. A semiconductor device according to claim 2, wherein the openings are disposed about a center portion of the bonding surface of the bond pad so that the center portion of the bonding surface is free of openings.
4. A semiconductor device according to claim 4, wherein the openings comprise A semiconductor device having an improved bond pad, the semiconductor device comprising:
a. a bond pad electrically connected to an active circuit in the semiconductor device;
b. a substantially flat bonding surface on the bond pad; and
c. a plurality of openings extending partially into the bonding surface and forming a pattern of radiating channels disposed about a center of the bonding surface.
5. A semiconductor device according to claim 2, wherein the openings comprise a series of spaced apart rectangular channels arranged parallel to one another.
6. A semiconductor device according to claim 2, wherein the openings comprise an array of L shaped channels disposed about a center of the bonding surface.
7. A semiconductor device according to claim 2, wherein the openings comprise an array of holes disposed about the bonding surface.
8. A semiconductor device, which comprises:
a. an active circuit in the semiconductor device;
b. a wiring pattern overlying and in electrical contact with the active circuit;
c. bond pads formed as select areas on the wiring pattern; and
d. a plurality of openings extending partially into a substantially flat bonding surface of the bond pads.
9. A semiconductor device according to claim 8, wherein the openings are disposed about a center portion of the bonding surface of the bond pad so that the center portion of the bonding surface is free of openings.
10. A semiconductor device according to claim 8, A semiconductor device, which comprises:
a. an active circuit in the semiconductor device;
b. a wiring pattern overlying and in electrical contact with the active circuit;
c. bond pads formed as select areas on the wiring pattern; and
d. a plurality of openings extending partially into a substantially flat bonding surface of the bond pads, wherein the openings comprise a pattern of radiating channels disposed about a center of the bonding surface.
11. A semiconductor device according to claim 8, wherein the openings comprise a series of spaced apart rectangular channels arranged parallel to one another.
12. A semiconductor device according to claim 8, wherein the openings comprise an array of L shaped channels disposed about a center of the bonding surface.
13. A semiconductor device according to claim 8, wherein the openings comprise an array of holes disposed about the bonding surface.
14. A semiconductor device according to claim 8, further comprising a passivation layer overlying the wiring pattern, the passivation layer having holes therethrough to expose the bonding surface of the bond pads to enable electrical connection to the bond pads through the holes.
15. A semiconductor device according to claim 8, further comprising bond wires bonded to the bonding surface of the bond pads.
16. A semiconductor device, comprising:
a. a layer of insulating material;
b. a substantially flat layer of conductive material overlying the layer of insulating material;
c. bond pads formed as select areas on a surface of the layer of conductive material; and
d. at least one opening extending partially into the bond pads.
17. An improved bond pad comprising:
a metal layer having a substantially planar surface, said metal layer electrically connected to an active circuit of a semiconductor device and having a plurality of openings extending partially into said metal layer,
wherein the openings comprise a pattern of radiating channels disposed about a center of the bond pad.
US09/438,692 1995-12-21 1999-11-11 Semiconductor device with improved bond pads Expired - Lifetime USRE40819E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/438,692 USRE40819E1 (en) 1995-12-21 1999-11-11 Semiconductor device with improved bond pads

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/577,911 US5686762A (en) 1995-12-21 1995-12-21 Semiconductor device with improved bond pads
US09/438,692 USRE40819E1 (en) 1995-12-21 1999-11-11 Semiconductor device with improved bond pads

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/577,911 Reissue US5686762A (en) 1995-12-21 1995-12-21 Semiconductor device with improved bond pads

Publications (1)

Publication Number Publication Date
USRE40819E1 true USRE40819E1 (en) 2009-07-07

Family

ID=24310649

Family Applications (2)

Application Number Title Priority Date Filing Date
US08/577,911 Ceased US5686762A (en) 1995-12-21 1995-12-21 Semiconductor device with improved bond pads
US09/438,692 Expired - Lifetime USRE40819E1 (en) 1995-12-21 1999-11-11 Semiconductor device with improved bond pads

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US08/577,911 Ceased US5686762A (en) 1995-12-21 1995-12-21 Semiconductor device with improved bond pads

Country Status (1)

Country Link
US (2) US5686762A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080150147A1 (en) * 2004-11-23 2008-06-26 International Business Machines Corporation High surface area aluminum bond pad for through-wafer connections to an electronic package

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3526376B2 (en) 1996-08-21 2004-05-10 株式会社東芝 Semiconductor device and manufacturing method thereof
US6143396A (en) * 1997-05-01 2000-11-07 Texas Instruments Incorporated System and method for reinforcing a bond pad
JPH1168504A (en) * 1997-08-11 1999-03-09 Murata Mfg Co Ltd Surface acoustic wave device
WO1999038204A1 (en) * 1998-01-23 1999-07-29 Rohm Co., Ltd. Damascene interconnection and semiconductor device
TW411602B (en) * 1998-02-07 2000-11-11 Winbond Electronics Corp Semiconductor manufacturing process and its structure which can prevent bonding pad fall-off due to the plug process
US6329712B1 (en) 1998-03-25 2001-12-11 Micron Technology, Inc. High density flip chip memory arrays
KR100265566B1 (en) * 1998-05-12 2000-09-15 김영환 Ship stack package
US5942800A (en) * 1998-06-22 1999-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Stress buffered bond pad and method of making
US6566249B1 (en) * 1998-11-09 2003-05-20 Cypress Semiconductor Corp. Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures
US6444295B1 (en) 1998-12-29 2002-09-03 Industrial Technology Research Institute Method for improving integrated circuits bonding firmness
JP4021104B2 (en) * 1999-08-05 2007-12-12 セイコーインスツル株式会社 Semiconductor device having bump electrodes
US6297562B1 (en) 1999-09-20 2001-10-02 Telefonaktieboalget Lm Ericsson (Publ) Semiconductive chip having a bond pad located on an active device
US6191023B1 (en) * 1999-11-18 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of improving copper pad adhesion
US6489640B1 (en) * 2000-10-06 2002-12-03 National Semiconductor Corporation Integrated circuit with fuse element and contact pad
US7078822B2 (en) * 2002-06-25 2006-07-18 Intel Corporation Microelectronic device interconnects
US7015580B2 (en) * 2003-11-25 2006-03-21 International Business Machines Corporation Roughened bonding pad and bonding wire surfaces for low pressure wire bonding
JP2005243907A (en) * 2004-02-26 2005-09-08 Renesas Technology Corp Semiconductor device
JP4964780B2 (en) 2004-11-12 2012-07-04 スタッツ・チップパック・インコーポレイテッド Wire bond interconnect, semiconductor package, and method of forming wire bond interconnect
US7868468B2 (en) * 2004-11-12 2011-01-11 Stats Chippac Ltd. Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates
US8519517B2 (en) 2004-11-13 2013-08-27 Stats Chippac Ltd. Semiconductor system with fine pitch lead fingers and method of manufacturing thereof
US7731078B2 (en) * 2004-11-13 2010-06-08 Stats Chippac Ltd. Semiconductor system with fine pitch lead fingers
DE102006008454B4 (en) * 2005-02-21 2011-12-22 Samsung Electronics Co., Ltd. Pad structure, pad layout structure, semiconductor device, and pad layout method
US20060211167A1 (en) * 2005-03-18 2006-09-21 International Business Machines Corporation Methods and systems for improving microelectronic i/o current capabilities
JP4533804B2 (en) * 2005-06-02 2010-09-01 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof
US7791199B2 (en) * 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
JP5114969B2 (en) * 2007-02-21 2013-01-09 富士通セミコンダクター株式会社 Semiconductor device, semiconductor wafer structure, and manufacturing method of semiconductor device
CN101675516B (en) * 2007-03-05 2012-06-20 数字光学欧洲有限公司 Chips having rear contacts connected by through vias to front contacts
US7821132B2 (en) * 2007-06-05 2010-10-26 Xilinx, Inc. Contact pad and method of forming a contact pad for an integrated circuit
KR101538648B1 (en) 2007-07-31 2015-07-22 인벤사스 코포레이션 Semiconductor packaging process using through silicon vias
US7701049B2 (en) * 2007-08-03 2010-04-20 Stats Chippac Ltd. Integrated circuit packaging system for fine pitch substrates
US7888257B2 (en) * 2007-10-10 2011-02-15 Agere Systems Inc. Integrated circuit package including wire bonds
EP2195837A1 (en) * 2007-10-31 2010-06-16 Agere Systems Inc. Bond pad support structure for semiconductor device
US7935979B2 (en) * 2008-05-01 2011-05-03 Bridgelux, Inc. Wire bonding to connect electrodes
US8259415B2 (en) * 2009-06-22 2012-09-04 Seagate Technology Llc Slider bond pad with a recessed channel
US8901736B2 (en) * 2010-05-28 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Strength of micro-bump joints
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
KR101059490B1 (en) * 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 Conductive pads defined by embedded traces
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US20130154099A1 (en) 2011-12-16 2013-06-20 Semiconductor Components Industries, Llc Pad over interconnect pad structure design
DE102012109995A1 (en) * 2012-10-19 2014-04-24 Osram Opto Semiconductors Gmbh Semiconductor component e.g. laser diode chip has contact portion that is provided for externally and electrically contacting semiconductor component with bonding compound, and patterning portion that is provided with elongated recess
US9536850B2 (en) * 2013-03-08 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad
KR20150139190A (en) * 2014-06-03 2015-12-11 삼성전기주식회사 Device and device package
US9536848B2 (en) * 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
DE102014116956A1 (en) * 2014-11-19 2016-05-19 Infineon Technologies Ag Method for forming a bond pad and bond pad
US9984987B2 (en) * 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
KR20200122673A (en) * 2019-04-18 2020-10-28 삼성전자주식회사 Pattern disign and method for inspecting the pattern disign
US11217496B2 (en) 2019-05-07 2022-01-04 Globalfoundries Singapore Pte. Ltd. Test pad with crack stop protection

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5553441A (en) 1978-10-14 1980-04-18 Sony Corp Semiconductor device
JPS5739548A (en) 1980-08-21 1982-03-04 Toshiba Corp Semiconductor device
JPS5740943A (en) 1980-08-22 1982-03-06 Mitsubishi Electric Corp Semiconductror device
JPS5935437A (en) 1982-08-24 1984-02-27 Nec Corp Semiconductor device
JPS621249A (en) 1985-06-26 1987-01-07 Nec Corp Semiconductor device
JPS63161634A (en) * 1986-12-24 1988-07-05 Nec Corp Semiconductor integrated circuit device
JPH01179434A (en) 1988-01-06 1989-07-17 Nec Corp Semiconductor integrated circuit device
JPH02180020A (en) 1989-01-04 1990-07-12 Nec Corp Integrated circuit device
JPH02187045A (en) 1989-01-13 1990-07-23 Sharp Corp Formation of facedown bonding pad
JPH03153049A (en) 1989-11-10 1991-07-01 Fujitsu Ltd Semiconductor device
US5053850A (en) * 1988-03-14 1991-10-01 Motorola, Inc. Bonding pad for semiconductor devices
JPH03242938A (en) 1990-02-21 1991-10-29 Matsushita Electron Corp Semiconductor device
JPH0474446A (en) 1990-07-16 1992-03-09 Matsushita Electron Corp Semiconductor device
US5248903A (en) * 1992-09-18 1993-09-28 Lsi Logic Corporation Composite bond pads for semiconductor devices
JPH0637135A (en) * 1992-07-20 1994-02-10 Murata Mfg Co Ltd Semiconductor device
US5373111A (en) * 1993-11-19 1994-12-13 Delco Electronics Corporation Bond pad having a patterned bonding surface
US5703408A (en) 1995-04-10 1997-12-30 United Microelectronics Corporation Bonding pad structure and method thereof

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5553441A (en) 1978-10-14 1980-04-18 Sony Corp Semiconductor device
JPS5739548A (en) 1980-08-21 1982-03-04 Toshiba Corp Semiconductor device
JPS5740943A (en) 1980-08-22 1982-03-06 Mitsubishi Electric Corp Semiconductror device
JPS5935437A (en) 1982-08-24 1984-02-27 Nec Corp Semiconductor device
JPS621249A (en) 1985-06-26 1987-01-07 Nec Corp Semiconductor device
JPS63161634A (en) * 1986-12-24 1988-07-05 Nec Corp Semiconductor integrated circuit device
JPH01179434A (en) 1988-01-06 1989-07-17 Nec Corp Semiconductor integrated circuit device
US5053850A (en) * 1988-03-14 1991-10-01 Motorola, Inc. Bonding pad for semiconductor devices
JPH02180020A (en) 1989-01-04 1990-07-12 Nec Corp Integrated circuit device
JPH02187045A (en) 1989-01-13 1990-07-23 Sharp Corp Formation of facedown bonding pad
JPH03153049A (en) 1989-11-10 1991-07-01 Fujitsu Ltd Semiconductor device
JPH03242938A (en) 1990-02-21 1991-10-29 Matsushita Electron Corp Semiconductor device
JPH0474446A (en) 1990-07-16 1992-03-09 Matsushita Electron Corp Semiconductor device
JPH0637135A (en) * 1992-07-20 1994-02-10 Murata Mfg Co Ltd Semiconductor device
US5248903A (en) * 1992-09-18 1993-09-28 Lsi Logic Corporation Composite bond pads for semiconductor devices
US5373111A (en) * 1993-11-19 1994-12-13 Delco Electronics Corporation Bond pad having a patterned bonding surface
US5703408A (en) 1995-04-10 1997-12-30 United Microelectronics Corporation Bonding pad structure and method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080150147A1 (en) * 2004-11-23 2008-06-26 International Business Machines Corporation High surface area aluminum bond pad for through-wafer connections to an electronic package
US7964967B2 (en) * 2004-11-23 2011-06-21 International Business Machines Corporation High surface area aluminum bond pad for through-wafer connections to an electronic package

Also Published As

Publication number Publication date
US5686762A (en) 1997-11-11

Similar Documents

Publication Publication Date Title
USRE40819E1 (en) Semiconductor device with improved bond pads
US5892273A (en) Semiconductor package integral with semiconductor chip
US6313540B1 (en) Electrode structure of semiconductor element
US6153448A (en) Semiconductor device manufacturing method
US5707894A (en) Bonding pad structure and method thereof
US6020624A (en) Semiconductor package with bi-substrate die
KR100294719B1 (en) Molded semiconductor device and method for manufacturing the same, lead frame
US7315077B2 (en) Molded leadless package having a partially exposed lead frame pad
US5445994A (en) Method for forming custom planar metal bonding pad connectors for semiconductor dice
US6228689B1 (en) Trench style bump and application of the same
KR940002993A (en) Pad Array Semiconductor Device with Thermal Conductor and Manufacturing Method Thereof
US5708304A (en) Semiconductor device
JPH0829451A (en) Bump semiconductor device and probe inspection method thereof
JPH09330934A (en) Semiconductor device and its manufacture
KR20020044590A (en) Metal redistribution layer having solderable pads and wire bondable pads
JPH06302653A (en) Semiconductor device
JP3077316B2 (en) Integrated circuit device
US5863812A (en) Process for manufacturing a multi layer bumped semiconductor device
JP2000068403A (en) Semiconductor device and substrate bonding structure thereof
US6677235B1 (en) Silicon die with metal feed through structure
US5463255A (en) Semiconductor integrated circuit device having an electrode pad including an extended wire bonding portion
US6984877B2 (en) Bumped chip carrier package using lead frame and method for manufacturing the same
KR970077584A (en) Semiconductor device and manufacturing method
US5408127A (en) Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components
US6424049B1 (en) Semiconductor device having chip-on-chip structure and semiconductor chip used therefor

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001

Effective date: 20180629

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001

Effective date: 20190731