JPH03153049A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03153049A
JPH03153049A JP1292597A JP29259789A JPH03153049A JP H03153049 A JPH03153049 A JP H03153049A JP 1292597 A JP1292597 A JP 1292597A JP 29259789 A JP29259789 A JP 29259789A JP H03153049 A JPH03153049 A JP H03153049A
Authority
JP
Japan
Prior art keywords
layer
opening
pad portion
bonding wire
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1292597A
Other languages
Japanese (ja)
Inventor
Masakimi Nakahara
中原　正公
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Original Assignee
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Fujitsu Electronics Ltd, Fujitsu Ltd filed Critical Kyushu Fujitsu Electronics Ltd
Priority to JP1292597A priority Critical patent/JPH03153049A/en
Publication of JPH03153049A publication Critical patent/JPH03153049A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
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    • H01L2224/0554—External layer
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    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a semiconductor device whose moistureproof property is high by a method wherein a sidewall of a surface insulating layer does not come into contact with a molding resin and is covered with a metal. CONSTITUTION:Side faces of surface insulating layers 4, 5 are covered with an upper-layer pad part 7 and with a ball part 8 of a bonding wire 9 and do not come into contact with a molding resin. Consequently, moisture which has penetrated the molding resin does not reach exposed sidewalls of the surface insulating layers 4, 5. When the surface protective layers 4, 5 are composed of, e.g. a PSG layer 4 and an SiN layer 5, the moisture in the molding resin cannot reach the PSG layer 4 and it is possible to prevent phosphorus from being dissolved out from the PSG layer 4. The upper-layer pad part 7 is provided with an uneven surface. The ball part 8 of the bonding wire 9 comes into contact with the uneven surface of the upper-layer pad part 7. As a result, a bonding power of the bonding wire is increased.

Description

【発明の詳細な説明】 ［概要］ アルミニウムのポンディングパッドを有する半導体装置
に関し、 耐湿性に優れたポンディングパッドを有する半導体装１
を提供することを目的とし、 半導体基板と、該半導体基板上に形成された第１絶縁膜
と、該第１絶縁膜上に形成され、配線層に連続するアル
ミニウム層の下層パッド部と、該アルミニウム層の下層
パッド部の少なくとも周辺部を覆い、下層パッド部の１
部表面を露出する開口を有する表面絶縁層と、該アルミ
ニウム層の下層バンド部上に形成され、凹凸を有する表
面を形成する金属層の上層パッド部と、該上層パッド部
の露出表面を覆うボール部分を有するボンディングワイ
ヤとを有するように構成する。[Detailed Description of the Invention] [Summary] Regarding a semiconductor device having an aluminum bonding pad, the semiconductor device having a bonding pad with excellent moisture resistance 1
A semiconductor substrate, a first insulating film formed on the semiconductor substrate, a lower pad portion of an aluminum layer formed on the first insulating film and continuous with a wiring layer, Covers at least the peripheral part of the lower pad part of the aluminum layer, and covers one part of the lower pad part of the aluminum layer.
a surface insulating layer having an opening exposing the surface of the aluminum layer; an upper pad portion of a metal layer formed on the lower band portion of the aluminum layer and forming an uneven surface; and a ball covering the exposed surface of the upper pad portion. A bonding wire having a portion.

［産業上の利用分野］ 本発明は半導体装置に関し、特にアルミニウムのポンデ
ィングパッドを有する半導体装置に関する。[Industrial Field of Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an aluminum bonding pad.

［従来の技術］ 第２図（Ａ）〜（Ｃ）に従来の技術の例を示す。[Conventional technology] Examples of conventional techniques are shown in FIGS. 2(A) to 2(C).

第２図（Ａ）は集積回路装置におけるワイヤボンディン
グを行うためのポンディングパッドの構造を示す、シリ
コン等の半導体チップ５１の表面には５ｉ０２膜５２か
らなる絶縁膜が形成されている。アルミニウム層５３は
半導体チップ５１の内部から延在し、周辺部でポンディ
ングパッドとなる拡大した領域を形成しいる。このアル
ミニウム層５３を覆って、ホスホシリゲートガラス（Ｐ
ＳＧ）膜５４か形成されて、さらにその上を窒化シリコ
ン（ＳｉＮ）膜５５か覆って保護膜を形成している。ポ
ンディングパッドにおいては、これら保護膜５４．５５
をエツチングして開口５６を形成している。この開口５
６内でボンディングワイヤ５９のボール５８をアルミニ
ウム層５３に圧着して接続を形成する。FIG. 2A shows the structure of a bonding pad for wire bonding in an integrated circuit device. An insulating film made of a 5i02 film 52 is formed on the surface of a semiconductor chip 51 made of silicon or the like. The aluminum layer 53 extends from inside the semiconductor chip 51 and forms an enlarged area at the periphery that serves as a bonding pad. This aluminum layer 53 is covered with phosphosiligate glass (P).
A silicon nitride (SiN) film 54 is formed, and a silicon nitride (SiN) film 55 is further covered thereon to form a protective film. In the bonding pad, these protective films54.55
The opening 56 is formed by etching. This opening 5
6, the ball 58 of the bonding wire 59 is crimped onto the aluminum layer 53 to form a connection.

このようなポンディングパッドが使用される半導体装置
の例を第２図（Ｂ）、（Ｃ）を参照して説明する。An example of a semiconductor device using such a bonding pad will be described with reference to FIGS. 2(B) and 2(C).

第２図ＣＢ）はリードフレーム上に半導体チップをマウ
ントし、半導体チップ上のポンディングパッドとリード
フレームのリードとをボンディングワイヤで接続する構
造を示す平面図である１図において、リードフレームの
ダイパッド６１に近゛接して複数のり−ド６２が配置さ
れている。集積回路（ＩＣ）チップ６０がダイパッド６
１の上にダイス付は材によってダイス付けされている。Figure 2 CB) is a plan view showing a structure in which a semiconductor chip is mounted on a lead frame and bonding pads on the semiconductor chip and leads of the lead frame are connected with bonding wires. A plurality of boards 62 are arranged adjacent to the board 61 . An integrated circuit (IC) chip 60 is a die pad 6
The die attached on top of 1 is attached with a die depending on the material.

ＩＣチップ６０の表面周辺部には、複数のポンディング
パッド６５が設けられている。これらのポンディングパ
ッド６５とリード６２との間を金（Ａｕ）等のボンディ
ングワイヤ６３が接続している。A plurality of bonding pads 65 are provided around the surface of the IC chip 60 . Bonding wires 63 made of gold (Au) or the like are connected between these bonding pads 65 and leads 62.

第２図（Ｃ）は樹脂モールドの半導体集積回路装置を概
略的に示す、第２図（Ｂ）に示したような、ダイバンド
６１上に載置したＩＣチップ６０かモールド樹脂６４内
にモールドされている。モールド樹脂６４は５ｉ０２等
のフィシを含むエポキシ樹脂等で形成されている。FIG. 2(C) schematically shows a resin-molded semiconductor integrated circuit device. As shown in FIG. 2(B), an IC chip 60 placed on a die band 61 or molded in a molding resin 64 is shown. ing. The mold resin 64 is made of an epoxy resin containing 5i02 or the like.

モールド樹脂６４は水分を吸収する吸湿性を有する。外
部から吸収された水分はＩＣチップ６０の表面に到達す
る。第１図（Ａ）に示したポンディングパッドの部分で
は、開口５６においてＰＳＧ膜５４が側壁を露出してい
る。モールド樹脂はこの側壁に接触することになる。モ
ールド樹脂を通って水分がｐｓｃ、ｇ５４に到達すると
、ＰＳＧ膜５４から燐が溶は出す、このようにして、燐
酸か形成されると、露出しているアルミニウム層５３を
腐蝕する。The mold resin 64 has a hygroscopic property that absorbs moisture. Moisture absorbed from the outside reaches the surface of the IC chip 60. In the portion of the bonding pad shown in FIG. 1(A), the sidewall of the PSG film 54 is exposed in the opening 56. The mold resin will come into contact with this side wall. When moisture reaches psc, g54 through the molding resin, phosphorus is dissolved from the PSG film 54. In this way, phosphoric acid is formed and corrodes the exposed aluminum layer 53.

［発明か解決しようとする課題］ 以上説明したように、ポンディングパッド部において、
ＰＳＧＭ５４が露出していると、水分が侵入した時に燐
が溶は出し、アルミニウム層を腐蝕する等の故障を発生
させる。[Problem to be solved by the invention] As explained above, in the bonding pad section,
If the PSGM 54 is exposed, phosphorus will dissolve when moisture enters, causing failures such as corrosion of the aluminum layer.

本発明の目的は、耐湿性に優れたポンディングパッドを
有する半導体装置を提供することである。An object of the present invention is to provide a semiconductor device having a bonding pad with excellent moisture resistance.

［課題を解決するための手段］ 本発明によれば、ポンディングパッド部分においても、
表面保護層の側面がモールド樹脂と直接接触しないよう
に構成される。[Means for Solving the Problems] According to the present invention, also in the bonding pad portion,
The side surface of the surface protective layer is configured so as not to come into direct contact with the mold resin.

第１図（Ａ）、（Ｂ）は本発明の原理説明図である。FIGS. 1A and 1B are diagrams explaining the principle of the present invention.

第１図（Ａ＞を参照して説明すると、半導体基板１の表
面は第１絶縁膜２によって覆われており、その上に回路
部分から延在するアルミニウム層からなる下層パッド部
３が配置されている。この下層パッド部３を覆って表面
絶縁層４．５が形成されている０表面絶縁層はたとえば
、ＰＳＧ膜４とＳｉＮ膜５とからなる。この表面絶縁層
４．５は所定形状の開口６を有する０図示の場合には、
周辺で画定される開口６内に別に表面絶縁層４５゛の島
が残されている。この開目６全ように金属層からなる上
層パッド部７が形成される．上層パッド部７は表面絶縁
層４、５、４５“の露出した側面を覆うように形成する
．この上層パッド部７の露出表面を覆うようにボンディ
ングワイヤ９のボール部分８が圧着される．上層パッド
部７は開口部の形状によって凹凸ある表面を形成してい
る．ボンディングワイヤ９のボール８はこの凹凸に従う
係合面を形成する。To explain with reference to FIG. 1 (A>), the surface of the semiconductor substrate 1 is covered with a first insulating film 2, and a lower pad portion 3 made of an aluminum layer extending from the circuit portion is arranged on top of the first insulating film 2. A surface insulating layer 4.5 is formed to cover this lower pad portion 3. The surface insulating layer 4.5 is formed of, for example, a PSG film 4 and a SiN film 5. This surface insulating layer 4.5 has a predetermined shape. In the case shown in FIG. 0 having an opening 6 of
Another island of surface insulating layer 45' is left within the opening 6 defined at the periphery. An upper layer pad portion 7 made of a metal layer is formed over the entire opening 6. The upper layer pad portion 7 is formed to cover the exposed side surfaces of the surface insulating layers 4, 5, 45''.The ball portion 8 of the bonding wire 9 is crimped to cover the exposed surface of the upper layer pad portion 7.The upper layer The pad portion 7 forms an uneven surface due to the shape of the opening.The ball 8 of the bonding wire 9 forms an engagement surface that conforms to this unevenness.

第１図（Ｂ）においては、半導体基板１の表面に第１絶
縁膜２が形成され、その上に下層パッド部３が形成され
る点は第１図（Ａ）と同様である。In FIG. 1(B), the first insulating film 2 is formed on the surface of the semiconductor substrate 1, and the lower pad portion 3 is formed thereon, similar to FIG. 1(A).

表面絶縁層４、５は開口６を有する．この開口部内には
表面絶縁層の島領域は存在しない．開口６内に上層パッ
ド部７が凹凸のある表面を形成するように配置されてい
る．開口６において露出しな表面絶縁層４、５の側面を
覆うように、ボンディングワイヤ９のボール、部分８が
圧着されている。The surface insulating layers 4 and 5 have openings 6. There are no island regions of the surface insulating layer within this opening. An upper layer pad portion 7 is arranged within the opening 6 so as to form an uneven surface. The ball portion 8 of the bonding wire 9 is crimped so as to cover the side surfaces of the surface insulating layers 4 and 5 that are not exposed in the opening 6.

ボール８はまた上層パッド部７と下層パッド部３か形成
する凹凸ある表面に従う係合面を形成する。The ball 8 also forms an engagement surface that follows the uneven surface formed by the upper pad portion 7 and the lower pad portion 3.

［作用］ 表面絶縁層４、５の側面は、第１図（Ａ＞においては上
層パッド部、第１図（Ｂ）においてはボンディングワイ
ヤ９のボール部分８によって覆われモールド樹脂とは直
接接触しない．従って、モールド樹脂を浸透してきた水
分は表面絶縁層４、５の露出した側壁には到達しない．
たとえば、表面保護層４、５がＰＳＧ層４とＳｉＮ層５
からなる時、モールド樹脂中の水分はＰＳＧ層４に到達
できず、ＰＳＧ層４から燐が溶は出すことが防止できる
．このようにして、ポンディングパッドのアルミニウム
層の腐蝕が防止できる。[Function] The side surfaces of the surface insulating layers 4 and 5 are covered by the upper layer pad portion in FIG. 1 (A>) and by the ball portion 8 of the bonding wire 9 in FIG. 1 (B), and do not come into direct contact with the mold resin. Therefore, the moisture that has permeated the mold resin does not reach the exposed side walls of the surface insulating layers 4 and 5.
For example, the surface protective layers 4 and 5 are PSG layer 4 and SiN layer 5.
When the mold resin is made of PSG, moisture in the mold resin cannot reach the PSG layer 4, and phosphorus can be prevented from dissolving from the PSG layer 4. In this way, corrosion of the aluminum layer of the bonding pad can be prevented.

また、上層パッド部７は凹凸のある表面を有する．ボン
ディングワイヤ９のボール部分８が凹凸のある上層パッ
ド部７の表面と接触する．このため、ボンディングワイ
ヤ９の接着力は増強される。Further, the upper pad portion 7 has an uneven surface. The ball portion 8 of the bonding wire 9 comes into contact with the uneven surface of the upper layer pad portion 7. Therefore, the adhesive strength of the bonding wire 9 is enhanced.

［実施例コ 第３図（Ａ）、（Ｂ）は第１種の実施例によるポンディ
ングパッド構造を示す。Embodiment FIGS. 3A and 3B show a bonding pad structure according to the first embodiment.

第３図（Ａ）において、シリコン基板１１の表面はＳｉ
０　２　Ｈ　１　２によって覆われている，５１０２膜
１２の上に回路部分の配線から連続するアルミニウム層
からなる下層パッド部１３が形成されている．下層パッ
ド部１３の表面はＰＳＧ膜１膜上４ｉＮ膜１５によって
覆われ、開口部１６においてその表面が露出している．
開口部１６において露出しているＰＳＧｇ！１４の側壁
を密閉するようにアルミニウム層からなる上層パッド部
１７が開口１６を内包する面積上に形成されている．こ
の上層パッド部１７は表面保護膜１４、１５の開口１６
の段差形状に従った形状を有する．すなわち、上層パッ
ド部１７の表面は表面保護ＷＡ１４、１５の部分で持ち
上がり、凹凸を有する．この上層パッド部１７を覆い包
むようにボンディングワイヤ１つのボール１８が圧着さ
れている。In FIG. 3(A), the surface of the silicon substrate 11 is made of Si.
On the 5102 film 12 covered with 0 2 H 1 2, a lower pad portion 13 made of an aluminum layer is formed which is continuous from the wiring of the circuit portion. The surface of the lower pad portion 13 is covered with the 4iN film 15 on the PSG film 1, and is exposed at the opening 16.
PSGg exposed in opening 16! An upper layer pad portion 17 made of an aluminum layer is formed on an area including the opening 16 so as to seal the side wall of the opening 14. This upper layer pad portion 17 is connected to the opening 16 of the surface protection films 14 and 15.
It has a shape that follows the step shape. That is, the surface of the upper pad portion 17 is raised at the surface protection WA 14, 15 and has an uneven surface. A ball 18 of a bonding wire is crimped so as to cover and wrap this upper layer pad portion 17 .

たとえば、ボンディングワイヤ１９のボール１８は約７
０〜８０μｍの直径を有し、上層パッド部１７はボール
１８に完全に覆われる形状、たとえば約５０μｍの直径
を有する．開口１６はさらに片側で３μｍ程度小さくな
る寸法を有する．ボンディングワイヤ１９は金（Ａｕ）
またはＡｕ合金から形成される．上層パッド部１７は、
たとえば約５０００人〜１μｍの厚さを有するアルミニ
ウム層で形成される．下層パッド部１３はアルミニウム
ないしはアルミニウムを主成分とするアルミニウム合金
で構成される。For example, the ball 18 of the bonding wire 19 is about 7
The upper pad portion 17 has a shape that is completely covered by the ball 18, and has a diameter of about 50 μm, for example. The opening 16 has a dimension that is further reduced by about 3 μm on one side. Bonding wire 19 is gold (Au)
Or made of Au alloy. The upper pad portion 17 is
For example, it is formed of an aluminum layer having a thickness of about 5000 to 1 μm. The lower pad portion 13 is made of aluminum or an aluminum alloy containing aluminum as a main component.

このような構造が、エポキシ樹脂等のモールド樹脂中に
モールドされた場合、モールド樹脂を通って侵入してく
る水分はボンディングワイヤ１つおよび表面のＳｉＮ膜
１５には到達できるが、ＰＳＧ膜１膜上４到達できない
．従って、ＰＳＧ膜１膜上４が溶は出してアルミニウム
配線層を腐蝕することがない。When such a structure is molded in a mold resin such as epoxy resin, moisture that enters through the mold resin can reach one bonding wire and the SiN film 15 on the surface, but one PSG film can reach one bonding wire and the SiN film 15 on the surface. I can't reach the top 4. Therefore, the upper layer 4 of the PSG film 1 does not melt and corrode the aluminum wiring layer.

第３図（Ｂ）は、他の形態を示す．開口１６は第３図（
Ａ）と同様の形状を有するが、開口１６の内にさらに表
面保護層１４°、１５°のパターンが残されており、周
辺部で画定される開口１６と残された表面保護層１４°
　１５°のパターンによって下層パッド部１３の露出す
る実効的開口部分１６′を画定する構成である。別の見
方をすれば、実効的開口１６゛が複数の輪郭線によって
画定されている。上層パッド部１７はこの開口１６を覆
って形成される。このため、下地形状に従った凹凸表面
が形成される。ボンディングワイヤ１９のホール１８は
この凹凸のある上層パッド１７の表面に圧着される。従
って、上層パッド部１７とボンディングワイヤ１つとの
接着力は増強する。FIG. 3(B) shows another form. The opening 16 is shown in FIG.
It has the same shape as A), but a pattern of 14° and 15° of the surface protective layer is left inside the opening 16, and the pattern of the opening 16 defined by the periphery and the remaining surface protective layer 14° are left.
In this configuration, an effective opening portion 16' through which the lower pad portion 13 is exposed is defined by a 15° pattern. Viewed from another perspective, the effective aperture 16' is defined by a plurality of contour lines. Upper layer pad portion 17 is formed to cover this opening 16. Therefore, an uneven surface conforming to the underlying shape is formed. The hole 18 of the bonding wire 19 is pressed onto the uneven surface of the upper layer pad 17. Therefore, the adhesive force between the upper layer pad portion 17 and one bonding wire is enhanced.

第３図（Ｂ）の構造においては、開口１６内に残された
表面保護膜１４’、１５°のパターンによる凹凸の分、
ボンディングワイヤ１９の接着力が増強する。In the structure of FIG. 3(B), the surface protection film 14' left in the opening 16 has unevenness due to the 15° pattern.
The adhesive force of the bonding wire 19 is enhanced.

第４図（Ａ）〜（Ｅ）はポンディングパッド部分の平面
パターンの例を示す、これらのポンディングパッドにお
いては、表面保護膜に開口が形成され、開口の内部に表
面保護膜のパターンが残される。露出される下層パッド
部をハツチングされた領域で示す。Figures 4 (A) to (E) show examples of planar patterns of the bonding pad portions. In these bonding pads, openings are formed in the surface protective film, and the pattern of the surface protective film is inside the openings. left behind. The exposed lower pad portion is indicated by a hatched area.

第４図（Ａ）は、矩形状の開口２１内にマトリクス状に
表面保護膜のパターン２２が残される形状である４たと
えば、矩形開口２１は約４５〜５５μｍ角の正方形であ
り、マトリクス状パターン２２の小単位は約２μｍ角の
正方形である。マトリクスの元の数は簡略化して示しで
ある。FIG. 4(A) shows a shape in which a pattern 22 of a surface protective film is left in a matrix in a rectangular opening 21.4 For example, the rectangular opening 21 is a square approximately 45 to 55 μm square, and the matrix pattern is The 22 small units are approximately 2 μm square. The number of elements in the matrix is shown in a simplified manner.

第４図（Ｂ）は矩形状の開口２１内に連続したパターン
２４で表面保護膜が残される。１回生の折り返しパター
ンを示したが、種々の形状を採用できる。In FIG. 4(B), a surface protective film is left in a continuous pattern 24 within the rectangular opening 21. In FIG. Although a first folding pattern is shown, various shapes can be adopted.

第４図（Ｃ）は、矩形開口ではなく、円形の開口２５を
有し、この開口２５内にマトリクス状の表面保護膜パタ
ーン２２が分散されている形態を示す、開口２５は、た
とえば直径５０〜６０μｍ程度の円であるマトリクス状
パターン２２は、たとえば１辺２μｍ程度の正方形の集
合である。数は任意に選べる。FIG. 4(C) shows a configuration in which a circular opening 25 is used instead of a rectangular opening, and a matrix-like surface protective film pattern 22 is dispersed within the opening 25. The opening 25 has a diameter of, for example, 50 mm. The matrix pattern 22, which is a circle with a diameter of about 60 μm, is, for example, a collection of squares with a side of about 2 μm. You can choose any number.

第４図（Ｄ）は、円形の開口２５内に円周方向のパター
ン２６が残される形態である０図では二重の円周方向パ
ターンを示したが、三重以上であっても、また単一の環
状パターンであってもよい。FIG. 4(D) shows a form in which a circumferential pattern 26 is left inside the circular opening 25. Although FIG. It may be a single circular pattern.

分割の数も任意に増減できる。The number of divisions can also be increased or decreased as desired.

第４図（Ｅ）は円形開口２５内に放射状のパターン２８
で表面保護膜が残される形態を示す、放射パターンは半
径方向に分割されてもよい９円周方向にいくつのパター
ンを配置するかも任意に選べる。FIG. 4(E) shows a radial pattern 28 inside the circular opening 25.
The radiation pattern may be divided in the radial direction.9 The number of patterns to be arranged in the circumferential direction can also be arbitrarily selected.

ポンディングパッドの開口内に残される表面保護膜のパ
ターンを幾つか示したが、これらを組み合わせること、
変更すること等は当業者に自明であろう。We have shown several patterns of the surface protective film left inside the opening of the bonding pad, but by combining these,
Modifications and the like will be obvious to those skilled in the art.

第５図（Ａ）〜（Ｃ）は他の実施例によるボンディング
バンド構造の製造方法を示す断面図である。FIGS. 5A to 5C are cross-sectional views showing a method of manufacturing a bonding band structure according to another embodiment.

第５図（Ａ）において、シリコン基板１１の表面にはＳ
ｈｏ　ｚ　Ｊｌｌ　１２が形成されており、その上に内
部回路から連続するアルミニウム層からなる下層パッド
部１３がバターニングされている。この下層パッド部１
３を覆、うように表面保護膜３１が形成され、所定パタ
ーンの開口３２が設けられている。所定パターンの開口
３２は、たとえば第４図（Ａ）〜（Ｅ）に示したような
パターンである。In FIG. 5(A), the surface of the silicon substrate 11 is S
A lower pad portion 13 made of an aluminum layer continuous from the internal circuit is patterned thereon. This lower layer pad part 1
A surface protective film 31 is formed to cover the surface of the substrate 3, and openings 32 of a predetermined pattern are provided. The predetermined pattern of openings 32 is, for example, a pattern as shown in FIGS. 4(A) to 4(E).

第５図（Ｂ）に示すように、この開ロバターン３２によ
って露出された下層パッド部１３の表面に、たとえば金
（Ａｕ）等のバリアメタル層３４をメツキによって堆積
する。As shown in FIG. 5B, a barrier metal layer 34 of, for example, gold (Au) is deposited by plating on the surface of the lower pad portion 13 exposed by the open pattern 32. As shown in FIG.

その後、第５図（Ｃ）に示すように、開口内の表面保護
層３１をエツチングして除去する。すなわち、開口内に
はバリアメタル層３４のパターンが残る。このバリアメ
タル層３４が上層パッド部を構成する。Thereafter, as shown in FIG. 5(C), the surface protective layer 31 within the opening is removed by etching. That is, the pattern of the barrier metal layer 34 remains within the opening. This barrier metal layer 34 constitutes an upper layer pad section.

このように、パターン化された上層パッド部３４を有す
るポンディングパッドにボンディングワイヤのボールを
圧着して、第１図（Ｂ）に示すような構造を作成する０
表面保護層３１は、たとえばＰＳＧとＳｉＮの積層から
なる。この構造によれば、表面保護膜３１の側壁はほと
んどバリアメタル層３４によって覆われる。ＰＳＧ膜と
ＳｉＮ膜との積層構造の場合、下層となるＰＳＧ膜の側
壁はバリアメタル層３４によって覆われる。ボンディン
グワイヤのボールの圧着した状態では、バリアメタル層
３４はボンディングワイヤのボールによって覆われる。In this way, the ball of the bonding wire is crimped onto the bonding pad having the patterned upper layer pad portion 34 to create a structure as shown in FIG. 1(B).
The surface protection layer 31 is made of, for example, a stack of PSG and SiN. According to this structure, most of the sidewalls of the surface protection film 31 are covered with the barrier metal layer 34. In the case of a laminated structure of a PSG film and a SiN film, the sidewalls of the underlying PSG film are covered with a barrier metal layer 34. In the state where the bonding wire ball is pressed, the barrier metal layer 34 is covered by the bonding wire ball.

モールド樹脂中を侵入する水分は、まずボンゲインクワ
イヤのボール部分によってその進行を阻まれ、さらにバ
リアメタル層３４によって阻まれる。従って、水分はＰ
ＳＧ膜にはほとんど到達しなくなる。Moisture entering the mold resin is first blocked by the ball portion of the bonding wire, and further blocked by the barrier metal layer 34. Therefore, water is P
It almost never reaches the SG film.

このように、表面絶縁層の側壁はモールド樹脂から隔離
されるので、モールド樹脂中を水分が侵入してきも水分
の影響によってアルミニウム層の腐蝕が生じることが低
減する。In this way, the side walls of the surface insulating layer are isolated from the mold resin, so even if moisture enters the mold resin, corrosion of the aluminum layer due to the influence of moisture is reduced.

体装置が提供される。A body device is provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（Ａ）、（Ｂ）は本発明の原理説明図、第２図（
Ａ）〜（Ｃ）は従来の技術を示し、第２図（Ａ）はポン
ディングパッド部分の断面図、第２図（Ｂ）はリードフ
レーム上の半導体チップを示す平面図、第２図（Ｃ）は
樹脂モールドの構造を示す断面図、 第３図（Ａ＞、（Ｂ）は本発明のヰ実施例によるポンデ
ィングパッド構造を示す断面図、第４図（Ａ）〜（Ｅ）
はポンディングパッドの［発明の効果］ 以上説明したように、本発明によれば、表面絶縁層の側
壁かモールド樹脂に接触することなく、金属によって被
覆されるので、耐湿性の高い半導図において、 ■ 半導体基板 第１絶縁膜 ４、５ １ ２ ３ ４ ５ ６ ７ ８ ９ ２１、２５ ２２、２４、 下層パッド部 表面絶縁層 開口 上層パッド部 ボール部分 ボンディングワイヤ シリコン基板 ５ｉ０２膜 Ａｌｌ下層パッド部 ＰＳＧ膜 ｉＮ　ＷＡ 開口 アルミニウム上層パッド部 ボール ボンディングワイヤ 開口 ２６．２８ 表面絶縁膜のパターン （Ｂ）その２Figures 1 (A) and (B) are diagrams explaining the principle of the present invention, and Figure 2 (
A) to (C) show the conventional technology, FIG. 2(A) is a cross-sectional view of the bonding pad portion, FIG. C) is a cross-sectional view showing the structure of the resin mold, FIGS. 3(A> and (B)) are cross-sectional views showing the bonding pad structure according to the embodiment of the present invention, and FIGS. 4(A) to (E)
[Effects of the Invention] As explained above, according to the present invention, the side wall of the surface insulating layer is covered with metal without coming into contact with the molding resin, so the semiconductor pad has high moisture resistance. In, ■ Semiconductor substrate first insulating film 4, 5 1 2 3 4 5 6 7 8 9 21, 25 22, 24, lower layer pad portion surface insulating layer opening upper layer pad portion ball portion bonding wire silicon substrate 5i02 film All lower layer pad portion PSG film iN WA Opening Aluminum upper layer pad part Ball bonding wire opening 26.28 Surface insulating film pattern (B) Part 2

Claims (3)

【特許請求の範囲】[Claims] （１）、半導体基板（１）と、 該半導体基板（１）上に形成された第１絶縁膜（２）と
、 該第１絶縁膜（２）上に形成され、配線層に連続するア
ルミニウム層の下層パッド部（３）と、 該アルミニウム層の下層パッド部（３）の少なくとも周
辺部を覆い、下層パッド部（３）の１部表面を露出する
開口（６）を有する表面絶縁層（４、５）と、 該アルミニウム層の下層パッド部（３）上に形成され、
表面に凹凸を有する金属層の上層パッド部（７）と、 該上層パッド部（７）の露出表面を覆うボール部分（８
）を有するボンディングワイヤ（９）とを有する半導体
装置。(1), a semiconductor substrate (1), a first insulating film (2) formed on the semiconductor substrate (1), and an aluminum film formed on the first insulating film (2) and continuous to the wiring layer. a lower pad portion (3) of the aluminum layer; and a surface insulating layer (6) that covers at least the peripheral portion of the lower pad portion (3) of the aluminum layer and has an opening (6) that exposes a portion of the surface of the lower pad portion (3). 4, 5), formed on the lower pad portion (3) of the aluminum layer,
An upper pad part (7) of a metal layer having an uneven surface, and a ball part (8) covering the exposed surface of the upper pad part (7).
) A bonding wire (9) having a bonding wire (9). （２）、前記表面絶縁層（４、５）がホスホシリケート
ガラスの下層（４）とその上に配置されたカバー層（５
）の積層構造を含み、前記上層パッド部（７）が前記開
口（６）の側壁を覆っている請求項１記載の半導体装置
。(2), the surface insulating layers (4, 5) include a lower layer (4) of phosphosilicate glass and a cover layer (5) disposed thereon;
2. The semiconductor device according to claim 1, wherein the upper layer pad portion (7) covers a side wall of the opening (6). （３）、前記上層パッド部（７）が、前記開口（６）内
に露出された下層パッド部（３）の表面の１部上に形成
されている請求項１記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the upper layer pad section (7) is formed on a part of the surface of the lower layer pad section (3) exposed in the opening (6).
JP1292597A 1989-11-10 1989-11-10 Semiconductor device Pending JPH03153049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1292597A JPH03153049A (en) 1989-11-10 1989-11-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1292597A JPH03153049A (en) 1989-11-10 1989-11-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03153049A true JPH03153049A (en) 1991-07-01

Family

ID=17783846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1292597A Pending JPH03153049A (en) 1989-11-10 1989-11-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03153049A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05343466A (en) * 1992-06-11 1993-12-24 Mitsubishi Electric Corp Pad structure for semiconductor device
JPH09289224A (en) * 1995-12-30 1997-11-04 Samsung Electron Co Ltd Semiconductor chip, manufacturing method thereof and wire bonding method
US5891745A (en) * 1994-10-28 1999-04-06 Honeywell Inc. Test and tear-away bond pad design
US6809415B2 (en) * 1998-07-22 2004-10-26 Ibiden Co., Ltd. Printed-circuit board and method of manufacture thereof
USRE40819E1 (en) 1995-12-21 2009-07-07 Micron Technology, Inc. Semiconductor device with improved bond pads
JP2010171107A (en) * 2009-01-21 2010-08-05 Renesas Electronics Corp Semiconductor apparatus and method of manufacturing the same
JP2013171928A (en) * 2012-02-20 2013-09-02 Tdk Corp Multilayer terminal electrode and electronic component
CN107305872A (en) * 2016-04-19 2017-10-31 意法半导体(鲁塞)公司 The novel of porous dielectric premature breakdown is protected between preventing the line in integrated circuit
WO2023189480A1 (en) * 2022-03-31 2023-10-05 ローム株式会社 Semiconductor element and semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05343466A (en) * 1992-06-11 1993-12-24 Mitsubishi Electric Corp Pad structure for semiconductor device
US5891745A (en) * 1994-10-28 1999-04-06 Honeywell Inc. Test and tear-away bond pad design
USRE40819E1 (en) 1995-12-21 2009-07-07 Micron Technology, Inc. Semiconductor device with improved bond pads
JPH09289224A (en) * 1995-12-30 1997-11-04 Samsung Electron Co Ltd Semiconductor chip, manufacturing method thereof and wire bonding method
US6809415B2 (en) * 1998-07-22 2004-10-26 Ibiden Co., Ltd. Printed-circuit board and method of manufacture thereof
JP2010171107A (en) * 2009-01-21 2010-08-05 Renesas Electronics Corp Semiconductor apparatus and method of manufacturing the same
US8350392B2 (en) 2009-01-21 2013-01-08 Renesas Electronics Corporation Semiconductor device having recess with varying width and method of manufacturing the same
JP2013171928A (en) * 2012-02-20 2013-09-02 Tdk Corp Multilayer terminal electrode and electronic component
CN107305872A (en) * 2016-04-19 2017-10-31 意法半导体(鲁塞)公司 The novel of porous dielectric premature breakdown is protected between preventing the line in integrated circuit
CN107305872B (en) * 2016-04-19 2020-03-31 意法半导体(鲁塞)公司 Protection against premature breakdown of interline porous dielectrics in integrated circuits
WO2023189480A1 (en) * 2022-03-31 2023-10-05 ローム株式会社 Semiconductor element and semiconductor device

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