JPS63202943A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63202943A JPS63202943A JP62036467A JP3646787A JPS63202943A JP S63202943 A JPS63202943 A JP S63202943A JP 62036467 A JP62036467 A JP 62036467A JP 3646787 A JP3646787 A JP 3646787A JP S63202943 A JPS63202943 A JP S63202943A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- bump
- insulating film
- forming
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title description 6
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- 238000007747 plating Methods 0.000 claims abstract description 11
- 239000004094 surface-active agent Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000004020 conductor Substances 0.000 claims description 8
- 230000002265 prevention Effects 0.000 claims description 7
- 239000002184 metal Substances 0.000 abstract description 27
- 229910052751 metal Inorganic materials 0.000 abstract description 27
- 238000000034 method Methods 0.000 abstract description 9
- 238000002161 passivation Methods 0.000 abstract description 6
- 239000011248 coating agent Substances 0.000 abstract 2
- 238000000576 coating method Methods 0.000 abstract 2
- 230000006866 deterioration Effects 0.000 abstract 1
- 239000010931 gold Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910010977 Ti—Pd Inorganic materials 0.000 description 2
- 235000008429 bread Nutrition 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- WGCNASOHLSPBMP-UHFFFAOYSA-N hydroxyacetaldehyde Natural products OCC=O WGCNASOHLSPBMP-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- -1 nitrogen-containing compound Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002503 polyoxyethylene-polyoxypropylene Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
従来の半導体装置では、パッド電極上にパッシベーショ
ン膜の窓を介して形成した突起電極（以降バンプと称す
）は、第５図に示すような構造となっていた。In a conventional semiconductor device, a protruding electrode (hereinafter referred to as a bump) formed on a pad electrode through a window of a passivation film has a structure as shown in FIG.
この従来例は、半導体基板１上に絶縁膜２を介してＡｅ
を主成分とする厚さ１μｍ程度の所定のパターンの電極
３を形成し、電極３の周辺部を覆いかつ接続用開孔部を
有する厚さ０．５μｍ程度の絶縁膜４からなるパッシベ
ーション膜を形成し、バンプ７″と電極３との接着用及
び電極３のＡｆとバンプ金属である金との相互拡散を防
止する拡散防止用金属５及び６を順次形成し、更に、ホ
トリソグラフィ法と金などの電解メッキによりパン１７
″を形成した後パン１７″をマスクとして金属層５及び
６を除去する。このバンプの構造は、ホトリソグラフィ
法に用いるホトレジスト膜の厚さにもよるが、一般にマ
ツシュルーム形になる。しかし、このパン１７″の表面
の中央部は、絶縁膜４の膜厚分の段差により、周辺部よ
り凹み、しかもこの凹みは金のメッキなどのつきまわり
性から絶縁膜４の膜厚よりも大きくなるのが普通である
。In this conventional example, Ae
A passivation film consisting of an insulating film 4 of about 0.5 μm thick and covering the periphery of the electrode 3 and having connection openings is formed. Then, diffusion prevention metals 5 and 6 are sequentially formed for bonding the bump 7'' and the electrode 3 and for preventing mutual diffusion between Af of the electrode 3 and gold as the bump metal. Bread 17 by electrolytic plating such as
After forming the metal layers 5 and 6, the metal layers 5 and 6 are removed using the pan 17 as a mask. The structure of this bump is generally in the shape of a mushroom, although it depends on the thickness of the photoresist film used in the photolithography method. However, the central part of the surface of this pan 17'' is recessed from the peripheral part due to a step equal to the thickness of the insulating film 4, and furthermore, this recess is smaller than the thickness of the insulating film 4 due to the throwing power of gold plating. It is normal for it to grow larger.
ここで、接着用及び拡散防止用金属層５及び６は、各層
の厚さが１０００人程度のＴｉ−Ｐｄ層等の二層の他、
Ｃｒ−Ｃｕ−Ａｕ層のような三層のものでも良い。Here, the metal layers 5 and 6 for adhesion and diffusion prevention include two layers such as a Ti-Pd layer each having a thickness of about 1000 layers, and
A three-layer structure such as a Cr-Cu-Au layer may also be used.
上述した従来の半導体装置では、バンプ表面の中央部が
凹んでいるので、例えばＴＡＢ用方式の一括ボンディン
グ（以降ギヤングボンディングと称す）でリードを接続
しようとすると、ボンデイクの際の圧力と熱によりパン
１７″のリード１０との接続部分が変形し、第６図のよ
うにつぶれ、しかもバンプ周辺部の高い部分に最もスト
レスが加わると共に一番変形が大きくなり、その下の部
分から発生するクラック等により半導体装置の品質・信
頼性を著しく低下させるという欠点を有していた。In the conventional semiconductor device described above, the central part of the bump surface is recessed, so if you try to connect the leads by, for example, TAB type bulk bonding (hereinafter referred to as gigantic bonding), the pressure and heat during bonding will cause damage. The connection part of the bread 17'' to the lead 10 is deformed and crushed as shown in Figure 6, and the highest stress is applied to the high part around the bump and the deformation is the largest, and cracks occur from the part below. It has the disadvantage that the quality and reliability of semiconductor devices are significantly reduced due to the above reasons.
又、これを防止するために従来、バンプを絶縁膜の段差
の内側に形成するという方法が考えられたが、バンプを
マスクとした接着用及び拡散防止用金属層をエツチング
するときにその下の電極３の表面が露出してエツチング
液によりおかれることがあるため、そのままでは問題が
多く、それを解決しようとするとホトリソグラフィ工程
を追加する等により製造工程が非常に長くなり生産効率
が甚しく低下するという欠点があった。In order to prevent this, a conventional method has been considered to form bumps inside the step of the insulating film, but when etching the adhesive and diffusion prevention metal layer using the bumps as a mask, Since the surface of the electrode 3 may be exposed and exposed to the etching solution, there are many problems if left as is, and if we try to solve this problem, the manufacturing process will become extremely long due to the addition of a photolithography process, which will significantly reduce production efficiency. The disadvantage was that it decreased.
本発明の半導体装置の製造方法は、半導体基板表面に第
１の絶縁膜を介して所定のパターンの第１の導体層を形
成する工程、該第１の導体層上に第２の絶縁膜を形成す
る工程、該第２の絶縁膜の前記第１の導体層上の部分を
開孔して接続用の窓を形成する工程、該窓を覆う接着用
及び拡散防止用を含む少くとも二層の第２の導体層を形
成する工程及び表面活性剤を少くとも含むメッキ液によ
り前記第２の導体層上に突起電極を形成する工程を含み
、表面が平坦な前記突起電極を形成して成る。The method for manufacturing a semiconductor device of the present invention includes the step of forming a first conductive layer in a predetermined pattern on the surface of a semiconductor substrate via a first insulating film, and forming a second insulating film on the first conductive layer. a step of forming a connection window by opening a portion of the second insulating film on the first conductor layer; and at least two layers including an adhesion layer and a diffusion prevention layer that cover the window. and forming a protruding electrode on the second conductor layer using a plating solution containing at least a surfactant, the protruding electrode having a flat surface. .
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の半導体装置の第１の実施例を説明する
ための半導体チップの断面図である。FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of a semiconductor device of the present invention.
この実施例による半導体装置は、半導体基板１上に絶縁
膜２を介して例えばＡｅからなる所定のパターンの電極
３を形成し、電極３を覆うパッシベーション用の絶縁膜
４を形成した後この電極３上部に接続用の開孔部を設け
、電極３の露出面を覆う少なくとも二層の接着用及び拡
散防止用金属層５及び６を形成し、更にホトリソグラフ
ィ法と少くとも表面活性剤を添加したメッキ液と交流な
いしはパルス波形の印加電流とによって表面が平坦なバ
ンプ７を形成し、最後にボンディングを良好にるための
金属層８をバンプ７の露出面に形成した後バンプ７をマ
スクとしてホトリソグラフィ法で用いたホトレジスト膜
とその下の金属層５及び６を除去して形成している。In the semiconductor device according to this embodiment, an electrode 3 of a predetermined pattern made of, for example, Ae is formed on a semiconductor substrate 1 via an insulating film 2, and an insulating film 4 for passivation covering the electrode 3 is formed. A connecting hole was provided in the upper part, at least two adhesive and diffusion preventing metal layers 5 and 6 were formed to cover the exposed surface of the electrode 3, and a photolithography method and at least a surfactant were added. A bump 7 with a flat surface is formed by applying a plating solution and an applied current in an alternating current or pulsed waveform.Finally, a metal layer 8 is formed on the exposed surface of the bump 7 to improve bonding, and then photolithography is performed using the bump 7 as a mask. It is formed by removing the photoresist film used in the lithography method and the underlying metal layers 5 and 6.
ここで、バンプ７の表面に金属層８形成したのは、表面
活性剤を添加したメッキ液と交流又はパルス波形の印加
電流とによって形成したバンプ７は表面が滑らかで光沢
がありしかも硬度が高く直接ボンディングしにくいので
、ボンディングが良好に出来るようにしたためである。Here, the metal layer 8 was formed on the surface of the bump 7 by using a plating solution containing a surfactant and an applied current in an alternating current or pulsed waveform.The bump 7 has a smooth, glossy surface and high hardness. This is because direct bonding is difficult, so bonding can be done well.
第２図は本発明の半導体装置の第２の実施例を説明する
ための半導体チップの断面図である。FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the semiconductor device of the present invention.
この実施例による半導体装置は、第１図の半導体装置と
同様に半導体基板１上に順次、絶縁膜２、電極３及びパ
ッシベーション用の絶縁膜４を形成し、接着用及び拡散
防止用金属層５′及び６′を形成し、更に第１の実施例
と同様の方法により表面の平坦なバンプ７′を形成し、
パン１７′表面にボディングを良好にする金属層８ａ’
及び８ｂ’を順次形成した後パン１７′をマスクとして
金属層５′及び６′の所定の部分以外を除去して、形成
する。In the semiconductor device according to this embodiment, an insulating film 2, an electrode 3, and an insulating film 4 for passivation are sequentially formed on a semiconductor substrate 1, as in the semiconductor device shown in FIG. ' and 6' are formed, and further a bump 7' with a flat surface is formed by the same method as in the first embodiment,
Metal layer 8a' for good boarding on the surface of the pan 17'
After sequentially forming metal layers 5' and 8b', portions other than predetermined portions of metal layers 5' and 6' are removed using pan 17' as a mask.
ここで、パン１７′表面の金属層を８ａ’及び８ｂ’を
二層にしているのは、ボンディングの時の熱処理等によ
って金属層８ｂ’とパン７７′とが相互拡散するのを防
止するためである。Here, the reason why the metal layer 8a' and 8b' on the surface of the pan 17' is made into two layers is to prevent mutual diffusion between the metal layer 8b' and the pan 77' due to heat treatment during bonding, etc. It is.
第３図（ａ）〜（Ｃ）は本発明の半導体装置の製造方法
の一実施例を説明するための工程順に示した半導体チッ
プの断面図である。FIGS. 3A to 3C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention.
この実施例では、先ず、第３図（ａ）に示すように、半
導体基板１表面上に絶縁膜２を介して所定のパターンの
例えばＡ！からなる電極３を形成し、パッシベーション
用の絶縁膜４を形成してこれに接続用の開孔部を設けた
後例えばＣｒ−Ｃｕ又はＴ ｉ −Ｐ ｄ等からなる接
着用及び拡散防止用金属層５及び６を１０００〜２００
０人の厚さに形成する。ここで、金属層５及び６は、必
ずしも、二層に限るものではなく、接着用及び拡散防止
用の金属層を含んでいれば、二層以上になっても良い。In this embodiment, first, as shown in FIG. 3(a), a predetermined pattern, for example, A! After forming an electrode 3 consisting of a passivation insulating film 4 and providing an opening for connection thereto, an adhesive and diffusion prevention metal such as Cr-Cu or Ti-Pd is formed. layers 5 and 6 from 1000 to 200
Form to a thickness of 0 people. Here, the metal layers 5 and 6 are not necessarily limited to two layers, and may be two or more layers as long as they include a metal layer for adhesion and diffusion prevention.
次に、第３図（ｂ）に示すよう、絶縁膜４の開孔部より
広い窓を有する所定のパターンのホトレジスト膜９を形
成する。Next, as shown in FIG. 3(b), a photoresist film 9 having a predetermined pattern having a window wider than the opening of the insulating film 4 is formed.
次に、第３図（Ｃ）に示すように、ホトレジスト膜９を
マスクとして少くとも表面活性剤を添加したメッキ液乃
至交流又はパルス波形の印加電流等によって表面が平坦
なバンプ７を２０μｍ程度の厚さで形成する。ここで、
メッキ液としては、例えば銅メッキの場合、基本的には
、通常の硫酸銅と硫酸とを含む銅メッキ液にポリオキシ
エチレン−ポリオキシプロピレングリコール等の表面活
性剤及び２−メルカプトベンゾチマゾールー８−プロパ
ンスルホン酸などの硫黄含有化合物又は窒素含有化合物
などを添加したものを使用する。Next, as shown in FIG. 3(C), using the photoresist film 9 as a mask, the bumps 7 with flat surfaces are formed to a thickness of about 20 μm using a plating solution containing at least a surfactant or an applied current with an alternating current or pulse waveform. Form in thickness. here,
For example, in the case of copper plating, the plating solution is basically a copper plating solution containing copper sulfate and sulfuric acid, a surfactant such as polyoxyethylene-polyoxypropylene glycol, and 2-mercaptobenzothymazole. A compound containing a sulfur-containing compound such as 8-propanesulfonic acid or a nitrogen-containing compound is used.
第４図はバンプ表面の段差ｔの表面活性剤の添加量に対
する依存性を示す特性図である。FIG. 4 is a characteristic diagram showing the dependence of the step t on the bump surface on the amount of surfactant added.
これは、電流密度を一定として行なったもので、表面活
性剤の添加量が１．０ｍＭ（ミリモル）程度で、バンプ
の表面がほぼ平坦になっている。This was done with a constant current density, and the amount of surfactant added was about 1.0 mM (millimol), so the bump surface was almost flat.
最後に、バンプ７の表面にボンディングを良好にする１
μｍ程度の厚さの金属層８を形成した後バンブ７をマス
クとしてホトレジスト膜９．金属層６及び５を順次除去
すれば、本発明の半導体装置の第１の実施例ができる。Finally, add 1 to improve bonding on the surface of bump 7.
After forming a metal layer 8 with a thickness of approximately μm, a photoresist film 9 is applied using the bump 7 as a mask. By sequentially removing metal layers 6 and 5, a first embodiment of the semiconductor device of the present invention can be obtained.
従って、本発明では、例えばバンプ金属を光沢のある金
を２０μｍ程度、そして表面金属層を無光沢の硬度の低
い金というメッキ条件の異なる二層構造のものやバンプ
金属を銅とし、表面金属層をハンダまたは金とするよう
な構造ものが可能になる。Therefore, in the present invention, for example, a two-layer structure with different plating conditions, in which the bump metal is made of shiny gold with a thickness of about 20 μm and the surface metal layer is matte, low-hardness gold, or the bump metal is copper, and the surface metal layer is made of copper. It becomes possible to create structures using solder or gold.
以上説明したように本発明は、表面の平坦なバンプを形
成することにより、表面段差による半導体チップのクラ
ック発生を防止して品質・信頼性を非常に改善すると共
にバンプとバンプ表面の金属層との光沢・硬度を変えた
りあるいは材料そのものを変えるなどしてボンディング
が良好に出来てしかもコストが安いバンプ等、目的に応
じた柔軟性のあるバンプ構造を実現できるという効果が
ある。As explained above, the present invention prevents cracks in semiconductor chips due to surface steps by forming bumps with flat surfaces, greatly improves quality and reliability, and improves the quality and reliability of semiconductor chips by forming bumps with flat surfaces. By changing the gloss and hardness of the material, or by changing the material itself, it is possible to realize a bump structure that is flexible depending on the purpose, such as a bump that can be bonded well and is inexpensive.
【図面の簡単な説明】
第１図及び第２図はそれぞれ本発明の半導体装置の第１
及び第２の実施例を説明するための半導体チップの断面
図、第３図（ａ）〜（Ｃ）は本発明の半導体装置の製造
方法の一実施例を説明するための工程順に示した半導体
チップの断面図、第４図はバンプ表面の段差上の表面活
性剤の添加量に対する依存性を示す特性図、第５図及び
第６図はそれぞれ従来の半導体装置の一例及びその使用
例を示す断面図である。
１・・・半導体基板、２・・・絶縁膜、３・・・電極、
４・・・絶縁膜、５．５’ 、６．６’・・・金属層、
７．７’。
７ ”−・・バンプ、８．８ａ’ 、８ｂ’−金属層、
９・・・ホトレジスト膜、１０・・・リード、１１・・
・クラック、ｔ・・・段差。
第３図[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 and 2 each show a first diagram of a semiconductor device of the present invention.
3(a) to 3(C) are cross-sectional views of a semiconductor chip for explaining a second embodiment, and FIGS. A cross-sectional view of the chip, FIG. 4 is a characteristic diagram showing the dependence on the amount of surfactant added on the step on the bump surface, and FIGS. 5 and 6 show an example of a conventional semiconductor device and an example of its use, respectively. FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... Electrode,
4... Insulating film, 5.5', 6.6'... Metal layer,
7.7'. 7”--bump, 8.8a', 8b'-metal layer,
9... Photoresist film, 10... Lead, 11...
・Crack, t...step. Figure 3
Claims (1)
ンの第１の導体層を形成する工程、該第１の導体層上に
第２の絶縁膜を形成する工程、該第２の絶縁膜の前記第
１の導体層上の部分を開孔して接続用の窓を形成する工
程、該窓を覆う接着用及び拡散防止用を含む少くとも二
層の第２の導体層を形成する工程及び表面活性剤を少く
とも含むメッキ液により前記第２の導体層上に突起電極
を形成する工程を含み、表面が平坦な前記突起電極を形
成することを特徴とする半導体装置の製造方法。a step of forming a first conductor layer in a predetermined pattern on the surface of a semiconductor substrate via a first insulating film; a step of forming a second insulating film on the first conductor layer; and a step of forming a second insulating film on the first conductor layer. a step of forming a connection window by opening a hole on the first conductor layer; a step of forming at least two second conductor layers, including one for adhesion and one for diffusion prevention, covering the window; and a step of forming a protruding electrode on the second conductor layer using a plating solution containing at least a surfactant, and forming the protruding electrode with a flat surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62036467A JPS63202943A (en) | 1987-02-18 | 1987-02-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62036467A JPS63202943A (en) | 1987-02-18 | 1987-02-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63202943A true JPS63202943A (en) | 1988-08-22 |
Family
ID=12470616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62036467A Pending JPS63202943A (en) | 1987-02-18 | 1987-02-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63202943A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7735713B2 (en) * | 2005-12-21 | 2010-06-15 | Tdk Corporation | Method for mounting chip component and circuit board |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59195847A (en) * | 1983-04-21 | 1984-11-07 | Matsushita Electronics Corp | Fabrication of electrode having bump structure |
| JPS6081893A (en) * | 1983-10-11 | 1985-05-09 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Method of electrolessly plating copper selectively on surface of nonconductive substrate |
| JPS61217580A (en) * | 1985-03-20 | 1986-09-27 | Sumitomo Metal Mining Co Ltd | Chemical copper plating solution and chemical copper plating method |
-
1987
- 1987-02-18 JP JP62036467A patent/JPS63202943A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59195847A (en) * | 1983-04-21 | 1984-11-07 | Matsushita Electronics Corp | Fabrication of electrode having bump structure |
| JPS6081893A (en) * | 1983-10-11 | 1985-05-09 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Method of electrolessly plating copper selectively on surface of nonconductive substrate |
| JPS61217580A (en) * | 1985-03-20 | 1986-09-27 | Sumitomo Metal Mining Co Ltd | Chemical copper plating solution and chemical copper plating method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7735713B2 (en) * | 2005-12-21 | 2010-06-15 | Tdk Corporation | Method for mounting chip component and circuit board |
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