JPS6341050A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6341050A JPS6341050A JP61185545A JP18554586A JPS6341050A JP S6341050 A JPS6341050 A JP S6341050A JP 61185545 A JP61185545 A JP 61185545A JP 18554586 A JP18554586 A JP 18554586A JP S6341050 A JPS6341050 A JP S6341050A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxide film
- forming
- mask
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000007747 plating Methods 0.000 claims abstract description 10
- 230000001681 protective effect Effects 0.000 claims abstract description 8
- 238000009713 electroplating Methods 0.000 claims abstract description 7
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 5
- 238000007772 electroless plating Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 19
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 19
- 239000010936 titanium Substances 0.000 abstract description 18
- 238000005530 etching Methods 0.000 abstract description 13
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 abstract description 11
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 abstract description 11
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 27
- 239000010931 gold Substances 0.000 description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910018054 Ni-Cu Inorganic materials 0.000 description 1
- 229910018481 Ni—Cu Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000009331 sowing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に半導体チッ
プの外部接続用電極としての突起型電極の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a protruding electrode as an electrode for external connection of a semiconductor chip.
従来、突起型電極（以下バンプという）を有する半導体
装置においては、半導体チップ上の配線層のアルミニウ
ムパッド上に金（Ａｕ）等の金属材でバンプを形成した
構成となっており、このバンプとアルミニウムパッドの
接着性を高める一方、バンプとアルミニウムパッド間で
の拡散を防ぐために両者間に接着層や障壁層を介挿させ
ている。Conventionally, a semiconductor device having a protruding electrode (hereinafter referred to as a bump) has a structure in which a bump is formed of a metal material such as gold (Au) on an aluminum pad of a wiring layer on a semiconductor chip. While increasing the adhesion of the aluminum pad, an adhesive layer or barrier layer is interposed between the bump and the aluminum pad to prevent diffusion between the bump and the aluminum pad.
以下その製造方法を第２図（ａ）〜（ｄ）を用いて説明
する。The manufacturing method will be explained below using FIGS. 2(a) to 2(d).
まず第２図（ａ）に示すようにシリコン基板１上に形成
された酸化シリコン膜等の絶縁膜２上に電極形成用のア
ルミニウム膜をたとえば１．０μｍ程度の厚さで被着せ
しめ、パッド部及び内部配線部を残し、その他の部分を
選択的に除去する。First, as shown in FIG. 2(a), an aluminum film for forming an electrode is deposited to a thickness of about 1.0 μm on an insulating film 2 such as a silicon oxide film formed on a silicon substrate 1, and a pad The remaining portions and internal wiring portions are left, and the other portions are selectively removed.
しかる後ＣＶＤ法で形成した酸化シリコン膜等の保護絶
縁膜４を全面に被着し、パッド部上に開口部５を形成し
てアルミニウムパッド３を形成する。Thereafter, a protective insulating film 4 such as a silicon oxide film formed by a CVD method is deposited over the entire surface, and an opening 5 is formed on the pad portion to form an aluminum pad 3.
次に第２図（ｂ）に示すように、Ｔｉ膜６及びＡ ｕ
膜７をスパッタ法等により全面に形成する。Next, as shown in FIG. 2(b), the Ti film 6 and Au
A film 7 is formed over the entire surface by sputtering or the like.
この接着層及び障壁層としての多層膜はＴｉ−ＡＵの他
に、Ｃｒ−Ｃｕ、Ｎｉ−Ｃｕ、Ｃｒ−Ｃｕ−Ａｕ、Ｔｉ
−Ｐｔ等を用いることができる。This multilayer film as an adhesive layer and a barrier layer includes Ti-AU, Cr-Cu, Ni-Cu, Cr-Cu-Au, Ti.
-Pt etc. can be used.
次に第２図（ｃ）に示すようにＴｉ膜膜上上ホトレジス
ト層を形成したのち、アルミニウムパッド３上の一部を
選択的に開口したマスク８を形成する。続いてＴｉ膜６
及びＡｕ膜７を給電電極とする電解めっき法によりＡｕ
を厚さ２０μｍ程度にめっきしアルミニウムパッド３上
にＡｕバンブ１０を形成する。Ａｕの代りにＣ＋１やは
んだ等も用いられる。Next, as shown in FIG. 2(c), a photoresist layer is formed on the Ti film, and then a mask 8 is formed which selectively opens a part of the aluminum pad 3. Next, Ti film 6
And Au by electrolytic plating method using Au film 7 as a power supply electrode.
Au bumps 10 are formed on the aluminum pads 3 by plating them to a thickness of about 20 μm. C+1, solder, etc. can also be used instead of Au.
次に第２図（ｄ）に示すように、マスク８を除去したの
ちＡ ＩＪバンブ１０をマスクとして不要のＡｕ膜７及
びＴｉ膜６をエツチングし除去することによりＡｕバン
ブ１０を有する半導体装置が完成する。Next, as shown in FIG. 2(d), after removing the mask 8, the unnecessary Au film 7 and Ti film 6 are etched and removed using the A IJ bump 10 as a mask, thereby forming a semiconductor device having the Au bump 10. Complete.
上述した従来の半導体装置の製造方法ではＡｕバンブ１
０の形成後にＡ １１バンブをマスクとして多層膜を構
成する金属層をそれぞれエンチングすることになる。In the conventional semiconductor device manufacturing method described above, the Au bump 1
After forming the A11 bump, each of the metal layers constituting the multilayer film is etched using the A11 bump as a mask.
バンプの金属としてはＡ ｕが主に用いられる。Au is mainly used as the metal of the bump.
又、多層膜の金属として最上層にＡｕを用いることが多
いが、この場合薄いＡｕ層７をＡｕバンブ１０をマスク
としてエツチングすることになる。Furthermore, Au is often used as the uppermost layer of the metal in a multilayer film, but in this case the thin Au layer 7 is etched using the Au bumps 10 as a mask.
このような場合は、エツチング後の表面状態をよくする
ために適度のオーバーエツチングを行うが、この時Ａｕ
バンブ１０の側面がエツチングされ、保護絶縁膜４上に
Ａｕバンプ１ｏが残らない形状となる。この状態で下層
の金属膜であるＴｉ膜６をエツチングすると、Ｔｉ膜６
のエツチングに伴なって、アルミニウムパッド３までが
エツチングされて電気的に不良となり半導体装置の信頼
性を低下させるという問題点があった。In such cases, moderate overetching is performed to improve the surface condition after etching, but at this time, the Au
The side surfaces of the bumps 10 are etched so that no Au bumps 1o remain on the protective insulating film 4. When the Ti film 6, which is the underlying metal film, is etched in this state, the Ti film 6
Along with this etching, even the aluminum pad 3 is etched, resulting in electrical defects and lowering the reliability of the semiconductor device.
本発明の目的は、金属パッドの不良をなくし、信頼性の
向上した半導体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device with improved reliability by eliminating defects in metal pads.
１′問題点を解決するための手段〕
本発明の半導体装置の製造方法は、半導体基板上に絶縁
膜を介して第１の金属層を形成したのちパターニングし
第１の金属層からなるパッドを形成する工程と、全面に
保護絶縁膜を形成したのち前記パッド上に選択的に開口
部を形成する工程と、前記開口部を含む全面に第２の金
属層を形成したのちその表面を酸化し絶縁酸化膜を形成
する工程と、前記開口部を含む前記パッド上の前記絶縁
酸化膜を選択的に除去し前記第２の金属層表面を露出さ
せる工程と、無電解めっき法により露出した前記第２の
金属層表面に第３の金属層を形成する工程と、電解めっ
き法により前記第３の金属層上に第４の金属をめっきし
突起型電極を形成する工程と、前記突起型電極とマスク
とし前記絶縁酸化膜及び第２の金属層を除去する工程と
を含んで構成される。1' Means for Solving Problems] The method for manufacturing a semiconductor device of the present invention includes forming a first metal layer on a semiconductor substrate via an insulating film, and then patterning it to form a pad made of the first metal layer. a step of forming a protective insulating film over the entire surface and then selectively forming an opening on the pad; and a step of forming a second metal layer over the entire surface including the opening and then oxidizing the surface. forming an insulating oxide film; selectively removing the insulating oxide film on the pad including the opening to expose the surface of the second metal layer; a step of forming a third metal layer on the surface of the second metal layer; a step of plating a fourth metal on the third metal layer by electrolytic plating to form a protruding electrode; The method includes a step of removing the insulating oxide film and the second metal layer using a mask.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.
まず、第１図（ａ）に示すように、熱酸化等により形成
した酸化シリコン膜等の絶縁膜２を有するシリコン基板
１上に、素子間を接続するアルミニウム配線及びアルミ
ニウムパッド３を形成する。First, as shown in FIG. 1(a), aluminum wiring and aluminum pads 3 for connecting elements are formed on a silicon substrate 1 having an insulating film 2 such as a silicon oxide film formed by thermal oxidation or the like.
続いて全面にＣＶＤ法により酸化シリコン等からなる保
護絶縁膜４を形成したのち、アルミニウムパッド３上の
一部に開口部５を形成する。Subsequently, a protective insulating film 4 made of silicon oxide or the like is formed over the entire surface by CVD, and then an opening 5 is formed in a portion above the aluminum pad 3.
次に第１図（ｂ）に示すように、接着層として厚さ３０
００〜５０００人のＴｉ層６を形成する。Next, as shown in FIG. 1(b), as an adhesive layer, a thickness of 30
00 to 5000 Ti layer 6 is formed.
続いてＴｉ層６の表面を陽極酸化法などを用いて酸化し
厚さ１０００人程度０酸化チタン膜１１を形成する。Subsequently, the surface of the Ti layer 6 is oxidized using an anodic oxidation method or the like to form a zero titanium oxide film 11 having a thickness of approximately 1000 yen.
次に第１図〈Ｃ〉に示すように、ホトレジストを全面に
塗布したのちフォトリソグラフィ技術を用いてアルミニ
ウムパッド３上の一部に開口部５Ｂを形成したマスク８
を形成する。そして、このマスク８を用いて開口部５Ｂ
に露出した酸化チタン膜１１をエツチング除去する。続
いて無電解めっき法を用いてＴｉ層６上にＡｕめっき層
１２を約１μｒｎの厚さに形成する。Next, as shown in FIG. 1 (C), a mask 8 is coated with photoresist and an opening 5B is formed in a part of the aluminum pad 3 using photolithography.
form. Then, using this mask 8, the opening 5B is
The exposed titanium oxide film 11 is removed by etching. Subsequently, an Au plating layer 12 with a thickness of about 1 μrn is formed on the Ti layer 6 using an electroless plating method.
次に第１図（ｄ）に示すように、マスク８を除去したの
ち酸化チタン膜１１をマスクとし、Ｔｉ層６を給電電極
とした電解め°つき法により、Ａ Ｕめっき層１２上に
Ａ ｕを厚さ約２０μｍめっきし、Ａｕバンブ１０を形
成する。続いてＡｕバンブ１０をマスクとして不要の酸
化チタン膜１１及びＴｉ層６をそれぞれエツチング除去
することによりＡ ｕバンプ１０を有する半導体装置が
完成する。Next, as shown in FIG. 1(d), after removing the mask 8, A is deposited on the A U plating layer 12 by electroplating using the titanium oxide film 11 as a mask and the Ti layer 6 as a power supply electrode. Au bumps 10 are formed by plating u to a thickness of about 20 μm. Subsequently, using the Au bumps 10 as a mask, unnecessary titanium oxide film 11 and Ti layer 6 are removed by etching, thereby completing a semiconductor device having Au bumps 10.
このようにして形成されたＡｕバンブ１０は、第１図（
ｄ）に示したように、アルミニウムバッド３上の保護絶
縁膜４上に形成された酸化チタン膜１１表面に隙間なく
形成される。従って、不要の酸化チタン膜１１及びＴｉ
層６をエツチング除去する際に、マスクとしてのＡ １
．１バンブ１０がエツチングされたとしてらその側面の
エツチング量は少なく、そのエツチング液によりアルミ
ニウムパッド３までが工・ソチングされることはない。The Au bump 10 formed in this way is shown in FIG.
As shown in d), the titanium oxide film 11 formed on the protective insulating film 4 on the aluminum pad 3 is formed without any gaps. Therefore, unnecessary titanium oxide film 11 and Ti
A 1 as a mask when etching away layer 6
．． Even if one bump 10 is etched, the amount of etching on its side surface is small, and the etching solution does not etching or sowing up to the aluminum pad 3.
尚、上記実施例においては接着層としてＴｉを用いた場
合について説明したがＣｒであってもよく、又バンブ形
成金属としてＡｕを用いなが、その他Ｃｕやはんだ等を
用いることができる。更に金属パッドとしてアルミニウ
ムを用いたが、アルミニウム合金であってもよい。In the above embodiments, the adhesive layer is made of Ti, but Cr may also be used.Although Au is used as the bump forming metal, other materials such as Cu or solder may also be used. Further, although aluminum is used as the metal pad, an aluminum alloy may be used.
以上説明したように本発明は、金属パッド上のめっき用
給電電極として用いる金属層の表面を酸化して絶縁酸化
膜を形成したのち、選択的に開口部を形成し、この絶縁
酸化膜をマスクとし電解めっき法により開口部の金属層
表面に突起型電極を形成することにより、突起型電極形
成後の不用の金属層及び絶縁酸化膜をエツチングする際
に、金属パッドはエツチングされることはなくなる。従
つて金属パッドの電気的不良がなくなり信頼性向上した
半導体装置の製造方法が得られる。As explained above, the present invention oxidizes the surface of a metal layer used as a power supply electrode for plating on a metal pad to form an insulating oxide film, and then selectively forms openings and masks this insulating oxide film. By forming a protruding electrode on the surface of the metal layer in the opening by electrolytic plating, the metal pad will not be etched when etching the unnecessary metal layer and insulating oxide film after forming the protruding electrode. . Therefore, it is possible to obtain a method of manufacturing a semiconductor device with improved reliability by eliminating electrical defects in metal pads.
第１図（ａ）〜（ｄ）は本発明の一実施例を明するため
の工程＋１＠に示した半導体チップの断固、第２図（ａ
）〜（ｄ）は従来の半導体装置製造方法を説明するため
の工程順に示した半導チップの断面図である。
１・・・シリコン基板、２・・・絶縁膜、３・・・アル
ミラムパッド、４・・・保護絶縁膜、５，５Ａ・・・開
口６・・・Ｔｉ膜、７・・・Ａｕ膜、８・・・マスク、
１０・・・Ｕバンブ、１１・・・酸化チタン膜、１２・
・・Ａｕめき層。FIGS. 1(a) to (d) show the determination of the semiconductor chip shown in step +1@ to clarify one embodiment of the present invention, and FIG. 2(a)
) to (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional semiconductor device manufacturing method. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Insulating film, 3... Aluminum ram pad, 4... Protective insulating film, 5, 5A... Opening 6... Ti film, 7... Au film , 8...mask,
10...U bump, 11...Titanium oxide film, 12.
...Au plating layer.
Claims (1)
たのちパターニングし第１の金属層からなるパッドを形
成する工程と、全面に保護絶縁膜を形成したのち前記パ
ッド上に選択的に開口部を形成する工程と、前記開口部
を含む全面に第２の金属層を形成したのちその表面を酸
化し絶縁酸化膜を形成する工程と、前記開口部を含む前
記パッド上の前記絶縁酸化膜を選択的に除去し前記第２
の金属層表面を露出させる工程と、無電解めっき法によ
り露出した前記第２の金属層表面に第３の金属層を形成
する工程と、電解めっき法により前記第３の金属層上に
第４の金属をめっきし突起型電極を形成する工程と、前
記突起型電極をマスクとし前記絶縁酸化膜及び第２の金
属層を除去する工程とを含むことを特徴とする半導体装
置の製造方法。A step of forming a first metal layer on a semiconductor substrate via an insulating film and then patterning it to form a pad made of the first metal layer, and forming a protective insulating film over the entire surface and then selectively forming a pad on the pad. a step of forming an opening, a step of forming a second metal layer on the entire surface including the opening, and then oxidizing the surface to form an insulating oxide film; and a step of forming an insulating oxide film on the pad including the opening. Selectively removing the film and removing the second
forming a third metal layer on the exposed second metal layer surface by electroless plating; and forming a fourth metal layer on the third metal layer by electrolytic plating. A method for manufacturing a semiconductor device, comprising: plating a metal to form a protruding electrode; and using the protruding electrode as a mask, removing the insulating oxide film and the second metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61185545A JPS6341050A (en) | 1986-08-06 | 1986-08-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61185545A JPS6341050A (en) | 1986-08-06 | 1986-08-06 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6341050A true JPS6341050A (en) | 1988-02-22 |
Family
ID=16172678
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61185545A Pending JPS6341050A (en) | 1986-08-06 | 1986-08-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6341050A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660384A1 (en) * | 1993-12-15 | 1995-06-28 | AT&T Corp. | Method for electrodeposition of solder |
-
1986
- 1986-08-06 JP JP61185545A patent/JPS6341050A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660384A1 (en) * | 1993-12-15 | 1995-06-28 | AT&T Corp. | Method for electrodeposition of solder |
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