JPH02159033A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02159033A
JPH02159033A JP63312801A JP31280188A JPH02159033A JP H02159033 A JPH02159033 A JP H02159033A JP 63312801 A JP63312801 A JP 63312801A JP 31280188 A JP31280188 A JP 31280188A JP H02159033 A JPH02159033 A JP H02159033A
Authority
JP
Japan
Prior art keywords
bump
lead
contact window
pad
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63312801A
Other languages
Japanese (ja)
Inventor
Aiichiro Umezuki
梅月 愛一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63312801A priority Critical patent/JPH02159033A/en
Publication of JPH02159033A publication Critical patent/JPH02159033A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13026Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13027Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being offset with respect to the bonding area, e.g. bond pad

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the strength of close contact between a lead and a bump by causing a contact window to be formed into the shape of a rectangle where its longitudinal side is at a right angle to a lead connecting to a bump electrode and making its location to deflect to the pointed end side of the lead rather than the center position of the bump electrode. CONSTITUTION:An insulating layer 4 is formed on a semiconductor substrate 3 and a metallic wiring layer including a pad 5 is formed on the above layer 4. Then an insulating layer 6 covering the whole body is formed after making up a three-layer structure consisting of PSG, SiN, and polyimide and then a contact window 2 is formed at the pointed end side of the lead 9 rather than the center of the bump and is formed into the shape of a rectangle as well. Subsequently, Ti and Pd are formed extensively as a barriermetal layer 7. A part corresponding to the bump 1 is removed by applying a resist layer 11 on the barrier/metal layer 7. The bump 1 plated with gold is laminated on the barrier/metal layer 7 which is not covered with resist 11 by using the barrier/metal layer 7 as an electrode through electrolytic plating. After removing the resist 11, Ti and Pb of the barrier/metal layer 7 are removed by etching.

Description

【発明の詳細な説明】 〔概 要〕 半導体装置製造でのTAB工程に適した半導体装置、特
に半導体装置のメツキバンプに関し、メツキバンプの大
きさを小さくしてもリード・バンプ問およびバンプ・基
板間の密着性を同時に確保できるようにするメツキバン
プを提供することを目的とし、 半導体基板上のパッドを覆う絶縁層に前記パッドを露出
するコンタクト窓が設けられ、前記パッドには前記コン
タクト窓を介してバンプ電極が設けられてなる半導体装
置において、前記コンタクト窓は、長手方向が前記バン
プ電極に接続されるリードに対して直角の長方形である
こと又は/および前記バンプ電極の中心位置よりも前記
リードの先端側へ偏位してなるように構成する。
[Detailed Description of the Invention] [Summary] With regard to semiconductor devices suitable for the TAB process in semiconductor device manufacturing, especially the plating bumps of semiconductor devices, even if the size of the plating bumps is reduced, the gap between the leads and bumps and between the bumps and the substrate will be reduced. In order to provide a plating bump that can simultaneously ensure adhesion, a contact window is provided in an insulating layer that covers a pad on a semiconductor substrate to expose the pad, and the pad is exposed to the bump through the contact window. In a semiconductor device provided with an electrode, the contact window has a rectangular shape whose longitudinal direction is perpendicular to the lead connected to the bump electrode, and/or the contact window is located closer to the tip of the lead than the center of the bump electrode. It is configured so that it deviates to the side.

〔産業上の利用分野] 本発明は、半導体装置製造でのTAB(tape au
t。
[Industrial Field of Application] The present invention is applicable to TAB (tape au
t.

mated bonding)工程に適した半導体装置
、特に、半導体装置のメツキバンプに関する。
The present invention relates to a semiconductor device suitable for a mated bonding process, and in particular to a plating bump for a semiconductor device.

半導体装での多ピンの接続技術として、TABはワイヤ
ーボンディングが抱える問題を解決できるより好ましい
手段として広く採用されるようになっている。
As a multi-pin connection technology for semiconductor devices, TAB has become widely adopted as a more preferable means for solving the problems faced by wire bonding.

[従来の技術] TAB工程では、リードとバンプとの間の密着性(接続
強度)およびバンプと半導体基板(すなわち、半導体基
板上の配線であるパッド)との密着性を良くすることが
、歩留り向上および信頼性向上のために求められている
[Prior art] In the TAB process, improving the adhesion (connection strength) between the lead and the bump and the adhesion between the bump and the semiconductor substrate (i.e., the pad, which is the wiring on the semiconductor substrate) improves the yield. Required for improvements and improved reliability.

バンプを金(Au)などのメツキで形成する場合には、
第2図および第7B図にも示すように、メツキを被着す
る表面のプロフィルがメツキバンプ表面プロフィルとな
っている。リードとバンプ間の密着性を大きくするには
、これらの接触面積を大きくすればよいが、バンプ全体
のサイズが規定されているので、バンプと基板との接触
面積となる絶縁層に設けたコンタクト窓を小さくするこ
とになる。しかし、コンタクト窓を小さくすると、バン
プと基板間の密着性が小さくなり、バンプの剥れが発生
する恐れがある。そこで、リードとバンプ間の密着性お
よびバンプと基板間の密着性を両方とも確保するように
コンタクト窓を形成する必要がある。
When forming bumps with plating such as gold (Au),
As shown in FIGS. 2 and 7B, the profile of the surface to which plating is applied is a plating bump surface profile. In order to increase the adhesion between the lead and the bump, it is possible to increase the contact area between them, but since the overall size of the bump is regulated, the contact area provided on the insulating layer, which is the contact area between the bump and the substrate, is The window will have to be made smaller. However, if the contact window is made smaller, the adhesion between the bump and the substrate will be reduced, and there is a risk that the bump will peel off. Therefore, it is necessary to form the contact window so as to ensure both the adhesion between the lead and the bump and the adhesion between the bump and the substrate.

従来の半導体装置のメツキバンプ1は、第7A図および
第7B図に示すように、正方形であり、コンタクト窓2
も正方形であってメツキバンプ1の中央に位置している
。この場合に、半導体基板3の表面に絶縁層4があって
、その上にパッド5を含む金属配線が形成され、半導体
基板のバッジュヘーション膜でもある絶縁層6が全体を
覆い、パッド5上にコンタクト窓2が形成されている。
The plating bump 1 of the conventional semiconductor device is square, as shown in FIGS. 7A and 7B, and the contact window 2
It is also square and located at the center of the bump 1. In this case, there is an insulating layer 4 on the surface of the semiconductor substrate 3, on which metal wiring including pads 5 is formed, and an insulating layer 6, which is also a badge film of the semiconductor substrate, covers the whole, and the pads 5 A contact window 2 is formed on top.

通常、パッド5はアルミニウム合金で作られており、電
解メツキ時の電極も兼ねるバリアメタル層7が第1B図
に示すようにコンタクト窓2内でパッド5と接解し絶縁
層6上に形成されている。このバリアメタル層7上にA
uなどのメツキバンプ1が電解メツキ法によって積層さ
れ、その中央部にはコンタクト窓2に対応する凹所8が
生じている。そして、メツキバンプ1に、Au 、錫(
Sn)などのリード9が熱圧着によって領域AおよびB
にて接着されている。
Usually, the pad 5 is made of an aluminum alloy, and a barrier metal layer 7, which also serves as an electrode during electrolytic plating, is bonded to the pad 5 within the contact window 2 and formed on the insulating layer 6, as shown in FIG. 1B. ing. A on this barrier metal layer 7
Plating bumps 1 such as U are laminated by electrolytic plating, and a recess 8 corresponding to the contact window 2 is formed in the center thereof. Then, on the Metsuki bump 1, Au, tin (
Leads 9 such as Sn) are attached to areas A and B by thermocompression bonding.
It is glued at.

〔発明が解決しようとする課題] 半導体装置の多ピン化のために、個々のバンプの大きさ
が小さくされてくると、リード9とバンプ1との接触面
積(領域A、Bの面積)が減少してリードとバンプ間の
密着強度が低下する。この密着強度確保のために、コン
タクト窓2を小さくすると、今度はバンプとパッド間の
密着強度はコンタクト窓面積と比例関係にあるのでこち
らの密着強度は低下することになる。また、パッドのコ
ンタクト抵抗が増加してしまう。したがって、コンタク
ト窓2の大きさを簡単に小さくはできないので、バンプ
サイズが小さくなると、リード・バンプ間およびバンプ
・基板間の密着性の両方を確保するのに問題がある。
[Problems to be Solved by the Invention] As the size of individual bumps becomes smaller due to the increase in the number of pins in semiconductor devices, the contact area between lead 9 and bump 1 (area of regions A and B) increases. As a result, the adhesion strength between the lead and the bump decreases. In order to ensure this adhesion strength, if the contact window 2 is made smaller, the adhesion strength between the bump and the pad is proportional to the area of the contact window, so the adhesion strength here will decrease. Furthermore, the contact resistance of the pad increases. Therefore, since the size of the contact window 2 cannot be easily reduced, if the bump size is reduced, there is a problem in ensuring both the adhesion between the lead and the bump and between the bump and the substrate.

本発明の目的は、メツキバンプの大きさを小さくしても
リード・バンプ間およびバンプ・基板間の密着性を同時
に確保できるようにするメツキバンプを提供することで
ある。
An object of the present invention is to provide a plating bump that can simultaneously ensure adhesion between the lead and the bump and between the bump and the substrate even if the size of the plating bump is reduced.

〔課題を解決するための手段〕[Means to solve the problem]

上述の目的が、半導体基板上のパッドを覆う絶縁+#!
−層に前記パッドを露出するコンタクト窓が設けられ、
前記パッドには前記コンタクト窓を介してバンプ電極が
設けられてなる半導体装置において、前記コンタクト窓
は、長手方向が前記バンプ電極に接続されるリードに対
して直角の長方形であること又は/および前記バンプ電
極の中心位置よりも前記リードの先端側へ偏位してなる
ことを特徴とする半導体装置によって達成される。
The above purpose is insulation covering the pads on the semiconductor substrate!
- a layer is provided with a contact window exposing said pad;
In a semiconductor device in which a bump electrode is provided on the pad through the contact window, the contact window is rectangular with a longitudinal direction perpendicular to the lead connected to the bump electrode; and/or This is achieved by a semiconductor device characterized in that the bump electrode is deviated from the center position toward the tip of the lead.

〔作 用〕[For production]

本発明によれば、コンタクト窓の面早(すなわち、バン
プ・基板間密着力)を変えずに、リードが剥れが先ず発
生するリード・バンプ接触領域(第1A図での領域Aに
相当)の面積を大きくするようにすれば、リード・バン
プ間密着力の確保ができることに基づいている。
According to the present invention, the lead-bump contact area (corresponding to area A in FIG. 1A) where the lead peels first occurs without changing the surface speed of the contact window (that is, the adhesion between the bump and the substrate). This is based on the fact that adhesion between the lead and the bump can be ensured by increasing the area of the bump.

このようにして、第1に、第6図のように、コンタクト
窓の位置を変えずに、コンタクト窓の形状を従来の正方
形からリードに対して垂直方向に長方形にすることによ
ってもリード・バンプ接触領域の面積が増大する。第2
に、第5図のように、コンタクト窓の位置のメツキバン
プ中心からリード先端側へずらせば、リード先端側での
リード・バンプ接触領域の面積が減少し、その分だけ半
導体装置外周側でのリード・バンプ接触領域の面積が増
大する。そして、上述の第1および第2の組合せとして
の第3の場合では、半導体装置外周側でのリード・バン
プ接触領域面積を一段と大きくすることができるので好
ましい。
In this way, first, as shown in FIG. 6, the shape of the contact window can be changed from the conventional square to a rectangle in the direction perpendicular to the lead without changing the position of the contact window, thereby improving the lead bump. The area of the contact area increases. Second
As shown in Fig. 5, if the contact window position is shifted from the center of the plating bump toward the lead tip side, the area of the lead-bump contact area on the lead tip side decreases, and the lead on the outer periphery of the semiconductor device decreases accordingly. - The area of the bump contact area increases. The third case, which is a combination of the first and second combinations described above, is preferable because the area of the lead/bump contact region on the outer peripheral side of the semiconductor device can be further increased.

〔実施例〕〔Example〕

以下、添付図面を参照して本発明をより詳しく説明する
Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

第1図は、本発明に係る半導体装置のバンプおよびリー
ドの部分平面図であり、その断面図が第2図である。本
発明の半導体装置のバンプは従来の半導体装置のバンプ
と類似の構造であり、同じ部分については同一参照番号
で示す。特に、この場合はコンタクト窓2の位置がリー
ド先端側にずれかつコンタクト窓形状が長方形である。
FIG. 1 is a partial plan view of bumps and leads of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view thereof. The bumps of the semiconductor device of the present invention have a similar structure to the bumps of conventional semiconductor devices, and the same parts are designated by the same reference numerals. In particular, in this case, the position of the contact window 2 is shifted toward the lead tip side, and the contact window shape is rectangular.

半導体装置のメツキバンプlは、例えば、次のようにし
て作られる。
The plating bump l of the semiconductor device is made, for example, as follows.

まず、第3図に示すように、通常の工程にしたがって、
シリコンなどの半導体基板3上に絶縁層4を形成し、そ
の上にパッド5を含む金属配線(Af−Si合金で厚さ
1.OI!m)を形成する。次に全体を被覆する絶縁層
6をPSG(1,On厚さ)1.5iN(0,3趨厚さ
)およびポリイミド(2,0趨厚さ)の三層構造で形成
する。
First, as shown in Figure 3, according to the normal process,
An insulating layer 4 is formed on a semiconductor substrate 3 made of silicon or the like, and a metal wiring (Af-Si alloy with a thickness of 1.OI!m) including a pad 5 is formed thereon. Next, an insulating layer 6 covering the entire structure is formed with a three-layer structure of PSG (1, On thickness), 1.5 iN (0.3 inch thickness), and polyimide (2.0 inch thickness).

第4図に示すように、通常のリングラフィ法によって絶
縁層6にコンタクト窓2を形成する。このコンタクト窓
2の位置および形状を第1図に示すように従来の第7A
図と比べてメツキバンプ1との関係でバンプ中心よりも
図面で左側へ(リード先端側へ)かつ長方形にする。な
お、コンタクト窓2の面積は従来の場合と同じとして、
バンプ・基板間密着強度は同じに維持される。次に、バ
リア・メタル層7としてT i (500nm厚さ)お
よびPd(300na+厚さ)をスパッタリング法によ
ってコンタクト窓2内でバッド5と接触する部分を含め
全面に形成する。バリア・メタル層7上にレジスト層(
厚さ;304)11を塗布し、バンプ1に相当する部分
を露光・現像によって除去する。そしてて、バリア・メ
タル層7を電極として電解メツキによってレジスト11
にカバーされていないバリア・メタル層7上に金メツキ
バンプ1(厚さ:25IIIl)を積層する。このメツ
キバンプ1の位置および形状は従来(第7A図、第7B
図)と同じにし、メツキバンプ1の上面に生じる凹所8
の位置、形状がコンタクト窓2に応じて変化しているわ
けである。
As shown in FIG. 4, a contact window 2 is formed in the insulating layer 6 by a normal phosphorography method. The position and shape of this contact window 2 are as shown in FIG.
Compared to the diagram, in relation to the mating bump 1, the bump center is moved to the left in the diagram (toward the lead tip side) and rectangular. Assuming that the area of the contact window 2 is the same as in the conventional case,
The adhesion strength between the bump and the substrate is maintained the same. Next, Ti (500 nm thick) and Pd (300 na+thick) are formed as a barrier metal layer 7 over the entire surface of the contact window 2 including the portion that contacts the pad 5 by sputtering. A resist layer (
A thickness of 304) 11 is applied, and the portion corresponding to bump 1 is removed by exposure and development. Then, the resist 11 is electrolytically plated using the barrier metal layer 7 as an electrode.
A gold plating bump 1 (thickness: 25III) is laminated on the barrier metal layer 7 which is not covered. The position and shape of this bump 1 are conventional (Fig. 7A, 7B).
The recess 8 created on the top surface of the bump bump 1 is the same as in the figure).
The position and shape of the contact window 2 change depending on the contact window 2.

レジスト11を除去してから、メツキバンプlをマスク
としてバリア・メタル層7のTiおよびpbを過酸化水
素アンモニアと王水でエツチング除去する。そして、チ
ップ処理を行った後に、インナーリードボンディング(
ILB)工程でり−ド9を熱圧着(400〜500°C
にて数秒)する(第1図および第2図)。
After removing the resist 11, using the plating bump 1 as a mask, Ti and PB of the barrier metal layer 7 are removed by etching with hydrogen peroxide ammonia and aqua regia. After chip processing, inner lead bonding (
ILB) process, heat compression bonding (400-500°C)
(for several seconds) (Figures 1 and 2).

このようにしてリード9を取付けたメツキバンプ1にお
いては、その接触領域alおよびblの合計面積が従来
(第7A図)の接触領域AおよびBの合計面積よりも大
きく、しかも剥離が発生しだすことになる接触領域al
の面積は従来の接触領域Aよりも大きい。したがって、
本発明の場合にはリード・バンプの間密着強度は従来よ
りも大きい。
In the mated bump 1 with the leads 9 attached in this way, the total area of the contact areas al and bl is larger than the total area of the conventional contact areas A and B (FIG. 7A), and furthermore, peeling begins to occur. The contact area al
The area of the contact area A is larger than that of the conventional contact area A. therefore,
In the case of the present invention, the adhesion strength between the lead and the bump is greater than that of the prior art.

本発明の別の実施態様例の半導体バンプを第5図に示す
。この場合には、従来(第7A図)と同じ形状の正方形
コンタクト窓2であるが、その位置をバンプ中心よりも
リード先端側へずらしである。したがって、リード9と
上述のようにして形成したメツキバンプlとの接触領域
a2およびb2の合計面積は従来(第7A図)の場合と
同じであるが、接触領域b2は位置ずれした分だけ従来
よりも小さくなり、その分接触領域a2は従来の接触領
域Aよりも大きい。ゆえに、この場合もリード・バンプ
間密着強度は従来よりも大きい。
A semiconductor bump according to another embodiment of the present invention is shown in FIG. In this case, the square contact window 2 has the same shape as the conventional one (FIG. 7A), but its position is shifted toward the lead tip side from the center of the bump. Therefore, the total area of the contact areas a2 and b2 between the lead 9 and the plating bump l formed as described above is the same as in the conventional case (FIG. 7A), but the contact area b2 is larger than the conventional one by the amount of positional shift. The contact area a2 is also smaller than the conventional contact area A. Therefore, in this case as well, the adhesion strength between the lead and the bump is greater than in the conventional case.

さらに、本発明のその他の実施態様例の半導体バンプを
第6図に示す。この場合には、従来(第7A図)とは形
状が異なるコンタクト窓2としており、その形状はリー
ドに対して垂直方向に長平方向のある長方形としである
。この場合でも、コンタクト窓2の面積は従来と同じに
してあり、細長くなっただけリード・バンプ接触領域a
3およびb3の合計面積は従来よりも大きくなっており
、接触領域a3についても接触領域Aよりも大きい。
Further, a semiconductor bump according to another embodiment of the present invention is shown in FIG. In this case, the contact window 2 has a different shape from the conventional one (FIG. 7A), and its shape is a rectangle with an elongated direction perpendicular to the leads. Even in this case, the area of the contact window 2 is the same as before, and the lead/bump contact area a is elongated.
The total area of 3 and b3 is larger than the conventional one, and the contact area a3 is also larger than the contact area A.

したがって、リード・バンプ間密着強度は従来よりも大
きい。
Therefore, the adhesion strength between the leads and bumps is greater than that of the prior art.

[発明の効果] 以上説明したように、本発明によれば、半導体メツキバ
ンプの基板とのコンタクト窓の位置および形状を従来と
変えることによって、バンプ・基板間の接触(着)面積
をそのまま維持して(一定にして)、リード・パン1間
(特に、半導体装置の外周側の剥れの発生しやすいリー
ド・バンプ間)接触面積を増大させることができる。そ
の結果として、リード・パン1聞書着強度を向上させる
ことができて、歩留りおよび信頌性を向上させ、今後の
メンキバンプ微細化において本発明を応用して微細化が
図れる。
[Effects of the Invention] As explained above, according to the present invention, the contact area between the bump and the substrate can be maintained as is by changing the position and shape of the contact window between the semiconductor plating bump and the substrate from the conventional one. (at a constant value), it is possible to increase the contact area between the lead pan 1 (particularly between the lead and bumps where peeling tends to occur on the outer peripheral side of the semiconductor device). As a result, the adhesion strength of the lead pan can be improved, yield and reliability can be improved, and the present invention can be applied to miniaturization of Menki bumps in the future.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明に係る半導体メツキバンプおよび接着
したリードの部分平面図であり、第2図は、第1図に対
応した部分断面図であり、第3図および第4図は、本発
明に係る半導体メツキバンプ(第1図および第2図)を
製作する中間工程での部分断面図であり、 第5図および第6図は、本発明の別の実施態様例の半導
体メツキバンプおよびリードの概略平面図であり、 第7A図は、従来の半導体装置のメツキバンプおよびリ
ードの部分平面図であり、 第7B図は、第7A図に対応した部分断面図である。 l・・・メツキバンプ、   2・・・コンタクト窓、
5・・・パッド、      6・・・絶縁層、9・・
・リード。 本発明の半導体装置バンプの平面図 第1図 第1図の新面図 第20 第 図 ニー 図 第 図 其6図
FIG. 1 is a partial plan view of a semiconductor plating bump and bonded leads according to the present invention, FIG. 2 is a partial cross-sectional view corresponding to FIG. 1, and FIGS. FIGS. 5 and 6 are partial cross-sectional views at an intermediate step in manufacturing the semiconductor plating bump (FIGS. 1 and 2) according to the present invention; FIGS. 5 and 6 are schematic diagrams of the semiconductor plating bump and leads of another embodiment of the present invention 7A is a partial plan view of a plating bump and lead of a conventional semiconductor device; FIG. 7B is a partial sectional view corresponding to FIG. 7A; FIG. l...Metsuki bump, 2...contact window,
5... Pad, 6... Insulating layer, 9...
・Lead. Plan view of the semiconductor device bump of the present invention FIG. 1 New view of FIG. 1 FIG. 20 FIG. knee diagram FIG. 6

Claims (1)

【特許請求の範囲】 1、半導体基板上のパッドを覆う絶縁層に前記パッドを
露出するコンタクト窓が設けられ、前記パッドには前記
コンタクト窓を介してバンプ電極が設けられてなる半導
体装置において、 前記コンタクト窓は、長手方向が前記バンプ電極に接続
されるリードに対して直角の長方形であることを特徴と
する半導体装置。 2、半導体基板上のパッドを覆う絶縁層に前記パッドを
露出するコンタクト窓が設けられ、前記パッドには前記
コンタクト窓を介してバンプ電極が設けられてなる半導
体装置において、 前記コンタクト窓は、前記バンプ電極の中心位置よりも
、前記バンプ電極に接続されるリードの先端側へ偏位し
てなることを特徴とする半導体装置。 3、半導体基板上のパッドを覆う絶縁層に前記パッドを
露出するコンタクト窓が設けられ、前記パッドには前記
コンタクト窓を介してバンプ電極が設けられてなる半導
体装置において、 前記コンタクト窓は、長手方向が前記バンプ電極に接続
されるリードに対して直角の長方形であると共に、前記
バンプ電極の中心位置よりも前記リードの先端側へ偏位
してなることを特徴とする半導体装置。
[Claims] 1. A semiconductor device in which an insulating layer covering a pad on a semiconductor substrate is provided with a contact window that exposes the pad, and a bump electrode is provided on the pad through the contact window, A semiconductor device, wherein the contact window has a rectangular shape whose longitudinal direction is perpendicular to a lead connected to the bump electrode. 2. A semiconductor device in which an insulating layer covering a pad on a semiconductor substrate is provided with a contact window that exposes the pad, and a bump electrode is provided on the pad via the contact window, wherein the contact window is A semiconductor device characterized in that the bump electrode is deviated from the center position toward the tip of a lead connected to the bump electrode. 3. In a semiconductor device in which a contact window exposing the pad is provided in an insulating layer covering a pad on a semiconductor substrate, and a bump electrode is provided to the pad via the contact window, the contact window has a longitudinal direction. A semiconductor device characterized in that the semiconductor device has a rectangular shape whose direction is perpendicular to a lead connected to the bump electrode, and the semiconductor device is deviated from the center position of the bump electrode toward the tip of the lead.
JP63312801A 1988-12-13 1988-12-13 Semiconductor device Pending JPH02159033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63312801A JPH02159033A (en) 1988-12-13 1988-12-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63312801A JPH02159033A (en) 1988-12-13 1988-12-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02159033A true JPH02159033A (en) 1990-06-19

Family

ID=18033570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63312801A Pending JPH02159033A (en) 1988-12-13 1988-12-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02159033A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5773888A (en) * 1994-11-12 1998-06-30 Kabushiki Kaisha Toshiba Semiconductor device having a bump electrode connected to an inner lead
US6710384B2 (en) * 1999-06-03 2004-03-23 Oki Electric Industry Co., Ltd. Semiconductor memory device
JP2012174847A (en) * 2011-02-21 2012-09-10 Murata Mfg Co Ltd Electronic component and module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5773888A (en) * 1994-11-12 1998-06-30 Kabushiki Kaisha Toshiba Semiconductor device having a bump electrode connected to an inner lead
US6710384B2 (en) * 1999-06-03 2004-03-23 Oki Electric Industry Co., Ltd. Semiconductor memory device
JP2012174847A (en) * 2011-02-21 2012-09-10 Murata Mfg Co Ltd Electronic component and module

Similar Documents

Publication Publication Date Title
US7056818B2 (en) Semiconductor device with under bump metallurgy and method for fabricating the same
JP5113346B2 (en) Electronic device substrate and manufacturing method thereof, and electronic device and manufacturing method thereof
JP2792532B2 (en) Semiconductor device manufacturing method and semiconductor wafer
USRE46466E1 (en) Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
US6656772B2 (en) Method for bonding inner leads to bond pads without bumps and structures formed
JP3217624B2 (en) Semiconductor device
JP7051508B2 (en) Semiconductor devices and methods for manufacturing semiconductor devices
JPH1012769A (en) Semiconductor device and its manufacture
JP2000299337A (en) Semiconductor device and manufacture thereof
JPH0432541B2 (en)
US7202421B2 (en) Electronic elements, method for manufacturing electronic elements, circuit substrates, method for manufacturing circuit substrates, electronic devices and method for manufacturing electronic devices
JP2009044077A (en) Semiconductor device, and manufacturing method of semiconductor device
JPH02159033A (en) Semiconductor device
JP2003243455A (en) Tape, method of manufacturing the same, semiconductor device, method of manufacturing the same
JP3323091B2 (en) Semiconductor integrated circuit device and method of manufacturing the same
JPH11186309A (en) Semiconductor device and manufacture of the semiconductor device
JP3019556B2 (en) Lead frame manufacturing method and semiconductor device manufacturing method
JPH02220440A (en) Manufacture of semiconductor device
JPH01187949A (en) Manufacture of semiconductor device
KR100237619B1 (en) Tape automatic bonding method and its structure
JPH0719797B2 (en) Semiconductor device mounting tool
JP3316532B2 (en) Semiconductor device and manufacturing method thereof
KR100325459B1 (en) Chip size package manufacturing method
JPH0878419A (en) Manufacture of bump and semiconductor device using the same
JP2001237261A (en) Semiconductor, device and method for manufacturing the same