JP2009044077A - Semiconductor device, and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has a bump electrode whose surface is flat, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device includes a semiconductor chip 11 where an electrode pad 13 is formed on the surface, an upper wiring layer 17 which is arranged on the electrode pad 13, with the upper surface facing the semiconductor chip 11, being flat, a passivation film 15 which is flush with the upper surface of the upper wiring layer 17 to contact the side surface of the upper wiring layer 17, for covering the surface of the semiconductor chip 11, a bump base material metal 21 which is arranged on the upper wiring layer 17 and the passivation film 15 around the upper wiring layer 17, being connected to the upper wiring layer 17, and a gold bump 25 having a specified film thickness which is arranged on the bump base material metal 21, being flat, to share the side surface. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a bump electrode and a method for manufacturing the semiconductor device.

  A semiconductor chip for an LCD driver used in a liquid crystal display (LCD) is required to cope with downsizing and / or high definition. TCP (Tape Carrier Package) etc. are adopted as the LCD driver package. In COF (Chip on Film) etc., bump electrodes formed on the LCD driver semiconductor chip are formed by inner lead and ILB (Inner Lead Bonding) method etc. Often connected. COF is known as being suitable for fine pitching because it can be reduced in size and thickness.

  A manufacturing method is disclosed in which the dimensional accuracy of a bump electrode is increased by using a silanol compound instead of a resist used in the prior art in order to cope with a fine pitch of a bump electrode of a semiconductor chip (for example, Patent Documents). 1).

In this disclosed manufacturing method, it is considered possible to increase the dimensional accuracy of the bump electrode. For example, a gold bump is an electrode pad on the top of the chip, a passivation film on the chip, and a step of the passivation film. Reflecting the stepped shape of the UBM (Under Bump Metal) film disposed on the substrate, the surface shape is high at the peripheral portion and low at the central portion. For example, when the surface irregularities are connected to the inner lead, the central portion of the gold bump cannot sufficiently contact the inner lead, resulting in a connection failure. When a load is applied in order to bring the central portion of the gold bump into sufficient contact with the lead, more collapse occurs, causing a problem of contact with the adjacent gold bump.
Japanese Patent Laying-Open No. 2005-322735 (page 4, FIG. 2)

  The present invention provides a semiconductor device having a bump electrode with a flat surface and a method for manufacturing the semiconductor device.

  A semiconductor device according to an aspect of the present invention includes a semiconductor chip having an electrode pad formed on a surface thereof, an upper wiring layer disposed on the electrode pad and having a flat upper surface facing the semiconductor chip, and the upper wiring An insulating film that is flush with an upper surface of the layer, is in contact with a side surface of the upper wiring layer, and covers the surface of the semiconductor chip; and is disposed on the insulating film around the upper wiring layer and the upper wiring layer. A metal film connected to the upper wiring layer; and a metal bump having a predetermined film thickness disposed on the metal film forming a plane, sharing the side surface with the metal film. To do.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which an electrode pad is formed on a surface in a chip formation effective region of a semiconductor substrate that can be arranged without chipping a semiconductor chip, and an opening is formed on the electrode pad. Forming a film, and depositing a conductive film on the electrode pad and the insulating film, and forming an upper wiring layer flattened so that an upper surface of the conductive film is flush with an upper surface of the insulating film A step of depositing a metal film on the insulating film and the upper wiring layer, and a first metal bump on the upper wiring layer via the metal film in the chip formation effective region. And simultaneously forming a second metal bump on the metal film in a region adjacent to the chip formation effective region of the semiconductor substrate and measuring a hardness of the second metal bump. To have And butterflies.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of a semiconductor device which has a bump electrode with a flat surface, and a semiconductor device can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals.

  A semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1A and 1B are diagrams schematically illustrating a configuration of a semiconductor device, in which FIG. 1A is a cross-sectional view and FIG. 1B is a plan view. FIG. 2 is a cross-sectional view schematically showing a method for manufacturing a semiconductor device in the order of steps. FIG. 3 is a cross-sectional view schematically showing the semiconductor device manufacturing method following FIG. 2 in the order of steps. 4A and 4B are diagrams schematically showing a configuration in which a semiconductor device is connected to an inner lead. FIG. 4A is a cross-sectional view, and FIG. 4B is a plan view.

  As shown in FIG. 1, a semiconductor device 1 includes a semiconductor chip 11 having an electrode pad 13 formed on the surface thereof, and an upper portion disposed on the electrode pad 13 and having an upper surface that faces the semiconductor chip 11 being substantially flat. A passivation film 15 that is substantially flush with the upper surface of the wiring layer 17 and is in contact with the side surface of the upper wiring layer 17 and covers the surface of the semiconductor chip 11, the upper wiring layer 17, and the upper wiring layer A bump base metal (UBM) 21 which is a metal film connected to the upper wiring layer 17 and a bump base metal 21 having a flat surface is disposed on the passivation film 15 around the base plate 17. And a gold bump 25 which is a metal bump having a substantially constant film thickness. Note that, in the vertical line standing on the surface of the semiconductor chip 11, the semiconductor chip side is the bottom or bottom, and the gold bump 25 side is the top.

  The cross-sectional view shown in FIG. 1A is a cross-sectional view along the line AA shown in FIG. When projected onto the surface of the semiconductor chip 11, that is, as shown in the plan view of FIG. 1B, the planar size of the gold bump 25 is larger than the planar size of the upper wiring layer 17, and the electrode pad 13. It is smaller than the planar size.

  Next, a method for manufacturing the semiconductor device 1 will be described. Here, the material of each component will be described. As shown in FIG. 2A, the semiconductor chip 11 is not shown in the figure, but, for example, a semiconductor element or the like is formed on the surface of a semiconductor substrate made of silicon, and an interlayer insulating film and A wiring layer is formed, and electrode pads 13 are formed on the wiring layer made of Al or Al alloy at the top. The semiconductor chip 11 has a passivation film 15 formed by laminating a silicon oxide film and a silicon nitride film on the surface, and an opening 14 for connecting the electrode pad 13 to the gold bump 25 is formed inside the upper surface of the electrode pad 13. It is formed by a photolithography method. In addition, the electrode pad 13 may be Cu, Cu alloy, or the like, and the passivation film 15 may be a silicon oxide film, a silicon nitride film, or an organic insulating film such as polyimide resin. is there.

  As shown in FIG. 2B, a material similar to the electrode pad 13, for example, a layer to be the upper wiring layer 17 made of an Al alloy is deposited on the surface of the semiconductor chip 11 by a sputtering method. The film thickness is made thicker than the step of the opening 14.

  As shown in FIG. 2C, the upper surface of the upper wiring layer 17 filling the opening 14 and the upper surface of the passivation film 15 are substantially flush with each other by CMP (Chemical Mechanical Polishing). Process. That is, the upper wiring layer 17 is left only in the opening 14 around the opening 14 and the opening 14. The region that is substantially coplanar is a region that includes a region where a gold bump 25 described later is disposed. If the upper surface of the passivation film 15 can be polished until the upper surface of the upper wiring layer 17 is processed to be flat, the film thickness when the upper wiring layer 17 is deposited is not necessarily thicker than the step of the opening 14. May be.

  As shown in FIG. 2D, a bump base metal 21 composed of two layers of Ti and Pd, which are refractory metals, is deposited on the entire upper surfaces of the passivation film 15 and the upper wiring layer 17 by, for example, a sputtering method. . The bump base metal 21 is used for applying a predetermined potential in the electrolytic plating method, and is a barrier metal. In addition, a two-layer structure of TiW and Au can be used. At least the upper surface of the bump base metal 21 in the region where the gold bump 25 is disposed is flat.

  As shown in FIG. 3A, a resist 23 is applied to the upper surface of the bump base metal 21, and an opening 22 of the resist 23 reaching the bump base metal 21 is formed in a region where the gold bump 25 is formed by photolithography. Form. The bump base metal 21 on the bottom surface of the opening 22 is substantially flat. The step of the opening 22, that is, the upper surface of the resist 23 around the opening 22 is formed to be higher than the upper surface of a gold bump 25 described later.

  As shown in FIG. 3B, the inside of the opening 22 where the bump base metal 21 is exposed at the bottom is made of gold by an electrolytic (electric) plating method using an electrolyte containing gold ions or gold complex ions as a plating solution. A deposited layer, that is, a gold bump 25 is formed. The thickness of the gold bump 25, that is, the height from the bump base metal 21 is substantially constant, and does not exceed the thickness of the resist 23.

  As shown in FIG. 1A, the resist 23 is removed with, for example, an alkaline stripping solution, and then, with the gold bumps 25 as a mask, the Pd and Ti of the bump base metal 21 are, for example, aqua regia and fluorine. The semiconductor device 1 in which the gold bumps 25 each having the same side surface as the side surface of the bump base metal 21 is formed on the bump base metal 21 by etching with an acid is completed. The Pd etching solution may be iodine-based or cyan-based, and Ti etching can be performed using an ammonium fluoride-based solution or dry etching. In addition, when the Pd is etched, the gold bumps 25 are also etched. However, the desired gold bumps 25 can be obtained by forming extra portions in advance for the etching.

  The height (film thickness) of the gold bumps 25 is about 15 μm, the width shown in the left-right direction in FIG. 1 is about 18 μm, and the pitch (not shown) between the gold bumps 25 is about 25 μm. The side surface of the electrode pad 13 is about 2 to 3 μm outside from the projected position of the side surface of the gold bump 25. The side surface of the upper wiring layer 17 is about 3 to 5 μm inside from the projection position of the side surface of the gold bump 25. These dimensions can be changed as appropriate according to the purpose.

  As described above, the semiconductor device 1 is disposed on the semiconductor chip 11 having the electrode pad 13 formed on the surface thereof and the electrode pad 13, and the upper wiring layer 17 whose upper surface facing the semiconductor chip 11 is substantially planar. The passivation film 15 that is substantially flush with the upper surface of the upper wiring layer 17, is in contact with the side surface of the upper wiring layer 17 and covers the surface of the semiconductor chip 11, and the passivation around the upper wiring layer 17 and the upper wiring layer 17. The bump base metal 21 disposed on the film 15 and connected to the upper wiring layer 17 and the bump base metal 21 having a flat surface and the gold bump 25 having a substantially constant film thickness are disposed on the side surface. It has.

  That is, in the semiconductor device 1, since the surface formed by the upper wiring layer 17 and the passivation film 15 is flat, the bump base metal 21 is flat, and since the bump base metal 21 is flat, the bottom surface of the gold bump 25 is flat and the gold film thickness is almost equal. Since it is constant, the exposed surface, that is, the upper surface of the gold bump 25 becomes flat.

  Next, a form in which the semiconductor device 1 is mounted on a package will be described. 4 (a) and 4 (b) correspond to FIGS. 1 (a) and 1 (b), respectively, and the cross-sectional view shown in FIG. 4 (a) is BB shown in FIG. 4 (b). It is sectional drawing along a line. As shown in FIG. 4, the gold bumps 25 of the semiconductor device 1 and the inner leads 31 formed on the COF tape (not shown) are connected on a one-to-one basis. The width of the inner lead 31 shown in the left-right direction in FIG. 4B is formed smaller than the width of the gold bump 25, and the length of the inner lead 31 shown in the vertical direction in FIG. It is arranged beyond.

  For example, the inner lead 31 is made of Cu or a Cu alloy, and the surface thereof is plated with Sn. Although illustration is omitted, by using an inner lead bonder or the like, the gold bump 25 and the inner lead 31 are pressed, and at the same time, the temperature of the contact portion is raised to a temperature at which an Au—Sn eutectic is formed. A eutectic 32 is formed between 25 and the inner lead 31. The gold bump 25 and the inner lead 31 are electrically and mechanically connected by this eutectic 32.

  As described above, the upper surface of the gold bump 25 is flattened. Therefore, the gold bump 25 and the inner lead 31 can be brought into contact with each other by pressing with a relatively weak force. That is, it is possible to make contact with a smaller force compared to the contact between the gold bumps having irregularities on the surface and the inner leads.

  As a result, it is possible to suppress the deformation of the gold bump 25 caused by pressing. In addition, the planar size of the gold bump 25 is smaller than the planar size of the electrode pad 13, and the passivation film 15, the upper wiring layer 17, the electrode pad 13, etc. are caused by the stress generated by the pressing. Can be prevented from being destroyed. Moreover, since it does not press with a strong force, the residual stress when it returns to room temperature is comparatively small.

  Therefore, in the semiconductor device 1, the connection failure between the gold bump 25 and the inner lead 31 is suppressed, and the reliability is improved. In addition, since the deformation of the gold bump 25 in the width direction can be reduced in the semiconductor device 1, the risk of contact with the adjacent gold bump is suppressed, a fine pitch is possible, and miniaturization and high definition are achieved. It becomes possible to respond.

  Conventionally, a technique for reducing the unevenness of the surface of the gold bump, that is, the opening 14 of this embodiment is a set of openings having a small diameter opened in the passivation film, so that the bump base metal on the opening 14 is a small opening. A technique is known in which a concave portion on the surface of a gold bump is made small by forming a gold bump thereon and further forming a gold bump thereon. However, although this conventional technique enables electrical connection due to a collection of small openings, the contact area between the bump base metal and the electrode pad is reduced, and so-called bump peeling is likely to occur.

  Compared to this, the semiconductor device 1 forms a large opening 14, and the upper wiring layer 17 and the bump base metal 21 are contacted and connected in an area equivalent to the large opening 14. 17 and the bump base metal 21 are more strongly connected. As a result, bump peeling is suppressed. The electrode pad 13 and the upper wiring layer 17 are formed of the same material, and the mechanical connection strength is higher than the connection strength between the upper wiring layer 17 and the bump base metal 21.

  Further, the technique of the above-described embodiment can be applied to a gold bump for hardness measurement for monitoring the hardness of the gold bump 25 of the semiconductor device 1. The gold bumps 25 are formed by an electrolytic plating method, but the hardness may change depending on plating conditions and the like. In order to monitor this hardness, the semiconductor device 1 is used for purposes other than electrical and mechanical connection. In many cases, gold bumps for hardness measurement are formed.

  The gold bumps for measuring the hardness are arranged, for example, on the periphery of the semiconductor chip 11 so as not to prevent the connection between the gold bumps 25 and the inner leads 31. According to the inventor's experiment, the gold bump for measuring the Vickers hardness can be stably and accurately measured when it is formed in a square or rectangle having a side of 70 μm or more. That is, the gold bump for hardness measurement has the same shape as the gold bump 25 shown in FIG. 1, has the same height, and has a large planar spread. The upper surface of the gold bump for hardness measurement is flat because it is formed on the base layer having the same layer structure as the base layer of the gold bump 25. In addition, the gold bump for hardness measurement can be similarly formed in the process of forming the gold bump 25.

  As a result, the gold bump for hardness measurement to which the technique of this embodiment is applied can leave the indentation (indentation for measurement) formed by the Vickers hardness measuring device clearly on the flat upper surface, and the diagonal line of the indentation Can be read more accurately, and the Vickers hardness can be obtained more accurately. In the semiconductor device 1, the hardness of the gold bump 25 is suitable for bump connection.

  Further, in the case where the gold bumps for hardness measurement having a large area hinder the miniaturization of the semiconductor device 1, the gold bumps for hardness measurement are arranged outside the semiconductor device 1, that is, the semiconductor device 1 (semiconductor chip 11) is arranged. It can be arranged on the outer periphery of a semiconductor substrate (wafer shape). For example, the outer peripheral portion of the semiconductor substrate does not have an area sufficient for arranging the rectangular semiconductor chip 11, but has a region where the gold bump for hardness measurement can be arranged. Gold bumps can be formed. Here, the region of the semiconductor substrate that can be arranged without chipping the semiconductor chip is referred to as a chip formation effective region. The gold bumps for hardness measurement are arranged in an area adjacent to the chip formation effective area.

  For example, in the step of forming the gold bump 25, the step of forming the gold bump for hardness measurement can proceed in the same manner up to the bump base metal 21 (see FIG. 2D). Then, in the step of forming the opening 22 for the gold bump shown in FIG. 3A and thereafter, patterning is performed with another mask only in the region where the gold bump for hardness measurement is arranged, Simultaneously, electrolytic plating can be performed to form gold bumps for hardness measurement.

  As a result, for example, as shown in FIG. 5, the semiconductor substrate 41 located on the outer periphery of the semiconductor chip 11, the lower wiring layer 43 similar to the electrode pad 13 disposed on the semiconductor substrate 41, the semiconductor substrate A passivation film 15 covering the surface of 41 and the lower wiring layer 43, and a bump base metal 51 similar to the bump base metal 21 disposed on the passivation film 15 are laminated, and a gold bump 55 for hardness measurement is a bump A hardness measuring gold bump 55 similar to the gold bump 25 is disposed on the base metal 51. The surface of the hardness measuring gold bump 55 is flat because the underlying layers are flat. 1 is different from the base structure of the gold bump 25 of the semiconductor device 1 shown in FIG. 1 in that the upper wiring layer 17 is not provided. Since the hardness measurement gold bump 55 is not for connection, it is not always necessary to have the upper wiring layer 17.

  The hardness measurement gold bump 55 is measured more accurately in the Vickers hardness similarly to the hardness measurement gold bump disposed in the semiconductor device 1 described above, and the semiconductor device 1 has the hardness of the gold bump 25. It is suitable for bump connection. Although a process for forming the hardness measurement gold bump 55 is added to the semiconductor substrate 41 on the outer peripheral portion outside the semiconductor device 1, it is not necessary to arrange a hardness measurement gold bump having a relatively large area. The chip size of the semiconductor device 1 can be reduced.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  For example, in the above embodiment, the gold bump and the inner lead are connected by forming an Au—Sn eutectic, but the gold bump and the mounting tape or the mounting substrate side electrode corresponding to the inner lead are different. It is possible to connect via conductive particles of an isotropic conductive resin. Since the surface of the gold bump is flat, the contact resistance can be further lowered and stabilized.

  Moreover, although the gold bump and the inner lead are connected by forming an Au—Sn eutectic in the above embodiment, the metal bump is not only Au but also Cu, Ag, alloys of these metals, etc. In addition, a method of connecting by thermocompression bonding, ultrasonic thermocompression bonding, or the like, or a method of connecting metal bumps by Cu or Cu alloy or the like using solder or the like is possible.

1A and 1B are diagrams schematically illustrating a configuration of a semiconductor device according to an embodiment of the present invention, in which FIG. 1A is a cross-sectional view, and FIG. Sectional drawing which shows typically the manufacturing method of the semiconductor device which concerns on the Example of this invention in order of a process. Sectional drawing which shows typically the manufacturing method following FIG. 2 of the semiconductor device which concerns on the Example of this invention in process order. 4A and 4B are views schematically showing a configuration in which a semiconductor device according to an embodiment of the present invention is connected to an inner lead, in which FIG. 4A is a cross-sectional view and FIG. 4B is a plan view. Sectional drawing which shows typically the structure of the gold bump part which concerns on the modification of the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Semiconductor chip 13 Electrode pad 14, 22 Opening 15 Passivation film 17 Upper wiring layer 21, 51 Bump base metal 23 Resist 25 Gold bump 31 Inner lead 32 Eutectic 41 Semiconductor substrate 43 Lower wiring layer 55 Hardness measurement gold bump

Claims (5)

A semiconductor chip with electrode pads formed on the surface;
An upper wiring layer disposed on the electrode pad and having a flat upper surface facing the semiconductor chip;
An insulating film that is flush with the upper surface of the upper wiring layer, is in contact with the side surface of the upper wiring layer, and covers the surface of the semiconductor chip;
A metal film disposed on the insulating film around the upper wiring layer and the upper wiring layer and connected to the upper wiring layer;
On the metal film forming a plane, the metal film and the side surface are arranged in common, a metal bump having a predetermined film thickness,
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the electrode pad is made of aluminum or an aluminum alloy.   3. The semiconductor device according to claim 1, wherein the metal film is a single layer including a refractory metal or a plurality of layers including a layer including a refractory metal.   4. The semiconductor device according to claim 1, wherein the metal bump is larger than the upper wiring layer and smaller than the electrode pad. 5. Forming an electrode pad on a surface in a chip formation effective region of a semiconductor substrate that can be arranged without chipping the semiconductor chip, and forming an insulating film having an opening on the electrode pad;
Depositing a conductive film on the electrode pad and the insulating film, and forming an upper wiring layer flattened so that an upper surface of the conductive film is flush with an upper surface of the insulating film;
Depositing a metal film on the insulating film and the upper wiring layer;
A first metal bump is formed on the upper wiring layer through the metal film in the chip formation effective region, and at the same time, on the metal film in a region adjacent to the chip formation effective region of the semiconductor substrate. Forming a second metal bump on
Measuring the hardness of the second metal bump;
A method for manufacturing a semiconductor device, comprising:

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