JP4726221B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique for forming a via hole from a back surface of a semiconductor substrate to expose a pad electrode formed on the semiconductor substrate.

  In recent years, CSP (Chip Size Package) has attracted attention as a three-dimensional mounting technique and a new packaging technique. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip.

  Conventionally, a BGA (Ball Grid Array) type semiconductor device is known as a kind of CSP. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a lattice pattern on one main surface of a package, and electrically connected to a semiconductor chip mounted on the other surface of the package. Is connected to.

  When this BGA type semiconductor device is incorporated into an electronic device, each conductive terminal is mounted on a wiring pattern on the printed circuit board to electrically connect the semiconductor chip and an external circuit mounted on the printed circuit board. Connected.

  Such a BGA type semiconductor device is provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. It has the advantage that it can be reduced in size. This BGA type semiconductor device has an application as an image sensor chip of a digital camera mounted on a mobile phone, for example.

  FIG. 14 shows a schematic configuration of a conventional BGA type semiconductor device, and FIG. 14A is a perspective view of the surface side of the BGA type semiconductor device. FIG. 14B is a perspective view of the back side of this BGA type semiconductor device.

  In this BGA type semiconductor device 101, a semiconductor chip 104 is sealed between first and second glass substrates 102 and 103 via epoxy resin layers 105a and 105b. A plurality of conductive terminals 106 are arranged in a grid pattern on one main surface of the second glass substrate 103, that is, on the back surface of the BGA type semiconductor device 101. The conductive terminal 106 is connected to the semiconductor chip 104 via the second wiring 110. Aluminum wires drawn from the inside of the semiconductor chip 104 are connected to the plurality of second wirings 110, respectively, and electrical connection between each conductive terminal 106 and the semiconductor chip 104 is made.

  A cross-sectional structure of the BGA type semiconductor device 101 will be described in more detail with reference to FIG. FIG. 15 is a cross-sectional view of the BGA type semiconductor device 101 divided into individual chips along the dicing line.

  A first wiring 107 is provided on the insulating layer 108 disposed on the surface of the semiconductor chip 104. The semiconductor chip 104 is bonded to the first glass substrate 102 by a resin layer 105a. Further, the back surface of the semiconductor chip 104 is bonded to the second glass substrate 103 by a resin layer 105b.

  One end of the first wiring 107 is connected to the second wiring 110. The second wiring 110 extends from one end of the first wiring 107 to the surface of the second glass substrate 103. A ball-shaped conductive terminal 106 is formed on the second wiring 110 extending on the second glass substrate 103.

The technique described above is described in Patent Document 1 below.
Patent Publication 2002-512436

  However, in the semiconductor device 101 described above, since the contact area between the first wiring 107 and the second wiring 110 is very small, there is a risk of disconnection at this contact portion. There was also a problem with the step coverage of the second wiring 110. Therefore, the present invention aims to improve the reliability of the semiconductor device and the manufacturing method thereof.

Therefore, the semiconductor device of the present invention is formed on the surface of the semiconductor substrate, the semiconductor substrate having a first opening that penetrates from the back surface to the surface and becomes a part of the via hole, and the first of the semiconductor substrate. A first insulating layer having a second opening that is continuous with the opening and becomes a part of the via hole, and a pad disposed on the first insulating layer so as to cover the second opening An electrode , and a wiring layer electrically connected to the pad electrode at the bottom of the via hole and extending to the back surface of the semiconductor substrate through the via hole , wherein the first opening is the semiconductor A portion close to the pad electrode is formed to spread laterally in a barrel shape so that an opening diameter of the portion close to the pad electrode is wider than a portion close to the back surface of the substrate, and the second opening is formed of the semiconductor Close to the surface of the board Than the portion, the opening diameter of the portion close to the pad electrode is formed to the tapered shape becomes narrower, and than the opening diameter of the portion close to the pad electrode of the first opening, the second The opening diameter of the portion of the opening close to the surface of the semiconductor substrate is narrower .

The opening diameter of the surface of the semiconductor substrate at the bottom of the first opening is wider than the planar width of the pad electrode. Further, a second insulating layer is formed on a sidewall of the via hole, and the wiring layer is formed on the second insulating layer .

Furthermore, a second insulating layer is formed on the side wall of the via hole, and the thickness of the end of the second insulating layer on the side wall of the second opening increases toward the center of the via hole. It is characterized by being formed thin. In addition, a support is formed on the surface side of the semiconductor substrate.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising preparing a semiconductor substrate having a pad electrode formed on a surface via a first insulating layer, and removing the semiconductor substrate from the back surface of the semiconductor substrate toward the surface. The first insulating layer is partially exposed to form a first opening that becomes a part of a via hole, and the exposed first insulating layer is removed, thereby removing the first insulating layer. Forming a second opening which is continuous with the first opening in one insulating layer and becomes a part of the via hole; and after forming the first and second openings, the bottom of the via hole Forming a wiring layer electrically connected to the pad electrode and extending to the back surface of the semiconductor substrate through the via hole, and forming the first opening removal of the semiconductor substrate, said first opening Than said portion close to the back surface of the semiconductor substrate, performs the opening diameter of the portion close to the pad electrode Ri is wide, so a portion close to the pad electrode of the first opening extending transverse to the barrel, the first The removal of the first insulating layer in the step of forming the second opening is such that the opening diameter of the portion close to the pad electrode is narrower than the portion of the second opening close to the surface of the semiconductor substrate. The opening diameter of the portion of the second opening close to the surface of the semiconductor substrate is narrower than the opening diameter of the portion of the first opening close to the pad electrode. It is characterized by performing as follows.

  Further, in the removal of the semiconductor substrate in the step of forming the first opening, the opening diameter of the surface of the semiconductor substrate at the bottom of the first opening is larger than the planar width of the pad electrode. It is performed as follows.

The method further includes the step of forming a second insulating layer on the sidewall of the via hole, wherein the wiring layer is formed on the second insulating layer .

Further, the step of forming the second insulating layer on the side wall of the via hole has a film thickness at the end of the second insulating layer on the side wall of the second opening as it goes toward the center of the via hole. It is characterized by performing so that it may form thinly.

  The step of forming the second insulating layer on the sidewall of the via hole may include forming a second insulating layer on the semiconductor substrate including the via hole and then using the resist layer formed on the semiconductor substrate as a mask. It has the process of removing the 2nd insulating layer on a pad electrode, It is characterized by the above-mentioned.

In the step of forming the second insulating layer on the sidewall of the via hole, the film thickness on the back surface of the semiconductor substrate including the via hole is larger than the film thickness on the pad electrode at the bottom of the via hole. After the second insulating layer is formed as described above, the second insulating layer is etched without using a resist layer, so that the second insulating layer on the back surface of the semiconductor substrate is completely removed. And a step of completely removing the second insulating layer on the pad electrode.

The method further includes a step of forming a conductive terminal connected to the wiring layer . Further, the method includes a step of dividing the semiconductor substrate into a plurality of semiconductor chips. The method further includes a step of forming a support on the surface side of the semiconductor substrate.

  According to the present invention, since the wiring from the pad electrode of the semiconductor chip to the conductive terminal is formed through the via hole, disconnection of the wiring and deterioration of the step coverage can be prevented. Thereby, a highly reliable semiconductor device can be obtained.

  According to the present invention, in addition to the via hole formed so as to reach the surface of the pad electrode from the back surface of the semiconductor substrate, the opening diameter of the portion near the back surface of the semiconductor substrate is closer to the pad electrode. Forming a first opening having a wide opening diameter; further, a portion connected to the first opening and closer to the pad electrode than a portion closer to the surface of the semiconductor substrate than the first insulating layer; By forming the second opening so that the opening diameter of the first insulating layer becomes narrower, for example, compared with a semiconductor device in which the opening diameter of the first insulating layer is the same over the entire thickness of the first insulating layer. Thus, the second insulating layer or conductive layer formed on the side wall of the via hole is caught in the portion where the opening diameter is widened, so that the second insulating layer or the conductive layer is not easily peeled off from the semiconductor substrate. Joint There is improved.

  Furthermore, since the opening diameter of the via hole formed on the surface of the pad electrode is increased, the stress can be relieved even if the conductive layer is subsequently filled.

  Also, after providing a second opening having a tapered shape (a shape in which the opening diameter becomes narrower toward the pad electrode side) in the first insulating layer on the pad electrode, the semiconductor substrate including the second opening The taper formed in the first insulating layer when the second insulating layer is covered and the third opening is formed in the second insulating layer to expose the pad electrode. Reflecting the shape, the end portion of the second insulating layer is formed such that its film thickness becomes thinner toward the center of the via hole. Therefore, the inner wall of the via hole can be formed smoothly, and the coverage of each layer formed thereafter can be improved.

  In addition, when the opening diameter of the surface of the semiconductor substrate at the bottom of the first opening is made wider than the planar width of the pad electrode, the stress accumulated in the pad electrode (accumulated during deposition of the pad electrode). (Stress) can be released efficiently. Therefore, it is possible to prevent deformation of the pad electrode when the first opening reaching the first insulating layer is formed or when the first insulating layer is removed to expose the pad electrode. Then, each layer formed on the pad electrode can be formed with good film quality, wiring connection failure and the like are suppressed, and the reliability of the semiconductor device is improved.

  Next, a first embodiment of a semiconductor device and a method for manufacturing the same according to the present invention will be described with reference to FIGS. 1 to 7 are cross-sectional views showing a semiconductor device applicable to an image sensor chip and a manufacturing method thereof.

  First, as shown in FIG. 1, a pad electrode made of an aluminum layer, an aluminum alloy layer, copper, or the like is provided on the surface of a semiconductor substrate 1 via a first insulating layer 2 made of, for example, a silicon oxide film or a silicon nitride film. 3 is formed. The pad electrode 3 is connected to a circuit element in the semiconductor chip. Then, for example, a glass substrate, a silicon substrate, a plastic substrate or the like is provided on the semiconductor substrate 1 including the pad electrode 3 covered with a passivation film made of a silicon oxide film, a silicon nitride film or the like via an adhesive 4 made of an epoxy resin or the like. The support 5 is bonded. A tape-shaped protective material may be bonded to the semiconductor substrate 1 instead of the glass substrate, silicon substrate, plastic substrate, or the like, and a double-sided adhesive tape or the like may be used as a support material.

Next, as shown in FIG. 2, a resist layer 6 having an opening is formed on the back surface of the semiconductor substrate 1 corresponding to the pad electrode 3, and dry etching is performed on the semiconductor substrate 1 using the resist layer 6 as a mask. A first opening 7 </ b> A that reaches the first insulating layer 2 on the pad electrode 3 from the back surface of the substrate 1 is formed. In this etching step, at least SF ₆ and O ₂ , or a semiconductor substrate made of Si using an etching gas containing a CF (fluorinated carbon) -based gas such as C ₂ F ₄ , C ₄ F ₈ , CHF ₃ or the like. 1 is etched. At this time, when the semiconductor substrate 1 is over-etched on the first insulating layer 2, the opening diameter of the portion close to the pad electrode 3 is larger than the opening diameter of the portion close to the back surface of the semiconductor substrate 1. A first opening 7A extending laterally is formed (K1 <K2).

Subsequently, as shown in FIG. 3, a CF (fluorinated carbon) -based etching gas such as CF ₄ or CHF _{3 is applied} to the first insulating layer 2 on the pad electrode 3 using the resist layer 6 as a mask. A second opening 7B is formed by removing the used etching to expose the pad electrode 3. The second opening 7 </ b> B is formed in the first insulating layer 2 continuously to the first opening 7 </ b> A, and is closer to the pad electrode 3 than the portion closer to the surface of the semiconductor substrate 1. The opening diameter is narrowed. That is, the second opening 7B has a tapered shape in which the opening diameter increases toward the surface of the semiconductor substrate 1 (K3> K4). At this time, in the etching process of the first insulating layer 2, the first opening 7 </ b> A has a larger opening diameter near the pad electrode 3 than the opening diameter near the back surface of the semiconductor substrate 1. Therefore, most of the etching gas entering from the narrow opening at the top of the first opening 7A hits the first insulating layer 2 above the pad electrode 3 from the vertical direction. A part of the etching gas hits the first insulating layer 2 from an oblique direction along the side wall shape of the first opening 7A. Therefore, as shown in FIG. 3, the pad electrode 3 is exposed in a state where the side wall shape of the first insulating layer 2 has a tapered shape in which the upper part of the opening is widened. Here, a via hole 8 is constituted by the first opening 7A and the second opening 7B.

  Further, even if the bottom of the first opening 7A is wide, the upper side walls of the resist layer 6 and the opening 7A serve as a mask, and the etching gas for the first insulating layer 2 is difficult to spread in the lateral direction. The opening diameter K3 above the first insulating layer 2 on the pad electrode 3 is substantially the same as the opening diameter K1 above the first opening 7A. Depending on the etching conditions, the opening diameter K4 may be substantially the same as the opening diameter K1 while maintaining the relationship of K3> K4.

  This step may be an etching step that does not use the resist layer 6 as a mask. In this case, after removing the resist layer 6, the first insulation on the pad electrode 3 using the semiconductor substrate 1 as a mask. Layer 2 is removed.

  Thereafter, a second insulating layer 9 made of a silicon oxide film or a silicon nitride film is formed on the back surface of the semiconductor substrate 1 including the inside of the via hole 8 as shown in FIG. 4, and on the pad electrode 3 as shown in FIG. The second insulating layer 9 is removed, and a second insulating layer 9 A is formed on the side wall portion of the via hole 8 and the back surface of the semiconductor substrate 1. At this time, after providing the tapered second opening 7B in the first insulating layer 2 on the pad electrode 3, the second insulating layer 9 is covered on the semiconductor substrate including the second opening 7B. Further, the second insulating layer 9 is partially etched to expose the pad electrode 3 again. A region of the via hole 8 on the first insulating layer 2 where the end X of the second insulating layer 9A is formed is referred to as a third opening for convenience. In FIG. 5, the end portion X of the second insulating layer 9A covers a part of the tapered portion of the first insulating layer 2 and the other portions are exposed, but by changing the etching conditions, The second insulating layer 9A can also be formed so that all of the first insulating layer 2 is covered.

  By adopting such a process, the tapered shape of the side wall of the second opening 7B formed in the first insulating layer 2 is reflected in the shape of the end X of the second insulating layer 9A. The end portion X of the second insulating layer 9 </ b> A is formed so that its film thickness decreases as it goes toward the center of the via hole 8. Since the end X of the second insulating layer 9A covers the first insulating layer 2 along the inclination, the vicinity of the third opening 8A is not angular as shown in FIG. It becomes a taper shape. Therefore, the entire inner wall of the via hole 8 can be formed smoothly, and the coverage of each layer of the barrier layer 10, the seed layer 11, and the wiring layer 12 formed thereafter can be improved. On the contrary, as shown in the reference diagram shown in FIG. 12, when there is a corner portion on the side wall of the first insulating layer 20 that is not tapered, the second insulating layer 21 and the barrier layer 22 are formed at the corner portion. , Regions Z having poor coverage are formed in the layers such as the seed layer 23 and the wiring layer 24. In addition, there is a possibility that problems such as concentration of an electric field at such a corner and deterioration of the withstand voltage or leakage may occur.

  In the process of this embodiment, after the first opening 7A is formed in the semiconductor substrate 1, the second insulation is formed on the first insulating layer 2 and the semiconductor substrate 1 including the inside of the first opening 7A. Compared with the process of forming the layer 9 and removing the first insulating layer 2 and the second insulating layer 9 by one etching to expose the pad electrode 3, the third of the sidewalls of the via hole 8 is the third. The shape in the vicinity of the opening 8A can be made a smoother tapered shape. This is because in the process of the present embodiment, the tapered shape of the side wall of the first insulating layer 2 is reflected in the shape of the end X of the second insulating layer 9A. As described above, in the present embodiment, a process preferable for improving the coverage of each layer such as the barrier layer 10, the seed layer 11, and the wiring layer 12 formed thereafter and manufacturing a highly reliable semiconductor device is adopted. ing.

  Subsequently, as shown in FIG. 6, a barrier layer 10 is formed on the back surface of the semiconductor substrate 1 including the inside of the via hole 8. The barrier layer 10 is preferably a titanium nitride (TiN) layer, for example, a refractory metal such as titanium (Ti) or tantalum (Ta) or a compound thereof, a titanium tungsten (TiW) layer, a tantalum nitride ( If it is a TaN) layer or the like, it may be made of a metal other than the titanium nitride layer.

  The step of forming the second insulating layer 9A includes forming a resist layer (not shown) on the semiconductor substrate 1 after forming the second insulating layer 9 on the semiconductor substrate 1 including the inside of the via hole 8. The second insulating layer 9 on the pad electrode 3 may be removed using the resist layer as a mask, or an etching process without using the resist layer as a mask.

  In the case of etching without using the resist layer as a mask, the coverage of the second insulating layer 9 on the via hole 8 is used. That is, in FIG. 4, for convenience, the second insulating layer 9 formed on the via hole 8 is shown to have a uniform film thickness, but the second insulating layer 9 actually formed is not shown. The film thickness is such that the thickness of the second insulating layer 9 formed on the semiconductor substrate 1 is larger than that of the second insulating layer 9 at the bottom of the via hole 8. The thickness of the second insulating layer 9 may be twice the thickness of the second insulating layer 9 at the bottom of the via hole 8. Therefore, by utilizing this characteristic, the second insulating layer 9 on the pad electrode 3 is completely removed before the second insulating layer 9 on the semiconductor substrate 1 is completely removed without forming a resist layer on the semiconductor substrate 1. The insulating layer 9 can be completely removed.

  At this time, it is preferable to use the etching characteristics of the second insulating layer 9 formed on the via hole 8. That is, the etching rate of the second insulating layer 9 formed at the bottom of the via hole 8 is lower than the etching rate of the second insulating layer 9 formed on the semiconductor substrate 1, and an example For example, the etching rate of the second insulating layer 9 on the semiconductor substrate 1 may be about 1.5 times higher than the etching rate of the second insulating layer 9 at the bottom of the via hole 8. Therefore, the reliability of the manufacturing process is improved by using both the covering property of the second insulating layer 9 and the etching property of the second insulating layer 9 described above.

  Further, as shown in FIG. 7, a seed layer 11 (for example, Cu layer) for plating is formed on the barrier layer 10, and a plating process is performed on the seed layer 11 to form a wiring layer made of, for example, copper (Cu). 12 is formed. As a result, the wiring layer 12 is electrically connected to the pad electrode 3 and extends to the back surface of the semiconductor substrate 1 through the via hole 8. The wiring layer 12 may be patterned or may not be patterned. Further, a protective layer (not shown) is formed on the wiring layer 12, and an opening is provided at a predetermined position of the protective layer. Then, after forming a metal layer (not shown) made of, for example, nickel and gold on the wiring layer 12 exposed at the opening, solder is screen printed, and the solder is reflowed by heat treatment to thereby conduct conductive terminals (electrode connection portions). The ball-shaped terminal 13 is formed. Depending on the mounting form, the ball-shaped terminal 13 may not be formed as a conductive terminal. In that case, the wiring layer 12 or a metal layer (not shown) such as nickel and gold is exposed, and becomes a conductive terminal when these layers are mounted.

  Here, the barrier layer 10 and the seed layer 11 can be formed by the MOCVD method, but in this case, there is a problem that the cost increases. Thus, by using a directional sputtering method such as a long throw sputtering method, which is less expensive than that, the coverage can be improved as compared with a normal sputtering method. By using this directional sputtering method, for example, the barrier layer 10 and the seed layer 11 can be formed with good coverage even for via holes having an inclination angle of less than 90 degrees or an aspect ratio of 3 or more. .

  Thereafter, although not shown, the semiconductor substrate and each of the layers stacked thereon are divided along a predetermined dicing line to be separated into individual semiconductor chips. In addition, as a method of separating into individual semiconductor chips, there are a dicing method, an etching method, a laser cut method and the like. Thus, a BGA type semiconductor device in which the pad electrode 3 and the ball terminal 13 are electrically connected is formed.

  Thus, in the present invention, the second insulating layer 9A, the barrier layer 10, the seed layer 11, and the wiring layer 12 formed on the side wall of the via hole 8 by the notch shape formed by the lateral etching at the bottom of the opening. However, it becomes a structure that is caught at the portion where the opening diameter is widened and is not easily peeled off from the semiconductor substrate 1. More specifically, the bondability between the pad electrode 3 and the seed layer 11, the wiring layer 12, etc. is improved.

  Furthermore, since the opening diameter of the via hole 8 that exposes the pad electrode 3 is widened, the stress can be relaxed even if the seed layer 11, the wiring layer 12, etc. are subsequently filled, and the reliability is improved.

  Similarly, the opening diameter of the portion close to the pad electrode 3 is narrower than the portion close to the surface of the semiconductor substrate 1 with respect to the first insulating layer 2 and connected to the first opening 7A. By forming the second opening 7B, for example, the semiconductor device in which the opening diameter of the opening formed in the first insulating layer 2A is the same over the entire thickness of the first insulating layer 2A. Compared with the above, stress concentration at the corners is suppressed, so that further stress relaxation can be achieved.

  Further, as shown in FIG. 13, when the via hole has a straight side wall or has a forward tapered shape or a bottom-side shape, an insulating layer 59A is formed on the side wall of the via hole 58A, and the insulating layer at the bottom of the via hole is formed. When etching is removed, the insulating layer 59A covered with the inclined portion of the bottom of the via hole is etched away (A portion in FIG. 13), and the insulating property at this portion may be lowered. However, the via hole shape of the present invention does not cause such etching scraping, and short circuit defects can be suppressed.

  According to the present invention, since the wiring from the pad electrode of the semiconductor chip to the conductive terminal is formed through the via hole, disconnection of the wiring and deterioration of the step coverage can be prevented. Thereby, a highly reliable semiconductor device can be obtained.

  Next, a second embodiment of the present invention will be described with reference to the drawings. In the semiconductor device and the manufacturing method thereof according to the first embodiment, when the via hole is formed, that is, when the first and second openings are formed, the pad electrode that should be originally kept in the horizontal state is the via hole. In some cases, it was pushed into the space on the 8th side and deformed into a curved shape.

  In the deformation of the pad electrode, the thermal stress (also referred to as residual stress or intrinsic stress) accumulated in the pad electrode at the time of forming the pad electrode in the previous process loses the previous balance due to a thermal load such as a thermal cycle test, It is thought that this happens to be released from the pad electrode in a concentrated manner. Such deformation of the pad electrode tends to occur when the first opening 7A reaching the first insulating layer 2 is formed or when the first insulating layer 2 is etched to expose the pad electrode 3. There is.

  Further, when the barrier layer 10, the seed layer 11, or the wiring layer 12 is formed in the via hole 8, the pad electrode 3 may be pulled toward the via hole 8 and the shape thereof may be deformed. The deformation at this time includes the residual stress accumulated in the barrier layer 10, the seed layer 11, and the wiring layer 12 when each layer is formed, and the stress accumulated in the pad electrode 3 when the pad electrode 3 is formed. It is thought to be caused by the relationship.

  Furthermore, such deformation of the pad electrode may cause damage or disconnection of the pad electrode, or the barrier layer 10, the seed layer 11, or the wiring layer 12 may be poorly covered, resulting in poor connection. As a result, the semiconductor device Reliability and yield may be reduced.

  Therefore, in the second embodiment of the present invention, the structure of the semiconductor device in which the deformation of the pad electrode 3 is further prevented and the manufacturing process thereof are employed. Although described below, the same reference numerals are used for the same configurations as those already described in the first embodiment, and description thereof is omitted.

  First, as shown in FIG. 1, a pad electrode 3 is formed on the surface of a semiconductor substrate 1 including an electronic device (not shown) via a first insulating layer 2. At this time, the pad electrode 3 is formed in a horizontal state, but it is considered that a certain amount of stress is accumulated. Next, the support 5 is attached to the surface of the semiconductor substrate 1 through the adhesive layer 4.

  Next, as shown in FIG. 8, a resist layer 6 having an opening is formed on the back surface of the semiconductor substrate 1 corresponding to the pad electrode 3, and the semiconductor substrate 1 is etched using the resist layer 6 as a mask. Forming a first opening 14 that reaches Here, the etching of the semiconductor substrate 1 is performed so that the opening diameter Y at the bottom of the first opening 14 is larger than the planar width K5 of the pad electrode 3. The opening diameter Y at the bottom of the first opening 14 is the opening diameter on the surface side of the semiconductor substrate 1 at the boundary between the semiconductor substrate 1 and the first insulating layer 2. In the figure, K6 is the opening diameter of the portion of the first opening 14 close to the back surface of the semiconductor substrate 1, and K7 is the opening diameter of the portion that is close to the surface of the semiconductor substrate 1 and spreads horizontally in a barrel shape. . Since the subsequent steps are the same as those already described, description thereof will be omitted. Thus, the semiconductor device according to the second embodiment is completed as shown in FIG.

  10 is a plan view showing the positional relationship between the pad electrode 3 and the bottom of the first opening 14 and the pad electrode. FIG. 10A shows the bottom of the first opening 14 with respect to the width K5 of the pad electrode 3. FIG. This shows an example in which the opening diameter Y is wider.

  In this way, by making the opening diameter Y at the bottom of the first opening 14 larger than the width K5 of the pad electrode 3, the stress accumulated during the formation of the pad electrode 3 reaches the first insulating layer 2. When the first opening 7A to be formed is formed, or when the pad electrode 3 is exposed by etching the first insulating layer 2, the pad electrode 3 is pushed out to the via hole 8 side. Can be prevented from bending. Accordingly, the pad electrode 3 is damaged or disconnected, the coverage of each layer (barrier layer 10, seed layer 11, wiring layer 12, etc.) formed on the pad electrode 3 is improved, and poor connection with the pad electrode 3 is suppressed. As a result, the reliability and yield of the semiconductor device can be improved.

  FIG. 10B shows an example in which the bottom of the first opening 14 has a wider area and a narrower area than the pad electrode 3a, and FIG. 10C shows a plurality of first electrodes on one pad electrode 3b. The example in which the opening part 14 was formed is shown. Thus, even if a part of the pad electrode partially overlaps the first opening 14, the stress accumulated in the pad electrode is released in the region where the opening diameter Y is wider than the pad electrode. Therefore, the occurrence of the bending can be prevented, and the reliability and yield of the semiconductor device can be improved.

  In the above embodiment, the wiring layer 12 is formed by plating. However, the present invention is not limited to this. For example, without forming the seed layer 11 for plating, other than plating. The wiring layer 12 may be formed by this method. For example, a layer made of aluminum or an alloy thereof may be formed by sputtering.

  Although the present embodiment is described as being applied to a semiconductor device in which the ball-shaped terminals 13 are formed, the present invention is not limited to this, and a via hole penetrating the semiconductor substrate is formed. The present invention can be applied to any semiconductor device, for example, an LGA (Land Grid Array) type semiconductor device.

  Moreover, although the above embodiment demonstrated embodiment which bonded the support body 5 to the surface of the semiconductor substrate 1, as shown to FIG. 11 (a), (b), the semiconductor device which does not use the support body 5, and its It can also be applied to manufacturing methods. Moreover, the support body 5 can also be removed after a semiconductor device is completed. 11A is substantially the same as that of the first embodiment described above, and the other configuration of FIG. 11B is substantially the same as that of the second embodiment described above. Those explanations are omitted.

  Further, in FIGS. 11A and 11B, a protective film 15 made of an insulator (for example, a passivation film or a film in which a passivation film and a resin such as a polyimide film are laminated) is formed on the semiconductor substrate 1 including the pad electrode 3. It is covered with. In FIGS. 11A and 11B, the protective film 15 completely covers the pad electrode 3. However, the pad electrode 3 may be partially covered and the pad electrode 3 may be partially exposed. . The exposed pad electrode 3 can be wire-bonded or a conductive terminal such as a bump electrode can be formed. Alternatively, when the semiconductor device is used for stacking with another semiconductor device, the pad electrode 3 and the conductive terminal of the other semiconductor device can be connected.

  Moreover, although the above embodiment demonstrated the case where the cross section (opening) of the via hole 8 was circular, the cross section of the via hole 8 can also be made into arbitrary shapes, such as an ellipse and a square.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which shows the positional relationship of the pad electrode which concerns on the 1st and 2nd embodiment of this invention, and the opening diameter of the bottom part of a 1st opening part. FIG. 2 is a reference diagram according to the first embodiment of the present invention. It is sectional drawing which shows the conventional semiconductor device. It is a perspective view which shows the conventional semiconductor device. It is sectional drawing which shows the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st insulating layer 3, 3a, 3b Pad electrode
4 Adhesive Layer 5 Support 6 Resist Layer 7A First Opening 7B Second Opening 8 Via Hole
9, 9A Second insulating layer 10 Barrier layer 11 Seed layer 12 Wiring layer 13 Ball-shaped terminal 14 First opening
20 First insulating layer 21 Second insulating layer 22 Barrier layer 23 Seed layer 24 Wiring layer

Claims (14)

A semiconductor substrate having a first opening that penetrates from the back surface to the front surface and becomes a part of the via hole;
A first insulating layer formed on a surface of the semiconductor substrate, having a second opening continuous with the first opening of the semiconductor substrate and serving as a part of the via hole;
A pad electrode disposed on the first insulating layer so as to cover the second opening;
A wiring layer electrically connected to the pad electrode at the bottom of the via hole and extending to the back surface of the semiconductor substrate through the via hole, and the first opening is a back surface of the semiconductor substrate The portion close to the pad electrode is formed to spread laterally in a barrel shape so that the opening diameter of the portion close to the pad electrode is wider than the portion close to
The second opening is formed in a tapered shape so that the opening diameter of the portion close to the pad electrode is narrower than the portion close to the surface of the semiconductor substrate, and the first opening A semiconductor device , wherein an opening diameter of a portion of the second opening close to the surface of the semiconductor substrate is narrower than an opening diameter of a portion close to the pad electrode .   2. The semiconductor device according to claim 1, wherein an opening diameter of the surface of the semiconductor substrate at the bottom of the first opening is wider than a planar width of the pad electrode. 3. The semiconductor device according to claim 1 , wherein a second insulating layer is formed on a sidewall of the via hole, and the wiring layer is formed on the second insulating layer . A second insulating layer is formed on a sidewall of the via hole;
3. The end portion of the second insulating layer on the side wall of the second opening is formed such that the film thickness thereof becomes thinner toward the center of the via hole. A semiconductor device according to 1.   The semiconductor device according to claim 1, wherein a support is formed on a surface side of the semiconductor substrate. Preparing a semiconductor substrate having a pad electrode formed on the surface via a first insulating layer;
Removing the semiconductor substrate in the direction from the back surface to the front surface of the semiconductor substrate to partially expose the first insulating layer and forming a first opening to be a part of a via hole;
Removing the exposed first insulating layer to form a second opening in the first insulating layer that is continuous with the first opening and becomes a part of the via hole; ,
Forming a wiring layer electrically connected to the pad electrode at the bottom of the via hole and extending to the back surface of the semiconductor substrate through the via hole after forming the first and second openings; And having
The removal of the semiconductor substrate of the first opening step of forming, the than the first partial opening is closer to the back surface of the semiconductor substrate, Ri a wide opening diameter of a portion close to the pad electrode, A portion close to the pad electrode of the first opening is performed so as to spread sideways in a barrel shape,
The removal of the first insulating layer in the step of forming the second opening is such that the opening diameter of the portion close to the pad electrode is narrower than the portion of the second opening close to the surface of the semiconductor substrate. The opening diameter of the portion of the second opening close to the surface of the semiconductor substrate is larger than the opening diameter of the portion of the first opening close to the pad electrode. A method for manufacturing a semiconductor device, characterized by being performed so as to be narrow .   The removal of the semiconductor substrate in the step of forming the first opening is performed so that the opening diameter of the surface of the semiconductor substrate at the bottom of the first opening is larger than the planar width of the pad electrode. The method of manufacturing a semiconductor device according to claim 6, wherein the method is performed. 8. The semiconductor according to claim 6, further comprising a step of forming a second insulating layer on a sidewall of the via hole, wherein the wiring layer is formed on the second insulating layer. Device manufacturing method. Forming the second insulating layer on the sidewall of the via hole;
The end portion of the second insulating layer on the side wall of the second opening is formed so as to decrease in thickness toward the center of the via hole. A method for manufacturing a semiconductor device.   The step of forming the second insulating layer on the side wall of the via hole includes forming the second insulating layer on the semiconductor substrate including the via hole and then using the resist layer formed on the semiconductor substrate as a mask. 10. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of removing the second insulating layer. In the step of forming the second insulating layer on the sidewall of the via hole, the film thickness on the back surface of the semiconductor substrate including the via hole is larger than the film thickness on the pad electrode at the bottom of the via hole. as after forming the second insulating layer,
By etching the second insulating layer without using a resist layer, the second insulating layer on the pad electrode is removed before the second insulating layer on the back surface of the semiconductor substrate is completely removed. 10. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of completely removing the semiconductor device. 12. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of forming a conductive terminal connected to the wiring layer .   13. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of dividing the semiconductor substrate into a plurality of semiconductor chips.   The method for manufacturing a semiconductor device according to claim 6, further comprising a step of forming a support on the surface side of the semiconductor substrate.

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