JP2005311117A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a high reliability high-density mounting semiconductor device exhibiting superior productivity. <P>SOLUTION: A groove 20, having a depth to the middle of thickness of a semiconductor chip 50, is formed in the semiconductor chip 50. The semiconductor chip 50 is divided into a first semiconductor region 50A (semiconductor thickness t1) where the groove 20 is not formed, and a second semiconductor region 50B (semiconductor thickness t2) which has become thinner than the first semiconductor region 50A, because the groove 20 has been formed. Furthermore, a via hole 21 is formed to penetrate the second semiconductor region 50B of the semiconductor chip 50. The rear surface of the semiconductor chip 50 and the sidewall of the via hole 21 are coated with an insulation layer 22. A wiring layer 23 is formed to extend over the rear surface of the semiconductor chip 50, i.e. over the first semiconductor region 50A and the second semiconductor region 50B, while being connected with pad electrodes 11 and 11 through the via hole 21. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor chip packaging technique.

  In recent years, CSP (Chip Size Package) has attracted attention as a three-dimensional mounting technique and as a new packaging technique. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip. Conventionally, a BGA type semiconductor device is known as a kind of CSP. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a lattice pattern on one main surface of a package, and electrically connected to a semiconductor chip mounted on the other surface of the package. Is connected to.

  When incorporating this BGA type semiconductor device into an electronic device, each conductive terminal is crimped to a wiring pattern on the printed circuit board, thereby electrically connecting the semiconductor chip and the external circuit mounted on the printed circuit board. Connected.

  Such a BGA type semiconductor device is provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. It has the advantage that it can be reduced in size. This BGA type semiconductor device has an application as an image sensor chip of a digital camera mounted on a mobile phone, for example.

  FIG. 17 shows a schematic configuration of a conventional BGA type semiconductor device, and FIG. 17A is a perspective view of the surface side of this BGA type semiconductor device. FIG. 17B is a perspective view of the back side of this BGA type semiconductor device.

  In this BGA type semiconductor device 101, a semiconductor chip 104 is sealed between first and second glass substrates 102 and 103 via epoxy resins 105a and 105b. On one main surface of the second glass substrate 103, that is, on the back surface of the BGA type semiconductor device 101, a plurality of ball-like terminals 106 are arranged in a lattice shape. The conductive terminal 106 is connected to the semiconductor chip 104 via the second wiring 110. Aluminum wires drawn from the inside of the semiconductor chip 104 are connected to the plurality of second wirings 110, and the respective ball-shaped terminals 106 and the semiconductor chip 104 are electrically connected.

  A cross-sectional structure of the BGA type semiconductor device 101 will be described in more detail with reference to FIG. FIG. 18 is a cross-sectional view of the BGA type semiconductor device 101 divided into individual chips along the dicing line. A first wiring 107 is provided on the insulating film 108 disposed on the surface of the semiconductor chip 104. The semiconductor chip 104 is bonded to the first glass substrate 102 with a resin 105a. The back surface of the semiconductor chip 104 is bonded to the second glass substrate 103 with a resin 105b.

  One end of the first wiring 107 is connected to the second wiring 110. The second wiring 110 extends from one end of the first wiring 107 to the surface of the second glass substrate 103. A ball-like conductive terminal 106 is formed on the second wiring extending on the second glass substrate 103.

The above-described technique is described in Patent Document 1 below, for example.
Patent Publication 2002-512436

  However, in the semiconductor device 101 described above, since the contact area between the first wiring 107 and the second wiring 110 is very small, there is a risk of disconnection at this contact portion. There was also a problem with the step coverage of the first wiring 107.

  The main features of the present invention are as follows. Other features of the present invention will be clarified in embodiments described later.

  The semiconductor device of the present invention includes a semiconductor chip having a first semiconductor region and a second semiconductor region thinner than the first semiconductor region. Electrodes are formed on the surface of the semiconductor chip. Also, a through hole penetrating the second semiconductor region of the semiconductor chip is provided, and an insulating layer is formed on the side wall of the through hole and the back surface of the semiconductor chip. And a wiring layer connected to the electrode through the through hole and extending on the insulating layer on the back surface of the semiconductor chip.

  Moreover, the manufacturing method of the semiconductor device of this invention prepares the semiconductor substrate by which the electrode was formed in the surface, and forms the through-hole which penetrates this semiconductor substrate. The peripheral region of this through hole is etched to the middle of the thickness of the semiconductor chip. Then, an insulating layer is deposited on the back surface of the semiconductor substrate in which the through hole is formed. The insulating layer at the bottom of the through hole is selectively etched to expose the electrode. A wiring layer connected to the electrode through the through hole and extending on the insulating layer on the back surface of the semiconductor substrate is formed. The semiconductor substrate that has undergone such a process is cut and separated into a plurality of semiconductor chips.

  The main effects obtained by the present invention are as follows. According to the present invention, the wiring layer connected to the electrode on the front surface of the semiconductor chip and extending to the back surface thereof through the through hole provided in the semiconductor chip is prevented, and the deterioration of the step coverage is prevented. A semiconductor device that can be mounted can be obtained. In particular, since the through hole is formed in a thin region of the semiconductor chip, the aspect ratio of the through hole can be substantially reduced. This facilitates the deposition of the insulating layer and the wiring layer on the side wall of the through hole, and can contribute to an increase in reliability and productivity of this type of semiconductor device.

  First, before describing an embodiment of the present invention, the structure of a semiconductor device as a premise thereof will be described with reference to FIGS. FIG. 1 is a plan view of a semiconductor wafer 100. The semiconductor wafer 100 (for example, a silicon wafer) has a plurality of semiconductor integrated circuit devices arranged in a matrix, and these semiconductor integrated circuit devices have a plurality of scribe lines SL provided in a row direction and a column direction. It is divided by. These semiconductor integrated circuit devices are cut and separated along these scribe lines SL to form a plurality of semiconductor chips 50. Therefore, in the following description, the semiconductor integrated circuit device before cutting and separation is also referred to as a semiconductor chip 50 for convenience.

  The semiconductor wafer 100 in FIG. 1 is a view seen from the back surface of the semiconductor chip 50. A plurality of external connection portions 51 are formed on the back surface of the semiconductor chip 50 along the end portions thereof. These external connection portions 51 are structures for obtaining an electrical connection between an electronic device or an electronic circuit provided on the semiconductor chip 50 and an external electrical component such as a printed circuit board, a lead frame, or another semiconductor chip. Thus, it may be formed in any region on the back surface of the semiconductor chip 50.

  FIG. 2 is an enlarged view of two adjacent external connection portions 51 (for example, a portion surrounded by a broken line) in FIG. 2A is a plan view of the external connection portion 51, and FIG. 2B is a cross-sectional view taken along the line AA in FIG. 2A. The semiconductor chip 50 having these external connection portions 51 is, for example, a CCD image sensor chip, and a pad electrode 11 is formed on the surface of the semiconductor chip 50 via an interlayer insulating layer 10 such as a BPSG film. The surface of the pad electrode 11 may be covered with a passivation film such as a silicon nitride film (not shown). A transparent or translucent glass substrate 200, which is a support for the semiconductor chip 50, is bonded to the surface of the semiconductor chip 50 on which the pad electrode 11 is formed via a resin layer 12 made of, for example, an epoxy resin. .

  In the case where the semiconductor chip 50 is a CCD image sensor chip, the support needs to be transparent or translucent in order to transmit light to the surface of the semiconductor chip 50. If there is no support, the support may be made of an opaque material. The support may be a tape. Further, when the semiconductor chip 50 is thick to some extent and it is not necessary to support it, the support may not be provided.

  Corresponding to the pad electrode 11, a via hole 13 that is a through hole penetrating the semiconductor chip 50 is formed. The side wall of the via hole 13 is inclined with respect to the back surface of the semiconductor chip 50. An insulating layer 14 is deposited on the back surface of the semiconductor chip 50 and the sidewalls of the via holes 13.

  A wiring layer 15 connected to the pad electrodes 11 and 11 through the via hole 13 and extending on the back surface of the semiconductor chip 50 is formed. The wiring layer 15 is formed on the insulating layer 14 and is electrically insulated from the semiconductor chip 50 by the insulating layer 14. The wiring layer 15 can be formed by sputtering a metal such as Al or by plating a metal such as copper (Cu). When the wiring layer 15 is formed by sputtering, the side wall of the via hole 13 needs to be inclined. The inclination angle is preferably 60 to 70 degrees.

  In the structure of the external connection portion 51 described above, the opening diameter of the via hole 13 decreases, and the thicker the semiconductor chip 50, the smaller the aspect ratio of the via hole 13 and the formation of the insulating layer 14 and the wiring layer 15 in the via hole 13. It becomes difficult. Further, when the side wall of the via hole 13 is inclined, it is possible to prevent the two adjacent via holes 13 and 13 from contacting each other and the two adjacent wiring layers 14 and 14 on the back surface of the semiconductor chip 50 from being short-circuited. In addition, there is a restriction that it is necessary to widen the distance L between two adjacent pad electrodes 11, 11, and there is a problem that the size of the semiconductor chip 50 is increased.

  Therefore, a first embodiment of the present invention that solves such a problem will be described. Also in this embodiment, the arrangement of the external connection portions 51 is the same as the arrangement shown in FIG. FIG. 3 is an enlarged view of two adjacent external connection portions 51 (for example, a portion surrounded by a broken line) in FIG. 3A is a plan view of the external connection portion 51, and FIG. 3B is a cross-sectional view taken along line BB in FIG. 3A. The semiconductor device is different from the semiconductor device of FIG. 2 in that a groove 20 having a depth up to the middle of the thickness is formed in the semiconductor chip 50. The semiconductor chip 50 includes a first semiconductor region 50A (semiconductor thickness t1) in which the groove 20 is not formed, and a second semiconductor region 50B that is thinner than the first semiconductor region 50A because the groove 20 is formed. (Semiconductor thickness t2).

  A via hole 21 penetrating the second semiconductor region 50B of the semiconductor chip 50 is formed. An insulating layer 22 is deposited on the back surface of the semiconductor chip 50 and the side wall of the via hole 21. A wiring layer 23 connected to the pad electrodes 11 and 11 through the via hole 21 and extending on the back surface of the semiconductor chip 50, that is, on the first semiconductor region 50A and the second semiconductor region 50B is formed. According to this embodiment, since the via hole 21 is formed in the second semiconductor region 50B due to the formation of the groove 20, the depth of the via hole 21 becomes shallow and the wiring layer 23 extending on the second semiconductor region 50B is formed. As the horizontal dimension decreases, the distance L2 between the two adjacent pad electrodes 11, 11 can be made smaller than the distance L in FIG. Thereby, the chip size of the semiconductor chip 50 can also be reduced.

  In addition, since the aspect ratio of the via hole 21 is substantially reduced, it becomes easy to form the insulating layer 14 and the wiring layer 15 in the via hole 21, leading to improvement in productivity and quality. Furthermore, the step coverage of the wiring layer 15 can be improved by inclining the side wall of the groove 20. In particular, the step coverage of the wiring layer 15 can be further improved by rounding the semiconductor end of the upper end K of the groove 20 by wet etching or the like described later.

Next, the manufacturing method of the semiconductor device of this embodiment will be described with reference to the drawings.
As shown in FIG. 4, a semiconductor integrated circuit device (for example, a CCD image sensor) (not shown) is formed on the surface of a semiconductor chip 50 that is a part of the semiconductor wafer 100. A pad electrode 11 is formed on the surface of the semiconductor chip 50 via an interlayer insulating layer 10. The pad electrode 11 is made of a metal such as aluminum, an aluminum alloy, or copper, and has a thickness of 1 μm. The pad electrode 11 can be formed using a sputtering method.

  A resin layer 12 made of, for example, an epoxy resin is applied to the surface of the semiconductor wafer 100 on which the pad electrode 11 is formed. Then, the glass substrate 200 is bonded to the surface of the semiconductor wafer 100 through the resin layer 12. The glass substrate 200 functions as a support or protective body for the semiconductor wafer 100. However, as described above, such a support does not necessarily have to be bonded. And in the state which this glass substrate 200 adhered, mechanical polishing of the back surface of the semiconductor wafer 100, what is called back grinding, is performed, and the thickness is processed thinly to 100-150 micrometers.

  Note that, after the back surface of the semiconductor wafer 100 is mechanically polished, the polishing surface may be smoothed by wet or dry etching. Further, only wet or dry etching treatment may be performed without performing such mechanical polishing.

  Then, as shown in FIG. 5, the semiconductor wafer 100 is selectively etched to form a via hole 21 </ b> A that penetrates the semiconductor wafer 100 and exposes the interlayer insulating layer 10 on the surface of the pad electrode 11. In this example, the side wall of the via hole 21A is inclined with respect to the back surface of the semiconductor wafer 100 (semiconductor chip 50) by etching the semiconductor wafer 100 by isotropic dry etching or wet etching. The inclination angle is preferably 60 to 70 degrees when the wiring layer 23 is formed by sputtering.

  The depth of the via hole 21 </ b> A is 100 to 150 μm, which is the same as the thickness of the semiconductor wafer 100. In order to form the via hole 221A, there is a method of making a hole in the semiconductor wafer 100 using a laser beam in addition to etching. At this time, the via hole 21A can be processed so that the side wall thereof is inclined by controlling the energy density of the laser beam.

  Next, as shown in FIG. 6, a photoresist layer PR having an opening is formed on the region surrounding the via holes 21A and 21A, and the semiconductor wafer 100 is etched halfway through its thickness using the photoresist layer PR as a mask. A hard mask made of a silicon oxide film or the like may be used instead of the photoresist layer PR. Thereby, the groove 20 is formed on the back surface of the semiconductor wafer 100. Etching at this time is isotropic dry etching or wet etching, so that the side wall of the groove 20 is also processed to have an inclination. Further, the semiconductor end of the upper end K of the groove 20 is rounded, and the step coverage of the wiring layer 23 is improved.

  By forming the groove 20, a structure in which the shallow via holes 21 and 21 are formed in the relatively thin second semiconductor region 50B is obtained. The thickness t1 of the first semiconductor region 50A is 100 to 150 μm, which is the same as the thickness of the semiconductor wafer 100, and the thickness t2 of the second semiconductor region 50B is preferably 50 to 70 μm. According to the embodiment described above, the groove 20 is formed after the via hole 21A is formed. However, the via hole 21A may be formed after the groove 20 is formed. Since it takes more time to deeply drill the opening having the small diameter as described above, the latter can shorten the working time.

  Next, as shown in FIG. 7, an insulating layer 22 is deposited on the entire back surface of the semiconductor wafer 100. The insulating layer 22 can be formed, for example, by depositing silicon oxide by a CVD method. Since the via hole 21 is formed shallow, its aspect ratio is reduced, and silicon oxide can be easily deposited on the side wall of the via hole 21 to improve productivity.

  Next, as shown in FIG. 8, the interlayer insulating layer 10 and the insulating layer 22 on the bottom of the via hole 21 are selectively removed. Specifically, for example, a photoresist layer (not shown) having an opening corresponding to the bottom of the via hole 21 is formed, and the interlayer insulating layer 10 and the insulating layer 22 are etched using this photoresist layer as a mask. A hard mask made of a silicon oxide film or the like may be used instead of the photoresist layer.

  Then, as shown in FIG. 3, a wiring layer 23 connected to the pad electrodes 11 and 11 through the via hole 21 and extending on the back surface of the semiconductor chip 50, that is, on the first semiconductor region 50A and the second semiconductor region 50B is formed. To do. Since the side wall of the via hole 21 is inclined, the wiring layer 23 can be formed so as to cover the side wall by sputtering a metal such as aluminum or aluminum alloy. Furthermore, in order to improve the corrosion resistance, Ni and Au may be formed by plating after the wiring layer is processed.

  The wiring layer 23 can also be formed using a plating method. In this case, a seed layer made of copper (Cu) is formed on the entire back surface of the semiconductor wafer 100 by electroless plating. Its thickness may be 1 μm. If the sidewall of the via hole 21 has an inclination, a sputtering method can be used for forming the seed layer. Then, the wiring layer 23 is formed by performing electrolytic plating of copper (Cu). At this time, a photoresist layer is formed in a portion where the wiring layer 23 is not formed.

  Conductive terminals such as solder bumps may be formed on the wiring layer 23 thus formed. In this case, a barrier metal layer made of Ni / Au or the like is formed on the wiring layer 23 by sputtering, and a conductive terminal is formed on the barrier metal layer. Further, a protective layer such as a solder mask may be formed on the wiring layer 23.

  Then, the semiconductor wafer 100 is cut and separated into a plurality of semiconductor chips 50 along the scribe line SL of FIG. In this scribing step, a laser beam can be used. Further, in the scribing process using a laser beam, the glass substrate 200 can be prevented from being cracked by processing the cut surface of the glass substrate 200 to be tapered.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings. As shown in FIG. 9, the pad electrode 11 is formed on the surface of the semiconductor chip 50 that is a part of the semiconductor wafer 100 via the interlayer insulating layer 10. A resin layer 12 made of, for example, an epoxy resin is applied to the surface of the semiconductor wafer 100 on which the pad electrode 11 is formed. Then, the glass substrate 200 is bonded to the surface of the semiconductor wafer 100 through the resin layer 12. Then, with the glass substrate 200 adhered, mechanical polishing of the back surface of the semiconductor wafer 100, so-called back grinding, is performed, and the thickness is reduced to 130 μm. The process up to this point is the same as in the first embodiment.

  Then, the semiconductor wafer 100 is selectively etched to form a via hole 31 </ b> A that penetrates the semiconductor wafer 100 and exposes the interlayer insulating layer 10 on the surface of the pad electrode 11. In this example, anisotropic dry etching is performed on the semiconductor wafer 100 so that the side wall of the via hole 31A stands perpendicular to the back surface of the semiconductor wafer 100 (semiconductor chip 50). The depth of the via hole 31 </ b> A is 130 μm, which is the same as the thickness of the semiconductor wafer 100.

  Next, as shown in FIG. 10, a photoresist layer PR2 having an opening is formed on the region surrounding the via holes 31A, 31A, and the semiconductor wafer 100 is etched halfway through its thickness using the photoresist layer PR2 as a mask. Thereby, the groove 30 is formed on the back surface of the semiconductor wafer 100. By performing anisotropic dry etching at this time, the side walls of the grooves 30 are also processed so as to stand vertically.

  By forming the groove 30, a structure in which shallow via holes 31, 31 are formed in the relatively thin second semiconductor region 51B is obtained. The thickness t1 of the first semiconductor region 51A is 130 μm, which is the same as the thickness of the semiconductor wafer 100, and the thickness t2 of the second semiconductor region 50B is preferably 70 μm. According to the embodiment described above, the groove 30 is formed after the via hole 31A is formed. Conversely, the via hole 31A may be formed after the groove 30 is formed. Since it takes more time to deeply drill the opening having the small diameter as described above, the latter can shorten the working time.

  Next, as shown in FIG. 11, an insulating layer 32 is deposited on the entire back surface of the semiconductor wafer 100. The insulating layer 32 can be formed, for example, by depositing silicon oxide by a CVD method. Since the via hole 31 is shallow, the aspect ratio is small, and silicon oxide can be easily deposited on the side wall of the via hole 31.

  Next, as shown in FIG. 12, the interlayer insulating layer 10 and the insulating layer 32 on the bottom of the via hole 31 are selectively removed. Specifically, for example, a photoresist layer (not shown) having an opening corresponding to the bottom of the via hole 31 is formed, and the interlayer insulating layer 10 and the insulating layer 32 are etched using this photoresist layer as a mask.

  Then, as shown in FIG. 13, a wiring layer 33 is formed which is connected to the pad electrodes 11 and 11 through the via hole 31 and extends on the back surface of the semiconductor chip 50, that is, on the first semiconductor region 51A and the second semiconductor region 51B. To do. The wiring layer 23 can be formed using a plating method or a CVD method.

  In this way, two adjacent external connection portions 51 are obtained. A conductive terminal such as a solder bump may be formed on the wiring layer 33. In this case, a barrier metal layer made of Ni / Au or the like is formed on the wiring layer 33 by sputtering, and a conductive terminal is formed on the barrier metal layer. Further, a protective layer such as a solder mask may be formed on the wiring layer 33.

  Then, the semiconductor wafer 100 is cut and separated into a plurality of semiconductor chips 50 along the scribe line SL of FIG. In this scribing step, a laser beam can be used. Further, in the scribing process using a laser beam, the glass substrate 200 can be prevented from cracking by processing the cut surface of the glass substrate 200 to be oblique.

  Next, a third embodiment of the present invention will be described in detail with reference to the drawings. This embodiment relates to the arrangement of the external connection portions 51 of the first and second embodiments, particularly the arrangement relationship between the via hole 21 and the groove 20 and the arrangement relationship between the via hole 31 and the groove 30. Here, the external connection portion 51 of the first embodiment will be described as an example, but the external connection portion 51 of the second embodiment can be arranged in exactly the same manner.

  As shown in FIG. 14, a plurality of external connection portions 51 are arranged along the end portion of the semiconductor chip 50 of the semiconductor wafer 100. And the via hole 21 of these external connection parts is formed in the area | region in which the elongate groove | channel 20 connected to one is formed, ie, the thin 2nd semiconductor region 50B. In such an arrangement, the first semiconductor region 50A protruding from the second semiconductor region 50B is formed in a long strip shape along the scribe line SL.

  Then, when the semiconductor wafer 100 is cut and separated along the scribe line SL, the impact may cause cracks in the long semiconductor first semiconductor region 50A. When a crack enters the first semiconductor region 50A, moisture and the like enter the external connection portion 51 through the crack, and the reliability of the semiconductor chip 50 is deteriorated.

  Therefore, as shown in FIG. 15, a plurality of grooves 20 (second semiconductor regions 50B) separated from each other are formed, and the external connection portion 51 is formed in each groove 20 (second semiconductor region 50B). One or more via holes 21 are formed. As a result, the band-shaped first semiconductor region 50A merges with the main body of the first semiconductor region 50A in the middle thereof, the length of the band-shaped first semiconductor region 50A is shortened, and the influence of the impact at the time of scribing is reduced. Since it becomes difficult to receive, generation | occurrence | production of a crack is prevented as much as possible.

  Alternatively, as shown in FIG. 16, a wide groove 20 (second semiconductor region 50B) may be formed from the end of the semiconductor chip 50 to a region including the scribe line SL. As a result, the strip-shaped first semiconductor region 50A is not formed at all, and the occurrence of cracks is prevented.

It is a top view of a semiconductor wafer. It is an enlarged view of the two adjacent external connection parts 51 in FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention. 6 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the invention. FIG. 6 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the invention. FIG. 6 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the invention. FIG. FIG. 6 is a plan view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 1A and 1B are diagrams illustrating a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention. It is a figure explaining the semiconductor device which concerns on the 2nd Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a top view of the semiconductor device concerning a 3rd embodiment of the present invention. It is a top view of the semiconductor device concerning a 3rd embodiment of the present invention. It is a top view of the semiconductor device concerning a 3rd embodiment of the present invention. It is a figure explaining the conventional semiconductor device. It is sectional drawing of the conventional semiconductor device.

Claims (21)

A semiconductor chip having a first semiconductor region and a second semiconductor region thinner than the first semiconductor region;
An electrode formed on the surface of the semiconductor chip;
A through hole penetrating the second semiconductor region of the semiconductor chip;
An insulating layer formed on the side wall of the through hole and the back surface of the semiconductor chip;
A semiconductor device comprising: a wiring layer connected to the electrode through the through hole and extending on the insulating layer on a back surface of the semiconductor chip. The semiconductor device according to claim 1, wherein a side wall of the through hole is inclined with respect to a back surface of the semiconductor chip. The semiconductor device according to claim 1, wherein a side wall of the through hole is perpendicular to a back surface of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein a step surface of a semiconductor step existing at a boundary between the first semiconductor region and the second semiconductor region is inclined with respect to a back surface of the semiconductor chip. The semiconductor device according to claim 1, further comprising a conductive terminal on the wiring layer. The semiconductor device according to claim 1, wherein a support for supporting the semiconductor chip is bonded to a surface of the semiconductor chip. A semiconductor chip having a first semiconductor region and a second semiconductor region thinner than the first semiconductor region;
A plurality of electrodes disposed on a surface of the semiconductor chip;
A plurality of through holes penetrating the second semiconductor region of the semiconductor chip;
A semiconductor device comprising: a plurality of wiring layers connected to the plurality of electrodes through the plurality of through holes and extending to a back surface of the semiconductor chip. The semiconductor device according to claim 7, wherein a plurality of the second semiconductor regions are provided along a scribe line of the semiconductor chip, and at least one through hole is provided in each of the second semiconductor regions. The semiconductor device according to claim 7, wherein the second semiconductor region is provided in a region including a scribe line of the semiconductor chip. Prepare a semiconductor substrate with electrodes on the surface,
A first etching step of forming a through hole penetrating the semiconductor substrate;
A second etching step of etching the peripheral region of the through hole to the middle of the thickness of the semiconductor substrate;
Depositing an insulating layer on the back surface of the semiconductor substrate in which the through hole is formed;
A third etching step of selectively etching the insulating layer at the bottom of the through hole to expose the electrode;
Forming a wiring layer connected to the electrode through the through hole and extending on the insulating layer on the back surface of the semiconductor substrate;
And a step of cutting and separating the semiconductor substrate into a plurality of semiconductor chips. The method of manufacturing a semiconductor device according to claim 10, wherein the first etching step is performed by isotropic etching. The method of manufacturing a semiconductor device according to claim 10, wherein the first etching step is performed by anisotropic etching. The method of manufacturing a semiconductor device according to claim 10, wherein the second etching step is performed by isotropic etching. The method of manufacturing a semiconductor device according to claim 10, wherein the second etching step is performed by anisotropic etching. Prepare a semiconductor substrate with electrodes on the surface,
First etching a predetermined region of the back surface of the semiconductor substrate to the middle of its thickness;
A second etching step of forming a through hole penetrating the semiconductor substrate in the etched predetermined region;
Depositing an insulating layer on the back surface of the semiconductor substrate in which the through hole is formed;
A third etching step of selectively etching the insulating layer at the bottom of the through hole to expose the electrode;
Forming a wiring layer connected to the electrode through the through hole and extending on the insulating layer on the back surface of the semiconductor chip;
And a step of cutting and separating the semiconductor substrate into a plurality of semiconductor chips. The method of manufacturing a semiconductor device according to claim 15, wherein the first etching step is performed by isotropic etching. The method of manufacturing a semiconductor device according to claim 15, wherein the first etching step is performed by anisotropic etching. The method of manufacturing a semiconductor device according to claim 15, wherein the second etching step is performed by isotropic etching. The method of manufacturing a semiconductor device according to claim 15, wherein the second etching step is performed by anisotropic etching. 16. The method for manufacturing a semiconductor device according to claim 10, further comprising a step of bonding a support to the surface of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 10, further comprising a step of forming a conductive terminal on the wiring layer.

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