KR930006867A - Loc 패키지 및 그 제조방법 - Google Patents

Loc 패키지 및 그 제조방법 Download PDF

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KR930006867A
KR930006867A KR1019910015863A KR910015863A KR930006867A KR 930006867 A KR930006867 A KR 930006867A KR 1019910015863 A KR1019910015863 A KR 1019910015863A KR 910015863 A KR910015863 A KR 910015863A KR 930006867 A KR930006867 A KR 930006867A
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South Korea
Prior art keywords
loc package
inner lead
package according
chip
forming
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KR1019910015863A
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KR940006083B1 (ko
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이희국
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문정환
금성일렉트론주식회사
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Priority to KR1019910015863A priority Critical patent/KR940006083B1/ko
Priority to TW081106880A priority patent/TW301045B/zh
Priority to DE4230187A priority patent/DE4230187B4/de
Priority to US07/943,908 priority patent/US5742096A/en
Priority to JP04243295A priority patent/JP3121450B2/ja
Publication of KR930006867A publication Critical patent/KR930006867A/ko
Priority to US08/141,455 priority patent/US5358906A/en
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Publication of KR940006083B1 publication Critical patent/KR940006083B1/ko

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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Abstract

본 발명은 LOC패키지 및 그제조방법에 관한 것으로서, 특히 기계적인 강도 및 박형화를 이룰수 있도록 한 것이다.
이를 위해, 본 발명은 칩(11)의 상면에 형성되는 중합체(13)와 인너리드(14)의 양면에 요철면을 형성하여 이들을 상호 접속되도록 한 것이다.

Description

LOC 패키지 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 의한 LOC 패키지의 구조를 나타낸 종단면도,
제3도는 제2도의 "A"부 상세도,
제4도는 본 발명에 의한 LOC 패키지 제조공정에 있어서, 솔더링 공정을 나타낸 평면도,
제5도는 본 발명의 다른 실시예를 나타낸 종단면도.

Claims (11)

  1. 칩(11)의 표면에 미세한 돌기(12)를 형성하고 중합체(13)와 인너리드(14)의 상하방에는 요철면을 각각 형성하여 이들을 차례로 접합시켜서된 LOC 패키지.
  2. 제1항에 있어서, 중합체(13)를 플로로에틸렌계의 필름으로 하여서된 LOC 패키지.
  3. 제1항 또는 제2항에 있어서, 중합체(13)의 두께를 60-70㎛으로 하여서된 LOC 패키지.
  4. 제1항에 있어서, 인너리드(14)와 이우터리드(18)를 별도로 형성하여 탭 또는 C-4본딩하여서된 LOC 패키지.
  5. 제1항에 있어서, 칩(11)의 패드(15)에 접속되는 인너리드(14)부분의 폭을 좁게 한후 이들을 상호 교호되게 설치하여서 된 LOC 패키지.
  6. 제1항에 있어서, 인너리드(14)에 일정간격으로 통공을 형성하여서된 LOC 패키지.
  7. 칩(11)의 표면에 미세한 돌기(12)를 형성하는 증착 공정과, 상기 돌기(12)의 상부에 요철면을 가진 중합체(13)를 형성하는 공정과, 상기 중합체(13)의 요철면과 접속되게 인너리드(14)에 요철면을 형성하는 공정과, 상기 각 칩(11)의 패드(15)에 솔더(16)를 형성하는 솔더공정과, 상기 솔더(16)에 프레임의 각 인너리드(14)를 솔더링하여 칩(11)과 인너리드(14)을 포함하는 일정면적을 몰딩하는 몰딩공정과, 상기 몰딩된 패키지를 트리밍/포밍하는 공정을 포함하는 LOC패키지 제조방법.
  8. 제7항에 있어서, 칩(11)의 표면에 형성된 미세한 돌기(12)를 저온에서 RF-스퍼터링 방법으로 형성하여서 된 LOC 패키지 제조방법.
  9. 제7항 또는 제8항에 있어서, 미세한 돌기 (12)를 Si3N4나 SiO2로 하여서된 LOC 패키지 제조방법.
  10. 제7항 또는 제8항에 있어서, 미세한 돌기 (12)의 두께를 400-500A으로 하여서 된 LOC 패키지 제조방법.
  11. 제7항에 있어서, 요철면을 가진 로울러를 이용하여 리드프레임의 인너리드(14)에 요철면을 형성하여서된 LOC 패키지 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910015863A 1991-09-11 1991-09-11 Loc 패키지 및 그 제조방법 KR940006083B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019910015863A KR940006083B1 (ko) 1991-09-11 1991-09-11 Loc 패키지 및 그 제조방법
TW081106880A TW301045B (ko) 1991-09-11 1992-08-31
DE4230187A DE4230187B4 (de) 1991-09-11 1992-09-09 Baueinheit mit Speicher-IC, sowie Verfahren zum Herstellen einer solchen Baueinheit
US07/943,908 US5742096A (en) 1991-09-11 1992-09-11 Lead on chip package
JP04243295A JP3121450B2 (ja) 1991-09-11 1992-09-11 Ｌｏｃパッケージおよびその製造方法
US08/141,455 US5358906A (en) 1991-09-11 1993-10-22 Method of making integrated circuit package containing inner leads with knurled surfaces

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KR1019910015863A KR940006083B1 (ko) 1991-09-11 1991-09-11 Loc 패키지 및 그 제조방법

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KR930006867A true KR930006867A (ko) 1993-04-22
KR940006083B1 KR940006083B1 (ko) 1994-07-06

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DE4230187B4 (de) 2007-02-01
KR940006083B1 (ko) 1994-07-06
TW301045B (ko) 1997-03-21
DE4230187A1 (de) 1993-03-18
JPH06169052A (ja) 1994-06-14
US5742096A (en) 1998-04-21
JP3121450B2 (ja) 2000-12-25
US5358906A (en) 1994-10-25

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