KR960026692A - 반도체 패키지 및 그 제조방법 - Google Patents

반도체 패키지 및 그 제조방법 Download PDF

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Publication number
KR960026692A
KR960026692A KR1019940035092A KR19940035092A KR960026692A KR 960026692 A KR960026692 A KR 960026692A KR 1019940035092 A KR1019940035092 A KR 1019940035092A KR 19940035092 A KR19940035092 A KR 19940035092A KR 960026692 A KR960026692 A KR 960026692A
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South Korea
Prior art keywords
inner lead
hole
semiconductor package
lead
solder
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KR1019940035092A
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English (en)
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KR0141952B1 (ko
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권용태
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문정환
Lg 반도체 주식회사
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Priority to KR1019940035092A priority Critical patent/KR0141952B1/ko
Priority to US08/370,903 priority patent/US5559372A/en
Priority to JP1615595A priority patent/JP2602182B2/ja
Publication of KR960026692A publication Critical patent/KR960026692A/ko
Application granted granted Critical
Publication of KR0141952B1 publication Critical patent/KR0141952B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/30—Technical effects
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    • H01L2924/30107—Inductance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 리드 프레임 패들과 리드 프레임의 인너리드를 직접 솔더링하는 반도체 패키지 및 그 제조방법에 관한 것이다.본 발명의 반도체 패키지는 리드 프레임의 소정부위에 패들을 설치시키고, 패들의 일측에는 인너리드가, 타측에는 보조리드가 각각 설치되며, 인너리드와 상기 보조리드의 연결부에는 적어도 1개 이상의 인너리드 홀이 설치되며, 상기 인너리드홀의 상부에는 상기 인너리드 홀과 연통되게 솔더 레지스터 필름상에 솔더 레지스터 홀이 적어도 1개 이상 설치된다. 이와 같은 본 발명의 반도체 패키지는 와이어 본딩공정을 수행하지 않으므로 패키지를 소형화 및 박형화시킬 수 있다.

Description

반도체 패키지 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 일실시예에 따른 패키지의 상면도, 제3도의 (가) 내지 (다)는 본 발명의 일실시예에 따른 인너리드홀의 다양한 형태를 나타낸 평면도, 제4도의 (가)는 제3도의 (가)에서 B-B' 선상을 취한 단면도, 제4도의 (나)는 제3도의 (가)에서 C-C' 선상을 취한 단면도.

Claims (7)

  1. 리드 프레임의 소정 부위에 설치된 패들의 일측에는 인너리드가, 타측에는 보조리드가 각각 설치되며, 상기 인너리드와 상기 보조리드의 연결부에는 적어도 1 개 이상의 인너리드 홀이 설치되며, 상기 인너리드 홀의 상부에는상기 인너리드 홀과 연통되게 솔더 레지스터 필름상에 솔더 레지스터 홀이 적어도 1 개 이상 설치되는 것을 특징으로 하는 반도체 패키지.
  2. 제1항에 있어서, 상기 인너리드 홀은 원 형태로 형성되는 것을 특징으로 하는 반도체 패키지.
  3. 제1항에 있어서, 상기 인너리드 홀은 사각형 형태로 형성되는 것을 특징으로 하는 반도체 패키지.
  4. 제1항에 있어서, 상기 인너리드 홀은 반원형태로 형성되는 것을 특징으로 하는 반도체 패키지.
  5. 제1항에 있어서, 상기 솔더 레지스터 홀은 상기 인너리드 홀 보다 더 크게 형성되는 것을 특징으로 하는반도체 패키지.
  6. 리드 프레임상에 솔더 레지스터 필름을 부착하는 단계와; 상기 리드 프레임의 인너리드가 패들과 직접 접촉할 수 있도록 리드 패턴을 형성하여 에칭하는 단계와; 상기 패들과 인너리드를 솔더링하는 단계와; 상기 리드 프레임을 에폭시 몰드 컴파운드로 몰딩하는 단계와; 상기 리드 프레임의 사이드 레일을 절단하고, 패키지의 고유형태로 절단하는 트림 및 포밍단계와; 소정의 도금피막을 얻기 위하여 틴(tin) 단계로 구성되는 것을 특징으로 반도체 패키지 제조 방법.
  7. 제6항에 있어서, 상기 솔더링 단계에서 솔더 레지스터 홀 및 인너리드 홀에는 솔더를 주입한 후, 열기를불어줌에 의해 불필요한 솔더가 제거될 수 있도록 구성되는 것을 특징으로 하는 반도체 패키지 제조 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940035092A 1994-12-19 1994-12-19 반도체 패키지 및 그 제조방법 KR0141952B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019940035092A KR0141952B1 (ko) 1994-12-19 1994-12-19 반도체 패키지 및 그 제조방법
US08/370,903 US5559372A (en) 1994-12-19 1995-01-10 Thin soldered semiconductor package
JP1615595A JP2602182B2 (ja) 1994-12-19 1995-02-02 半導体パッケージおよびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940035092A KR0141952B1 (ko) 1994-12-19 1994-12-19 반도체 패키지 및 그 제조방법

Publications (2)

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KR960026692A true KR960026692A (ko) 1996-07-22
KR0141952B1 KR0141952B1 (ko) 1998-06-01

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US (1) US5559372A (ko)
JP (1) JP2602182B2 (ko)
KR (1) KR0141952B1 (ko)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2734983B1 (fr) * 1995-05-29 1997-07-04 Sgs Thomson Microelectronics Utilisation d'un micromodule comme boitier de montage en surface et procede correspondant
KR100307776B1 (ko) * 1995-06-06 2001-11-22 엔도 마사루 프린트배선판
JP2899540B2 (ja) * 1995-06-12 1999-06-02 日東電工株式会社 フィルムキャリアおよびこれを用いた半導体装置
JP2894254B2 (ja) * 1995-09-20 1999-05-24 ソニー株式会社 半導体パッケージの製造方法
US5966592A (en) * 1995-11-21 1999-10-12 Tessera, Inc. Structure and method for making a compliant lead for a microelectronic device
KR100214480B1 (ko) * 1996-05-17 1999-08-02 구본준 반도체 패키지용 리드 프레임
KR100186333B1 (ko) * 1996-06-20 1999-03-20 문정환 칩 사이즈 반도체 패키지 및 그 제조방법
JP3050812B2 (ja) 1996-08-05 2000-06-12 イビデン株式会社 多層プリント配線板
JPH11233684A (ja) * 1998-02-17 1999-08-27 Seiko Epson Corp 半導体装置用基板、半導体装置及びその製造方法並びに電子機器
US6232666B1 (en) * 1998-12-04 2001-05-15 Mciron Technology, Inc. Interconnect for packaging semiconductor dice and fabricating BGA packages
US6310390B1 (en) * 1999-04-08 2001-10-30 Micron Technology, Inc. BGA package and method of fabrication
JP3356121B2 (ja) * 1999-07-02 2002-12-09 株式会社村田製作所 非可逆回路素子および通信装置
US7190157B2 (en) * 2004-10-25 2007-03-13 Agilent Technologies, Inc. Method and apparatus for layout independent test point placement on a printed circuit board
JP4533248B2 (ja) * 2005-06-03 2010-09-01 新光電気工業株式会社 電子装置
US9653424B2 (en) * 2009-09-21 2017-05-16 Alpha And Omega Semiconductor Incorporated Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method
TWI657237B (zh) * 2018-02-21 2019-04-21 茂達電子股份有限公司 光學偵測裝置及光學封裝結構
KR102169230B1 (ko) 2019-04-22 2020-10-23 강해일 비상 전력 및 블루투스 통신을 활용한 도어락 개폐 시스템 및 그 운영 방법

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3706409A (en) * 1970-02-26 1972-12-19 Gen Electric Semiconductor lead attachment system including a semiconductor pellet orientation plate
JPS5232267A (en) * 1975-09-05 1977-03-11 Citizen Watch Co Ltd Ic packaging construction
JPS53147968A (en) * 1977-05-30 1978-12-23 Hitachi Ltd Thick film circuit board
JPS5548954A (en) * 1978-10-03 1980-04-08 Toshiba Corp Manufacturing of film carrier
US4626478A (en) * 1984-03-22 1986-12-02 Unitrode Corporation Electronic circuit device components having integral spacers providing uniform thickness bonding film
US4811081A (en) * 1987-03-23 1989-03-07 Motorola, Inc. Semiconductor die bonding with conductive adhesive
JP2507476B2 (ja) * 1987-09-28 1996-06-12 株式会社東芝 半導体集積回路装置
JPH01278754A (ja) * 1988-05-02 1989-11-09 Matsushita Electron Corp 半導体装置用リードフレーム
JPH02106943A (ja) * 1988-10-17 1990-04-19 Nec Corp 半導体集積回路の実装構造
US5123163A (en) * 1989-04-27 1992-06-23 Nec Corporation Process and apparatus for forming bumps on film carrier
JPH0316146A (ja) * 1989-06-14 1991-01-24 Sumitomo Bakelite Co Ltd 半導体装置
US5388577A (en) * 1990-06-08 1995-02-14 Boston University Electrode array microchip
JPH0465166A (ja) * 1990-07-05 1992-03-02 Fuji Xerox Co Ltd 半導体装置の製造方法
US5132772A (en) * 1991-05-31 1992-07-21 Motorola, Inc. Semiconductor device having tape automated bonding (TAB) leads which facilitate lead bonding
US5467864A (en) * 1992-05-14 1995-11-21 Carl Strutz & Co., Inc. Dual purpose apparatus to manipulate workpieces

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KR0141952B1 (ko) 1998-06-01
JP2602182B2 (ja) 1997-04-23
US5559372A (en) 1996-09-24
JPH08186225A (ja) 1996-07-16

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