KR880010492A - 리이드프레임을 갖춘 반도체장치 및 그 제조방법 - Google Patents

리이드프레임을 갖춘 반도체장치 및 그 제조방법 Download PDF

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KR880010492A
KR880010492A KR1019880001744A KR880001744A KR880010492A KR 880010492 A KR880010492 A KR 880010492A KR 1019880001744 A KR1019880001744 A KR 1019880001744A KR 880001744 A KR880001744 A KR 880001744A KR 880010492 A KR880010492 A KR 880010492A
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lead
outer lead
semiconductor device
frame
semiconductor chip
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KR1019880001744A
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KR910000018B1 (ko
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마사미치 신도
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아오이 죠이치
가부시키가이샤 도시바
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음

Description

리이드프레임을 갖춘 반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 리이드프레임 외관의 1실시예를 도시해 놓은 평면도.
제3도는 본 발명에 따른 리이드성형을 행한 제2도의 선 A-A′에 대한 단면도.
제4도는 본 발명의 다른 실시예를 도시해 놓은 평면도.

Claims (10)

  1. 반도체칩 탑재영역의 주위에 방사상으로 배설된 내부리이드부(4)와, 이 내부리이드(4)로부터 바깥쪽으로 연장된 외부리이드부(5), 상기 내부 및 외부리이드(4)(5)를 안정적으로 지지해주는 프레임(1)등이 갖추어 짐과 더불어 상기 외부리이드부(5)의 선단부가 각각 상기 반도체칩의 한 변에 대응된 단위로 상기 프레임(1)과는 분리된 위치에 연결되어져서 반도체장치에 사용되도록 되어진 리이드프레임.
  2. 제1항에 있어서, 반도체칩 탑재영역에 상기 프레임에 결합된 베드부가 형성되어진 것을 특징으로 하는 리이드프레임.
  3. 제1항 또는 제2항에 있어서, 외부리이드(5)의 중간지점에서 각 변마다 외부리이드(5)를 연결시켜 주는 덤브(dumb)가 설치되어져 있는 것을 특징으로 하는 리이드프레임.
  4. 상기 리이드프레임(1)과 상기 리이드프레임(1)의 중앙에 반도체칩이 탑재되며, 외부리이드가 노출되도록 해주는 방법으로 수지봉합된 반도체장치에 있어서, 외부리이드(5)의 중간부분이 내부회로에 접속되기 위한 모양으로 형성되어 있고, 그 내측부분 및 선단부분이 봉합용 수지내에 매입되어져 구성되어진 것을 특징으로 하는 반도체장치.
  5. 제4항에 있어서, 외부리이드(5)의 접합부가 윗쪽이 개방되어 거의 "U"자형으로 되어 있는 것을 특징으로 하는 반도체장치.
  6. 제4항에 있어서, 외부리이드(5)의 접합용부분에 상방향이 개방된 관통구가 갖추어진 있는 것을 특징으로 하는 반도체장치.
  7. 제4항에 있어서, 봉합수지(11) 표면이 외부리이드의 접합용부분의 내면과 일치되어 있는 것을 특징으로 하는 반도체장치.
  8. 반도체칩 탑재영역의 주위에 방사상으로 배설된 내부리이드부(4)와, 이 내부리이드부(4)로부터 바깥쪽으로 연장된 외부리이드부(5), 상기 내부 및 외부리이드(4)(5)를 안정적으로 지지해 주는 프레임(1)등이 갖추어진 반도체장치를 제조해 주는 제조방법에 있어서, 상기 외부리이드(5)의 선단부가 상기 반도체칩의 한변에 대응되는 단위로 상기 프레임(1)으로부터는 분리된 위치에서 연결되어진 리이드프레임에 있어서의 상기 외부리이드(5)를 소정형상으로 성형해주는 공정과, 상기 리이드프레임의 칩답재영역에 반도체칩을 탑재해 주는 공정, 내부리이드(4)와 반도체칩사이에 배선을 연결해 주는 와이어-본딩공정, 수지로 반도체장치를 봉합해 주는 수지봉합공정, 외부리이드(5) 선단부의 연결부를 절단해 주는 공정 등이 수행되도록 되어진 것을 특징으로 하는 반도체장치의 제조공정.
  9. 제8항에 있어서, 외부리이드(5) 선단부의 연결부(7)를 절단해 주는 공정이 프레스로 행해지도록 되어진 것을 특징으로 하는 반도체장치의 제조방법.
  10. 제8항에 있어서, 외부리이드(5)의 성형 공정이 금속평면으로부터 외부리이드를 찍어 내는 과정과 동시에 수행되어지는 것을 특징으로 하는 반도체장치의 제조방법.
    ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880001744A 1987-02-20 1988-02-19 리이드프레임을 갖춘 반도체장치 및 그 제조방법 KR910000018B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62-037316 1987-02-20
JP62-37316 1987-02-20
JP62037316A JPH0831556B2 (ja) 1987-02-20 1987-02-20 半導体装置用リードフレーム

Publications (2)

Publication Number Publication Date
KR880010492A true KR880010492A (ko) 1988-10-10
KR910000018B1 KR910000018B1 (ko) 1991-01-19

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KR1019880001744A KR910000018B1 (ko) 1987-02-20 1988-02-19 리이드프레임을 갖춘 반도체장치 및 그 제조방법

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EP (1) EP0279683A3 (ko)
JP (1) JPH0831556B2 (ko)
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2508516Y2 (ja) * 1990-01-11 1996-08-28 日本特殊陶業株式会社 集積回路用パッケ―ジ
DE19639025C2 (de) 1996-09-23 1999-10-28 Siemens Ag Chipmodul und Verfahren zur Herstellung eines Chipmoduls
CN107046110B (zh) * 2016-02-05 2023-10-10 泰科电子(上海)有限公司 用于电池模组的引线框架、引线框架组件及电池模组

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5521128A (en) * 1978-08-02 1980-02-15 Hitachi Ltd Lead frame used for semiconductor device and its assembling
US4477827A (en) * 1981-02-02 1984-10-16 Northern Telecom Limited Lead frame for leaded semiconductor chip carriers
JPS59227148A (ja) * 1983-06-07 1984-12-20 Dainippon Printing Co Ltd 集積回路用リ−ドフレ−ム

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EP0279683A2 (en) 1988-08-24
JPH0831556B2 (ja) 1996-03-27
KR910000018B1 (ko) 1991-01-19
EP0279683A3 (en) 1989-12-20
JPS63204751A (ja) 1988-08-24

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