TW301045B - - Google Patents

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Publication number
TW301045B
TW301045B TW081106880A TW81106880A TW301045B TW 301045 B TW301045 B TW 301045B TW 081106880 A TW081106880 A TW 081106880A TW 81106880 A TW81106880 A TW 81106880A TW 301045 B TW301045 B TW 301045B
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TW
Taiwan
Prior art keywords
package
lead
semiconductor
leads
chip
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TW081106880A
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English (en)
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Gold Star Electronics
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Publication of TW301045B publication Critical patent/TW301045B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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    • H01L23/495—Lead-frames or other flat leads
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

3QiQ45 Λ 6 Η 6 五、發明説明（） 發明背景 發明领域： 本發明係Μ於記憶積體電路封裝及其製逄方法，尤措 用於封裝I6百舄位元級以上之記憶積體電路之引線在属片 上型封裝及其製造方法。 先甫技術 經濟部中央櫺準局员工消仲合作杜印製 3 狀 *«. 第1国爲一舦記億積體電路（1C〉之封裝構逄的釗面阖 ，第2明爲第1阑之記憶ic之引線柩的平面圓。製逄此種 封裝構造時，先準请引線框，以便封裝由截貫轟固而得之 晶片。第1及2圖中之苻號I3表示引線柩。如第2阖所示 ，引線框I3具有：用於裝附由截嘗晶圓而成之半導體品片 11之墊板l3a，往封裝内部接通至晶片u之外數内引線13b ，往封裝外部接通至其他元件之多數外引線13〇，用於保 持引線框I3之形狀的一對互相隔開的側軌Ud，在兩側轨 l3d之間將内引緣ub及外引線支持成以均一間跟隔開 之墒柵條（dam bar)l3e，將錾板ua支撐於兩側轨13d間之 一對支持條ISf，以及多個鎖定孔138。 製成具有上述構造之引線框U後，利用片結法（die b°nding)將晶片U裝附於？丨線柩u之墊板i3a。接之，以 金屬線μ並利用線結法（wire b〇nding〉捋晶片^之合接餐 12電氣迷接至對應之内引線13b。合接餐12係形成在晶片 11之表面以供施行上述之線結合者。若是雙列i排式封裝 ’敌合接^•被形成爲兩排，若是單列式封裝，則形成爲一 (請先閲讀背而之注意事項洱媾寫本頁) 裝- 訂_ 3 . Λ 6 ΙΪ6 經濟部屮央櫺準局员工消f合作社印製 五、發明説明（） 排。明示者，即屬於雙列並排式封裝。 施行片結及緣結後之引線框U被置入棋；1_5内，此棋I5 具有配合期望封裝成品形狀之棋腔。然後將環氧樹脂造棋 刻（EMC)l6裝入棋I5之棋腔内，以對半導體磊片玎及内引線 1讣施加棋製。 棋製後之封裝接受修剪處理，以去除蟎栅條Ue。接 之，施行成形處理，以將外引線Uc成形爲期望之形狀。 如此即褽成具有第1固所示構造之記憶IC封裝。 然而’近年来半導體元件製逄技術之發展導致記憶1(3 之容量有増大趄#，此趄棼亦使得半導體封裝内所含之裸 •ft片之尺寸增大。結果，在簦個半導體封裝面猜中裸品片 所佔之面積罢増加傾向，導致封裝之線厚度増大。 此種記憶1C封裝全面積内裸晶片所佔面積之増加，使 得在封裝内無法留彀爲確保引線框精確佈置所需之空間。 爲解決此問趙，巳知有一種在引線柩被栽置於晶片上之狀 態下族•行封裝之引線在晶片上（LOC)封裝扶術。 此種LOC封裝技術會被美國IBM公司採用以製造1百萬 位元随機存取記憶器（1M DRAMS〉，然後在日本日立公司， 以製造AM DRAMS。此L0C封裝技術將成爲用於製造1όΜ DRAM之新封裝技術。 第3圏爲習知loc封裝結構之刳面明。如第3圏所示 ，此L〇C封裝具有：一半導體晶片裝附於引線框之鮝板 34a並在晶片31之上表面之中央部設有單排之多個合接墊 ;一絶緣膜33形成在半導《品；之除與合接鲞Μ對應之 -4 - (請先閲讀背而之注意事項#填寫本頁)
本紙ft尺度逍用中a B家橒毕(CNS) T4規格(210x297公*) 表面部外之上表面亦即半導體晶片叮之上表面之兩側部； 多個内引線34b各個被延伸成其一埃位里於裝附在引線柩 之錾板34a的半導體晶片31之上表面上，各内引線均以金 屬線35電氣違接於對應之各合接錾32 ;多個外引緣34(；各 個被延伸自對應之各内引線3Ab之另一鳩並且形狀， 各外引線電氣逹接於外部其他元件；以及一封裝本禮36包 園著半導體義片31，絶緣膿33和内引線34b。 第4固燴出第3国之贺用LOC封裝所用引緣框之構造 。類似第2阖之構造，第4 «之引線框亦具有錾板34a , 多個内引緣34b，多個外引線3々c，一對側执34d，碟播條 34e，支持條SAf及鎖定孔3蛇0但是其各内引緣具有足 夠長度使得其一端能位置於欲裝附在錾板Ma上面之半導 體晷片31之上表面。 接著’説明具有上述構造之LOC封裝的製造方法。 首先，製餚具有第4明所示構造之引線框μ。然後將 預先由截首晶圓而成之半導體晶片31利用片結法裝附於引 線框34之墊板34a。然後捋預定厚度之聚醯胺層被復於半 導體晶片31之上表面之兩側部，以作爲絶緣膜33 〇然後利 用線結法以金屬線35將内引線34b電氣迷接於晶片is之种 應合接餐。 線結後，以猿氣樹腊造棋剞棋製包括晶片U，絶緣膿 33及内引線34b在内之預定部份。詳言之，將裝栽有属片 31之引線框34置於棋（未繪出）内。此時，引線框％之外引 緣34c伸出於棋外。然後將獴氧樹脂造棋劑填入棋之空腔 Λ 6 η 6 五、發明説明（） 内，如此即可將該預定部份棋製成爲封裝本體36。 (請先閲讀背而之.江意事項#璘筠本黃) 接之施加修首，去除蟎栅條34d及支持條34f。然後施 行成形步秘，以將外引線34c寄曲成J形狀。如此叮獲得 早列式LOC封裝。 依照此種LOC封裝，引緣框34之内引綠34b延伸至半導 種晶片31之活性品胞並以金屬線35建接於半導體義片31， 從而具有增加内引線34b在封裝内所佔面積之優黠。 但是，此種变式之LOC封裝需使用聚合物做爲不導電 衬料以達成半導體A片31與内缘34b之間之絶緣。此聚 合物之使用導致一個問題，即滅低聚合物與引綠框34間之 結合力及？丨線框34與瓖氣樹脂造棋則製封裝本體36間之結 合力。另一問題是，在各內引線34b與配置在内引綵34b下 方之半導體晶片31之電路之間容易發生不受歡迎的寄生電 容。 此種由線結合引起在半導體晶片U與伸至晶月31上表 面之各内引線34b間發生之寄生電容，可藉由將聚合物層 増厚以使晶片31與各内5丨線3处間完全絶緣之方式加以防 止。但是聚合物層増厚會導致記憶1C封裝之縝厍度増加， 其結果’無法產製層疊封裝。 經濟部中央標準局負工消赀合作社印製 發明之概述 因此’本發明之目的在於解決先前技術之上述問題， 益提供一種LOC封裝，其不僅可在絶緣膿減薄下防止寄生 電容増加’亦可増加絶緣膿與引緣框間及絶緣膿環氧樹脂 -6 - 本紙張尺度遑用中《困家標準(CNS) T4規格(210x297公*) 經濟部中央楳準局員工消费合作社印製 A 6 _______Π6_ 五、發明説明（） 造棋則製封裝本體間之結合力，同時亦提供上述LOC封裝 之製造方法。 依本發明之一特點，乃提供引線在晶片上之封裝，其 具有••半導體Λ片，其上表面中央部配置有單排之多個合 接巻*’並在該上表面之兩側部形成有多個微小突起；絶緣 胰，形成在半導體晶片之上表面的兩倒部上，此絶緣膜之 上下兩表面均敌有滾紋面；多個内引線，分別直結於半導 體晶月之對應各合接鮝件與該磊片電氣連接，各内引線之 上下兩表面均設有滾紋面；封裝本體，包園著半導體晶片 ，絶緣胰及内引線；以及多個外5丨線，分别自對應之各內 引線延伸而連接於封裝本體外之外部元件。 本發明之另一特點，乃提供引線在晶片上之封裝的製 法’其包括下列步驟：製備含有蚕板，多個内引緣，分別 自對應各内引線伸出之多個外引線的5丨線框；將半導ft甚 片結合於引緣框之塾板，該半導體晶月在其上表面之中央 部具有單排之多個合接鍪；形成多個微小突起於半導體品 之上表面之除對應於合接錾之部佾以外的兩側部；形成 絶緣膜於詨有該突起之半導體品片上表面，該絶緣胰在其 上下兩表面均具有滚紋面；形成滾紋面於各内引線並使各 内引線之其中一滾紋面與絶緣膜之其中一滚紋面接觭；在 半導《晶片之各合接錾形成軟垾體；將各內引線之一端軟 垾接於對應之該軟垾《，使内引線電氣迷接於半導體晶片 ，將各内引線之另一端軟焊接於各外引線之一端，使内、 外引綵互相迷接；棋製包含半導體晶片，絶緣膜及内引綵 (請先閲讀背而之注意事項再项寫本頁) 裝· 訂· 線. 本紙张尺度遑用中《國家楳準(CNS)T4規格(210x297公釐) Λ 6 Π 6 經濟部中央標準局员工消费合作社印製 五、發明説明（） 在内之預定部份，以形成封裝本體；以及修嘗及造型核封 裝本11。 阈式之簡單説明 茲參照下列之囷式詳細説明本發明之上述及其他目的 ，特點及功效： 第1圏爲一舦記憶1C之封裝結構之釗视圖； 第2阑爲第1圏之記憶ic封裝所用之引線框之平面固 9 第3圏爲皙知LOC封裝之剖视圏； 第4明爲第3圖之習知LOC封裝所用之引線框之平面 圖； 第5圖爲本發明之第1實施例L0C封裝之釗视_ ; 第6 A圈至6 C阖爲與第5阑中之"A"部份對應之封 裝一部份的放大圖，分别顒示半導體品片與内引線之接通 法的不同例子； 第7明爲本發明的第1實施例之LOC封裝所用之引線 框之平面明； 第8圖爲描獪本發明LOC封裝製法中之軟烊遇桎的平 面阑； 第9明爲本發明第2實施例LOC封裝的剖视阖。 實施例之説明 第5圖顯示本發明之第1實施例LOC封裝。 -8 - 本紙》•尺度遑用中B困家樣準(CNS) TM規格(210x297公；¢) (請先閲讀背而之注意事項再塡寫本頁) 裝- 訂- 線. 〇GiC^5 經 濟 部 屮 央 標 準 局 工 消 合 作 杜 印 製 Λ 6 B6 五、發明説明（) 如第5 «所示，L0C封裝具有半導體磊片^，此磊片 si在其上表面中央部彀有單排之多個合接鲞52 〇絶緣膜53 被形成在半導體晶片51之上表面之除與合接签52對應之部 份以外的部份，亦即形成在半導體晶月51之兩惻部上面。 此LOC封裝亦具有含有鲞板SAa，多個内引線541}及多個外 $1線54c之引線框54。半導體義片^之合接签52在其上表 面設有軟烊II55。引緣框54之各内引線Mb炎伸至半導種 晶片51之上表面，使得其一端位置於半導饉品片S1之上表 面上並且藉詨在對應各合接錾52之軟烊體55而電氣連接於 半導《晶片S1。使用樣氡樹腊造棋則棋製之封裝本體56包 固著半導體晶片51，引緣框54之內引線54b以及絶緣膿S3 Ο 依本發明’在半導體聶片51之上表面兩側部敌有多個 撤小突起57。另一方面，在絶緣膜53之上下兩面形成滚紋 面。同樣地，各内引線54b之上下兩面亦形成滾紋面。 依本發明’用來使半導體晶片si與内引緣54b之間絶 緣之絶緣胰53，使用比電容黃2.0至2·2之氟化L螓腆，不 同於一般所使用比電容量3.5之聚鱸胺膿。由於氟化匕味 膜之比當容量較低，可減少约44%之厚度，而不致増加在 半導體晶月51與内5丨線54b之間發生之寄生電容。亦即， 爲防止寄生電容發生，習用封裝之絶緣用聚鵷胺膿之厚度 爲大約100wm，而依本發明之L0C封裝之絶緣用氟化已雉 脒之厚度爲约6〇//ιη至約παπί，小於轅聚班胺膜厚度。 雖然上述氟化螓膿有藉著其低比電容量而減少絶緣 (請先閲讀背而之注意事項再填寫本頁) 裝· 線. Λ 6 Π 6 經濟部中央標準局ΚΧ工消#合作社印製 五、發明説明（） 膜53厚度之優點，但其附著性非常低。依本發明，此缺失 吁接在絶緣胰53之上下兩面及内引緣SAb之上下兩面形成 滾紋面之方式加以解決之。這些滾紋面可改善半導饉晶片 51與各内引線54b間及各内引線Mb與濛氧樹腊造棋劑製之 封裝本體56間之附著力。在各内引綠54b形成多個均勻瞞 閉之邋孔並以蛾氧樹脂棋製有邋孔之各内引線時，可増加 上迷零件間之接觭面積。 接下來，參照第5圖至8圖説明具有上述構造之loc 封裝之製法。 依本發明製法，先製请具有第7明所示構逄之引線框 54。此引線框54具有多個内引線54b，並與第4明之智用 LOC封裝之引緣框一樣，各内引緣5々b長狀延伸使得其一端 位置於半導體義片51之上表面上。佴是LOC用引線框54之 各内引線54b之與對應半導體si之各合接鍪52迷結之部份 的寬度小於與對應各外引線54〇連結之部份的寬度。 表示蟻栅條，Me表示側轨，Mf爲支持條，5竓爲 鎖定孔。 引緣框54製備後，利用片結法將半導體轟月S1裝附於 引線框54之鲞板54a。 然後，在载有單排之多個合接螯52之半導馥轟片^之 上表面形成多個撖小突起57。此#小突起57之形成方式爲 將一層Si3N4或Si〇2沉猜於半導體品片S1之上表面之兩倒 部上，但排除形成有合接錾52之部份，沉積時使用低温下 之射頻絨鍍法，以形成约4〇〇A至5〇〇A之厚度。 -10 - 本紙張尺度遑用中國Β家榫準(CNS)T4規格(210X297公;¢) (請先閲讀背而之注意事項再塡寫本頁) 裝- _ 線- 3Q1C45 A 6 Π 6 經濟部屮央標準局貝工消费合作杜印製 五、發明説明（） 在具有橄小突起57之半導體蟲片51之上表面兩倒部上 被復由具有滚紋面之氟化G烯胰構成之絶緣胰53。接之在 各内引線SAb之上下兩面形成滾紋面，妓使其中之一面接 觸於絶緣膿53之對應滾紋面。 在引綵框54之内引綠54b形成滾欽面之方法，可採用 令内引線Mbii遍分別具有滾紋面之兩輥輪間，或利用 lOOmA/cm2以上之高電流密度之當鍍法鍍後一結節狀層或 樹枝狀層於内引綵5々b之上表面。 纗形成滾紋面於内引線54b夜，將軟垾體55塗後於半 導體晶片51之各合接鍪52上。接之，施行軟垾步驊，利用 對應之各軟焊《55將引綠框54之各内引線54b軟焊接於對 應之合接墊*52，使各内引線54bt氟連接於半導《晶片51 〇 如第8固所示，引線框54之各内引緣54b之連接於半 導體晶；151之對應各合接塾52之部佾的寬度小於違接於對 應各外引缘之部份。依照此構造，軟烊後之內引緣54b 係交鉼配置於軟焊體55上，藉此被電氟迷接於半導體晶片 51。依照此彀計，可有效峰低封裝之螝厚度。 半導體晶片51與内51線間之電氟連接，亦可使用 一般金屬線58利用線結法達成，如第6 A阖所示。不逷爲 減少封裝總厚度起見，可利用如第6 B或6 C固所示之帶 自動結合法（taPe aut〇-b〇nding method〉或C-4結合法’ 將內引線54b直接連結於合接螌·52。 然後，用環氡樹腊造棋剤將包含半導體Α片51及内引 -11 - (請先間請背而之注意事項再堝寫本頁) 裝- 訂· 線- 本紙51尺度遑用中a «家«準(CNS) T4規格(210X297公;《:) A 6 Π 6 部 屮 央 準 工 消 合 作 社 印 製 五、發明説明（） 線54b之封裝預定部份予以棋製成封裝本體56。接之對此 封裝施行修膂及造垄步驟。如此即可獲得單緣排列魂LOC 封裝。 第9固表示本發明第2實施例之LOC封裝構造。 此LOC封裝除了引線框之内引線54b與對應之外引線 爲分開形成之彀計外，其他構造均與第5圖所示之LOC 封裝相同。於此實施例之場合，内引線S4b係用軟烊結合 於對應之外引線54c。 由上述T明繚，本發明係在用於絶緣半導片與5| 線框之内5丨線之間的聚合物膿，使用具有低比電容量之氟 化G烯胰，如與習知技術使用高比電容量之聚雄胺膜者相 比，能減少聚合物膿之厚度。依本發明，不僅在聚合物胰 之上下兩結合面以及引線框之内引線之上下兩結合面形成 有滾紋面，亦在半導體晶片之上結合面形成有多個微小突 起，因此可消除聚合物腆使用氟化L烯時在結合此聚合物 腺與内引線時所發生之問題。同時亦可減少聚合物旗之厍 度而防止寄生電容増加。聚合物膿厚度減少之結果，有助 益於封裝之層綦的效果。 爲方便説明本發明，上文僅就较佳货施例加以插述， 但在如後文之申請專利範因所記载之範疇下尚有其他種種 變更、附加、昝代。 中家樣毕(CNS) 規格(210x297公釐) (請先閲讀背而之注意事項再项寫本頁) 裝- 訂- -12

Claims (1)

  1. 修正 (八十五年十月修正） 1. 一種引線在晶片上之封裝，包括： 半導體晶片，此品片之上表面中央部配置有單神之 多個合接餐，並在拔上表面之兩側郤形成有多個微小突起 絶緣腆，形成在半導體晶片之上表面之兩側部上， 此絶緣胰之上下兩面設有滚紋面； 多個内引線’分別違結於半導體晶片之對應各合接 墊、俾與半導體晶片電氣連接，各内引線之上下兩面均具 有滾紋面； 封裝本體，包因著半導體晶片，絶緣胰及内引綵； 以及 多個外引線，分别自對應之各内引線楚伸而逑接於 封裝本體外之外部元件。 2·如申請專利範圍第1項之封裝，其中絶緣胰爲氟化 G烯胰。 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 狄年卜月 申請專 3. 如申請專利範園第1項之封裝，其中絶緣膜之厚度 爲60 a m至70以m 〇 4. 如申請專利範園第1項之封裝，其中封裝本體係由 環氧樹腊造棋刑所製0 -13 ABCD 301C4S 六、申請專利範圍 5·—種f丨線在晶片上之封裝的製造方法，包括下列步 驟： 褽锖含有錾板，多個内引線及分別自對應各內引線 伸出之多個外引線之引線框； 片結合半導體晶片於引線框之鮝板，此半導體晶片 在其上表面中央部具有單排之多個合接餐； 形成多個橄小突起於半導體晶片之上表面之除對應 於合接塾之部份以外的兩側部； 形成絶緣膜於具有橄小突起之半導《晶片上表面， 此絶緣膜之上下兩面具有滾紋面； 形成滾紋面於各内引線，並使各内引線之其中一滾 紋面與絶緣膜之其中一滾紋面接觸； 形成軟垾體於半導體晶片之各合接錾上； 軟焊各内引緣之一端於對應之各軟焊骰，使内引線 電氣連接於半導體晶片； 棋製含有半導體晶片，絶緣膜及内5丨線在内之預定 部份，以形成封裝本體；及 修首並成型該封裝本體。 如申請專利範園第5項之封裝的製造方法，其中形 成多個微小突起之步邾係在低溫下使用射頻減鍍方法達成 7·如申請專利範困第6項之封裝的褽造方法，其中撖 -14 - 本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨Ο X 2W公釐） (請先聞讀背面之注意事項再填寫本頁) ί 訂 經濟部中央樣準局負工消费合作社印策 申請專利範園 ABCD 小突起係由Si3N4或SiO製成。 8. 如申請專利範固第7項之封裝的髮遑方法，其中橄 小突起之厚度爲400$至5〇〇文。 9. 如申請專利範固第7項之封裝的踅逄方法，其中引 線框之構造爲各内引線之違接於半導骰晶片之對應各合接 墊之部份之寬度小於連接於對應外引綠之部份，俾使内引 線以交錯方式迷接於對應之合接鲞。 10.如申請專利範面第7項之封裝的製造方法，其中在 各内引線形成滾紋面之步驟係使用具有滾紋外周面之辊達 成。 (請先閲讀背面之注意事項再填寫本萸) 訂 經濟部_央標準局負工消費合作社印製 11.如申請專利範園第7項之封裝的製造方法，其中在 内引線形成滾紋面之步驟係使用高電流密度之電镀法或塗 復結節狀或樹枝狀層於各内引線表面上而達成。 I2·—種引線在晶片上之封裝，包括： 半導體晶片，此晶片之上表面中央部配置有單排之 多個合接墊，並在該上表面之兩側部形成多個微小突起； 絶緣膜，形成在半導體晶片之上面之兩側部上，此 絶緣胰之上下兩面設有滾紋面； 多個内引緣，分別直結於半導體晶；ί之對應各合接 -15 - 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） A8 B8 C8 一·· 六、申請專利範圍 "〜' ' --- 餐俾與該接’各㈣線<上下兩面均具有滾紋 面； 封裝本II，包目著半導㈣片，絶緣旗及0線； 以及 多個外5丨線’各自與對應之内引線㈣形成而連接 於封裝本體外之外部元件0 13. 如申請專利範園第I2項之封裝，其中各外引線係以 軟烊連接於對應之各内引線。 14. 一種引線在晶片上之封裝的製造方法包括下列步 m ： 製僑含有墊板，多個內引線及與對應各内5丨線分開 之多個外引線之引線框； 片結合半導艘晶片於引線框之塾板，此半導親品片在 其上表面中央部具有單排之多個合接錾： 形成多個橄小突起於半導體晶片之上表面之除對應於 合接錾之部份以外的兩側部； 經濟部中央標準局貝工消費合作社印製 形成絶緣膜於具有橄小突起之半導《晶片上表面，此 絶緣膜之上下兩面具有滚紋面； 形成滾紋面於各内引線’並使各内引線之其中一滚紋 面與絶緣膜之其中一滾紋面接觸； 形成軟焊體於半導體晶片之各合接墊上； 軟垾各内引線之一端於對應之各軟焊《，使内5丨線電 -16 - 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） S01045 A8 B8 C8 D8 々、申請專利範圍 氣迷接於半導體晶片； 軟垾各内引緣之另一端於各外引線之一端，使内外引 線互相連接； 棋製含有半導雅晶片，絶緣胰及内引線在内之預定部 份，以形成封裝本體；及 修赁並成型該封裝本體。 (請先閱讀背面之注意事項再填寫本頁. ) 、-° 經濟部中央標準局員工消費合作社印製 -17 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）
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Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0152901B1 (ko) * 1993-06-23 1998-10-01 문정환 플라스틱 반도체 패키지 및 그 제조방법
TW270213B (zh) * 1993-12-08 1996-02-11 Matsushita Electric Ind Co Ltd
KR970002140B1 (ko) * 1993-12-27 1997-02-24 엘지반도체 주식회사 반도체 소자, 패키지 방법, 및 리드테이프
US5554569A (en) * 1994-06-06 1996-09-10 Motorola, Inc. Method and apparatus for improving interfacial adhesion between a polymer and a metal
US5559366A (en) * 1994-08-04 1996-09-24 Micron Technology, Inc. Lead finger tread for a semiconductor lead package system
US5808354A (en) * 1994-11-21 1998-09-15 Samsung Electronics Co., Ltd. Lead frame for a semiconductor device comprising inner leads having a locking means for preventing the movement of molding compound against the inner lead surface
JP3205235B2 (ja) * 1995-01-19 2001-09-04 シャープ株式会社 リードフレーム、樹脂封止型半導体装置、その製造方法及び該製造方法で用いる半導体装置製造用金型
US5796158A (en) * 1995-07-31 1998-08-18 Micron Technology, Inc. Lead frame coining for semiconductor devices
US5785535A (en) * 1996-01-17 1998-07-28 International Business Machines Corporation Computer system with surface mount socket
JP3558459B2 (ja) * 1996-02-08 2004-08-25 沖電気工業株式会社 インナーリード接続方法
US6384333B1 (en) 1996-05-21 2002-05-07 Micron Technology, Inc. Underfill coating for LOC package
US5733800A (en) 1996-05-21 1998-03-31 Micron Technology, Inc. Underfill coating for LOC package
JP3261987B2 (ja) * 1996-07-24 2002-03-04 日立電線株式会社 Ｌｏｃ用リードフレームおよびそれを利用した半導体装置
JPH10199911A (ja) * 1996-11-14 1998-07-31 Nittetsu Semiconductor Kk 半導体装置及びその製造方法
JPH10163400A (ja) * 1996-11-28 1998-06-19 Nitto Denko Corp 半導体装置及びそれに用いる２層リードフレーム
US6692989B2 (en) * 1999-10-20 2004-02-17 Renesas Technology Corporation Plastic molded type semiconductor device and fabrication process thereof
US6291273B1 (en) * 1996-12-26 2001-09-18 Hitachi, Ltd. Plastic molded type semiconductor device and fabrication process thereof
DE19704351B4 (de) * 1997-02-05 2006-03-30 Infineon Technologies Ag Leiterrahmen und Montagevorbereitungsverfahren für einen Leiterrahmen
CA2232843C (en) * 1997-03-25 2002-03-12 Koichi Haruta Plastic package, semiconductor device, and method of manufacturing plastic package
KR100230515B1 (ko) * 1997-04-04 1999-11-15 윤종용 요철이 형성된 리드 프레임의 제조방법
US6117797A (en) 1998-09-03 2000-09-12 Micron Technology, Inc. Attachment method for heat sinks and devices involving removal of misplaced encapsulant
US6949822B2 (en) * 2000-03-17 2005-09-27 International Rectifier Corporation Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance
JP2002176130A (ja) 2000-12-08 2002-06-21 Mitsubishi Electric Corp 封止型半導体装置およびそれに用いられるリードフレーム
US7264456B2 (en) * 2001-10-10 2007-09-04 Micron Technology, Inc. Leadframe and method for reducing mold compound adhesion problems
JP2003204027A (ja) * 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法
JP3981089B2 (ja) * 2004-02-18 2007-09-26 株式会社東芝 半導体装置とその製造方法
US20070290303A1 (en) * 2006-06-07 2007-12-20 Texas Instruments Deutschland Gmbh Dual leadframe semiconductor device package
CN102047404B (zh) * 2008-12-16 2013-07-10 松下电器产业株式会社 半导体装置和倒装芯片安装方法及倒装芯片安装装置
US8643159B2 (en) 2012-04-09 2014-02-04 Freescale Semiconductor, Inc. Lead frame with grooved lead finger
US9978669B2 (en) * 2016-06-30 2018-05-22 Nxp Usa, Inc. Packaged semiconductor device having a lead frame and inner and outer leads and method for forming

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4003073A (en) * 1970-06-29 1977-01-11 Motorola, Inc. Integrated circuit device employing metal frame means with preformed conductor means
JPS52124865A (en) * 1976-04-13 1977-10-20 Sharp Corp Semiconductor device
JPS55140238A (en) * 1979-04-20 1980-11-01 Hitachi Ltd Tape carrier type semiconductor device
DE2929939A1 (de) * 1979-07-24 1981-02-19 Licentia Gmbh Halbleiteranordnung und verfahren zu ihrer herstellung
US5126820A (en) * 1985-02-01 1992-06-30 Advanced Micro Devices, Inc. Thermal expansion compensated metal lead frame for integrated circuit package
US4774635A (en) * 1986-05-27 1988-09-27 American Telephone And Telegraph Company At&T Bell Laboratories Semiconductor package with high density I/O lead connection
KR910006967B1 (ko) * 1987-11-18 1991-09-14 가시오 게이상기 가부시기가이샤 반도체 장치의 범프 전극 구조 및 그 형성 방법
JP2706077B2 (ja) * 1988-02-12 1998-01-28 株式会社日立製作所 樹脂封止型半導体装置及びその製造方法
GB2215125B (en) * 1988-02-22 1991-04-24 Mitsubishi Electric Corp Semiconductor device
JPH0727764B2 (ja) * 1988-03-16 1995-03-29 株式会社日立製作所 マイクロ波イオン源
JPH02113544A (ja) * 1988-10-21 1990-04-25 Mitsubishi Electric Corp キャリアテープ
US4916519A (en) * 1989-05-30 1990-04-10 International Business Machines Corporation Semiconductor package
US5175060A (en) * 1989-07-01 1992-12-29 Ibiden Co., Ltd. Leadframe semiconductor-mounting substrate having a roughened adhesive conductor circuit substrate and method of producing the same
US5278429A (en) * 1989-12-19 1994-01-11 Fujitsu Limited Semiconductor device having improved adhesive structure and method of producing same
US5164815A (en) * 1989-12-22 1992-11-17 Texas Instruments Incorporated Integrated circuit device and method to prevent cracking during surface mount
JPH03241826A (ja) * 1990-02-20 1991-10-29 Mitsubishi Materials Corp 半導体素子の製造方法およびこれに用いられる半導体基板
JPH03280532A (ja) * 1990-03-29 1991-12-11 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH0456239A (ja) * 1990-06-25 1992-02-24 Matsushita Electron Corp 半導体装置
NL9001491A (nl) * 1990-06-29 1992-01-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, en inrichting voor toepassing van de werkwijze.
DE4030771B4 (de) * 1990-09-28 2005-09-08 Infineon Technologies Ag Halbleiterbauelement mit einem in einem Kunststoffgehäuse eingebetteten Halbleiterchip
JPH04165624A (ja) * 1990-10-30 1992-06-11 Fujitsu Ltd 絶縁膜上のめっき配線方法
US5146312A (en) * 1991-02-28 1992-09-08 Lim Thiam B Insulated lead frame for semiconductor packaged devices
US5086018A (en) * 1991-05-02 1992-02-04 International Business Machines Corporation Method of making a planarized thin film covered wire bonded semiconductor package

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JP3121450B2 (ja) 2000-12-25
JPH06169052A (ja) 1994-06-14
KR930006867A (ko) 1993-04-22
US5358906A (en) 1994-10-25
DE4230187A1 (de) 1993-03-18
KR940006083B1 (ko) 1994-07-06
US5742096A (en) 1998-04-21
DE4230187B4 (de) 2007-02-01

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