CN100559577C - 具有阵列接垫的晶片封装构造及其制造方法 - Google Patents
具有阵列接垫的晶片封装构造及其制造方法 Download PDFInfo
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Abstract
本发明是有关于一种具有阵列接垫的晶片封装构造及其制造方法。该晶片封装构造,主要包含复数个打线接垫、一晶片、复数个焊线以及一封胶体。该些打线接垫的电铸核心的上下各形成有一上接合层与一下接合层,其中该电铸核心的材质包含铜。该些焊线是电性连接该晶片至该些打线接垫的上接合层。该封胶体是密封该些焊线、该些电铸核心与该些上接合层,其中在该些打线接垫中仅有该些下接合层是显露在该封胶体之外。本发明可以解决以往导线架基底无外接脚式晶片封装构造中引脚外露切割面生锈的问题,并具有阵列接垫,能达到高密度的晶片封装。本发明的制造方法在封装制程中持续使用一刚性导电模板进行电铸、粘晶、打线与封装步骤,可达到封装作业的一贯性。
Description
技术领域
本发明涉及一种半导体晶片的封装构造,特别是涉及一种可解决以往导线架基底无外接脚式晶片封装构造中引脚外露切割面生锈问题,并具有阵列接垫,能达到高密度的晶片封装,以及在封装制程中持续使用一刚性导电模板进行电铸、粘晶、打线与封装步骤,可达到封装作业一贯性的无外接脚式具有阵列接垫的晶片封装构造及其制造方法。
背景技术
在现有已知的封装技术中,一种导线架基底晶片封装构造是为无外接脚式。其是导线架中引脚的下表面对外表面接合,取代现有习知的导线架的外引脚,具有表面覆盖区(footprint)更小的优点。通常导线架的基础层材料是包含有铜(Cu),以利蚀刻成形。虽然具有导热佳、导电性佳与低制造成本的优势,但铜本身容易在大气与高温环境中生锈,终会影响晶片封装构造的产品可靠性。
请参阅图1及图2所示,图1是一种现有习知的无接脚式晶片封装构造的截面示意图,图2是现有习知的晶片封装构造的顶面透视图。现有习知的无外接脚式晶片封装构造100,包含一具有引脚111的导线架、一晶片120、复数个焊线130以及一封胶体140。习知的导线架的引脚111的基础层是为铜,并在封装前一体连接至该导线架的框条(图未绘出)。该导线架可另具有一晶片承座112。该晶片120是粘固于该晶片承座112上。以打线形成的该些焊线130是电性连接该晶片120的复数个焊垫121至该些引脚111的上表面113。而该封胶体140是密封该晶片120与该些焊线130并固着该些引脚111。该些引脚111的下表面114可外露于该封胶体140之外,并藉由该导线架的框条导通,以在该些下表面114电镀上一电镀层115。当该封胶体140与该电镀层115皆形成之后,方进行一单体化切割(singulation)的步骤。
如图1所示,该些引脚111会在该封胶体140的侧面形成露铜的引脚外露表面116。该些外露表面116依现有制程无法被该电镀层115所覆盖保护,故容易由该些外露表面116开始生锈,而影响产品的可靠性。此外,该些引脚111的外露表面116亦会造成高频讯号的干扰,形成天线效应。再者,如图2所示,由于该些引脚111的每一外端皆须延伸至该封胶体140的侧边,该些引脚的排列方式只能是单排或是多排的交错排列,而无法进一步达到高密度的晶片封装。
由此可见,上述现有的晶片封装构造及其制造方法在产品结构、制造方法与使用上,显然仍存在有不便与缺陷,而亟待加以进一步改进。为了解决上述存在的问题,相关厂商莫不费尽心思来谋求解决之道,但长久以来一直未见适用的设计被发展完成,而一般产品及方法又没有适切的结构及方法能够解决上述问题,此显然是相关业者急欲解决的问题。因此如何能创设一种新的具有阵列接垫的晶片封装构造及其制造方法,实属当前重要研发课题之一,亦成为当前业界极需改进的目标。
有鉴于上述现有的晶片封装构造及其制造方法存在的缺陷,本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识,并配合学理的运用,积极加以研究创新,以期创设一种新的具有阵列接垫的晶片封装构造及其制造方法,能够改进一般现有的晶片封装构造及其制造方法,使其更具有实用性。经过不断的研究、设计,并经反复试作样品及改进后,终于创设出确具实用价值的本发明。
发明内容
本发明的主要目的在于,克服现有的晶片封装构造及其制造方法存在的缺陷,而提供一种新的具有阵列接垫的晶片封装构造及其制造方法,所要解决的技术问题是使其利用电铸形成的打线接垫,而具有防止电铸核心生锈的功效以提升产品的可靠性,并能避免现有习知导线架的引脚的天线效应。此外,打线接垫的阵列形成还能够达到高密度的晶片封装,从而更加适于实用。
本发明的次一目的在于,提供一种新的具有阵列接垫的晶片封装构造及其制造方法,所要解决的技术问题是使其可以避免显露在封胶体底面的下接合层被刮伤或磨损,并且兼具有增进的防锈功效,从而更加适于实用。
本发明的另一目的在于,克服现有的晶片封装构造的制造方法存在的缺陷,而提供一种新的具有阵列接垫的晶片封装构造的制造方法,所要解决的技术问题是使其在封装制程中持续使用一刚性导电模板进行电铸、粘晶、打线与封装的步骤,不需要中途更换载具,而可以达到封装作业的一贯性,非常适于产业应用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种具有阵列接垫的晶片封装构造,其包含:复数个打线接垫与复数个承载接垫,其是阵列形成在同一平面,每一打线接垫与承载接垫包含有一下接合层、一电铸核心与一上接合层,其中该电铸核心的材质是包含铜;一晶片,其具有复数个电极,该晶片的背面仅固着于该些承载接垫上;复数个焊线,其电性连接该些电极与该些打线接垫的上接合层;以及一封胶体,其是结合该晶片与该些打线接垫为一体并密封该些焊线、该些电铸核心与该些上接合层,其中在该些打线接垫中仅有该些下接合层是显露在该封胶体之外。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的具有阵列接垫的晶片封装构造,其中所述的该些下接合层是选自于镍-金层、镍-钯-金层、锡层与锡铅共晶层的其中之一。
前述的具有阵列接垫的晶片封装构造,其中所述的该些上接合层是选自于镍-金层、镍-钯-金层与银层的其中之一。
前述的具有阵列接垫的晶片封装构造,其中所述的该些下接合层是与该封胶体的底面为共平面。
前述的具有阵列接垫的晶片封装构造,其中所述的该些承载接垫与该些打线接垫等尺寸并为棋盘排列。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种晶片封装构造的制造方法,其包括以下步骤:提供一刚性导电模板;形成一电铸遮罩于该导电模板上,并使其图案化;依该电铸遮罩的开孔图案,电铸形成设有复数个打线接垫与复数个承载接垫于该导电模板上,该些打线接垫与该些承载接垫是阵列形成在同一平面,每一打线接垫与承载接垫包含有一下接合层、一电铸核心与一上接合层,其中该电铸核心的材质是包含铜;设置至少一晶片于该导电模板上,该晶片的背面仅固着于该些承载接垫上;形成复数个焊线,其是电性连接该些电极与该些打线接垫的上接合层;形成一封胶体于该导电模板上,该封胶体是结合该晶片与该些打线接垫为一体并密封该些焊线、该些电铸核心与该些上接合层;以及在该封胶体形成之后,剥离该导电模板,可使在该些打线接垫中仅有该些下接合层是显露在该封胶体之外。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的晶片封装构造的制造方法,其中所述的该些承载接垫与该些打线接垫等尺寸并为棋盘排列。
本发明与现有技术相比具有明显的优点和有益效果。由以上可知,为了达到上述目的,本发明提供了一种晶片封装构造,主要包含有复数个打线接垫、一晶片、复数个焊线以及一封胶体。该些打线接垫是阵列形成在同一平面,每一打线接垫包含有一下接合层、一电铸核心与一上接合层,其中该电铸核心的材质是包含铜。该晶片具有复数个电极。该些焊线是电性连接该些电极与该些打线接垫的上接合层。该封胶体是结合该晶片与该些打线接垫为一体并密封该些焊线、该些电铸核心与该些上接合层,其中在该些打线接垫中仅有该些下接合层是显露在该封胶体之外。此外,本发明另揭示了一种该晶片封装构造的制造方法。
前述的晶片封装构造,其中另包含有一晶片承座,以供固着该晶片。前述的晶片封装构造,另包含有复数个承载接垫,以供固着该晶片。前述的晶片封装构造,其中该些承载接垫与该些打线接垫是为等尺寸并为棋盘排列。前述的晶片封装构造,其中该些下接合层的防锈性是较优于该些电铸核心。前述的晶片封装构造,其中该些下接合层是选自于镍-金层、镍-钯-金层、锡层与锡铅共晶层的其中之一。前述的晶片封装构造,其中该些上接合层是选自于镍-金层、镍-钯-金层与银层的其中之一。前述的晶片封装构造,其中该些下接合层是与该封胶体的底面为共平面。
借由上述技术方案,本发明具有阵列接垫的晶片封装构造及其制造方法至少具有下列优点:
1、本发明具有阵列接垫的晶片封装构造及其制造方法,借由利用电铸形成的打线接垫,使其电铸核心完全被封胶体所密封,并使其仅有打线接垫的下接合层是显露于一封胶体之外,而具有防止电铸核心生锈的功效,并且可以提升产品的可靠性,还能够避免现有习知的导线架的引脚的天线效应,非常适于实用。此外,借由打线接垫的阵列形成,还能够达到高密度的晶片封装,从而更加适于实用。
2、本发明具有阵列接垫的晶片封装构造及其制造方法,可以避免显露在封胶体底面的下接合层被刮伤或磨损,并且兼具有增进的防锈功效,更加适于实用。
3、本发明的具有阵列接垫的晶片封装构造的制造方法,在封装制程中是持续使用一刚性导电模板进行电铸、粘晶、打线与封装的步骤,不需要中途更换载具,而可以达到封装作业的一贯性,非常适于产业应用。
综上所述,本发明是有关于一种具有阵列接垫的晶片封装构造及其制造方法。该晶片封装构造,主要包含复数个打线接垫、一晶片、复数个焊线以及一封胶体。该些打线接垫的电铸核心的上下各形成有一上接合层与一下接合层,其中该电铸核心的材质包含铜。该些焊线是电性连接该晶片至该些打线接垫的上接合层。该封胶体是密封该些焊线、该些电铸核心与该些上接合层,其中在该些打线接垫中仅有该些下接合层是显露在该封胶体之外。本发明可解决以往导线架基底无外接脚式晶片封装构造中引脚外露切割面生锈的问题,并具有阵列接垫,能达到高密度的晶片封装。本发明的制造方法在封装制程中持续使用一刚性导电模板进行电铸、粘晶、打线与封装步骤,可达到封装作业的一贯性。本发明具有上述诸多优点及实用价值,其不论在产品结构、制造方法或功能上皆有较大的改进,在技术上有显著的进步,并产生了好用及实用的效果,且较现有的晶片封装构造及其制造方法具有增进的突出功效,从而更加适于实用,并具有产业的广泛利用价值,诚为一新颖、进步、实用的新设计。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图,详细说明如下。
附图说明
图1是现有习知的无接脚式晶片封装构造的截面示意图。
图2是现有习知的晶片封装构造的顶面透视图。
图3是依据本发明的第一具体实施例,一种具有阵列接垫的晶片封装构造的截面示意图。
图4是依据本发明的第一具体实施例,绘示该晶片封装构造的晶片与打线接垫的顶面示意图。
图5是依据本发明的第一具体实施例,在该晶片封装构造的制程中所提供的导电模板的顶面示意图。
图6A至图6G是依据本发明的第一具体实施例,该晶片封装构造在制程中的截面示意图。
图7是依据本发明的第二具体实施例,另一种具有阵列接垫的晶片封装构造的截面示意图。
图8是依据本发明的第二具体实施例,该晶片封装构造的底而示意图。
图9是依据本发明的第三具体实施例,另一种具有阵列接垫的晶片封装构造的截面示意图。
100:晶片封装构造 111:引脚
112:晶片承座 113:上表面
114:下表面 115:电镀层
116:引脚外露表面 120:晶片
121:焊垫 130:焊线
140:封胶体 200:晶片封装构造
210:打线接垫 211:下接合层
212:电铸核心 213:上接合层
220:晶片 221:主动面
222:背面 223:电极
230:焊线 240:封胶体
241:底面 250:晶片承座
260:导电模板 270:电铸遮罩
271:开孔图案 300:晶片封装构造
310:打线接垫 311:下接合层
312:电铸核心 313:上接合层
320:晶片 321:电极
330:焊线 340:封胶体
350:承载接垫 400:晶片封装构造
410:接垫 410A:虚置垫
411:下接合层 412:电铸核心
412A:侧面 413:上接合层
420:晶片 421:表面
422:电极 430:封胶体
431:底面
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的具有阵列接垫的晶片封装构造及其制造方法其具体实施方式、结构、制造方法、步骤、特征及其功效,详细说明如后。
请参阅图3及图4所示,图3是依据本发明的第一具体实施例,一种具有阵列接垫的晶片封装构造的截面示意图,图4是该晶片封装构造的晶片与打线接垫的顶面示意图。在本发明的第一具体实施例中,该具有阵列接垫的晶片封装构造200,主要包含复数个打线接垫210、一晶片220、复数个焊线230以及一封胶体240。
如图4所示,上述的该些打线接垫210,是为阵列排列,可任意多排的排列,其是由电铸技术形成(容后详述)。并且,如图3所示,该些打线接垫210是形成在同一平面。每一打线接垫210包含有一下接合层211、一电铸核心212与一上接合层213,其中:
该电铸核心212,其材质是包含铜,其是一种导电性佳、导热性佳且易于电镀的电属。该些电铸核心212的厚度大于对应下接合层211的厚度及大于对应上接合层213的厚度。
在本实施例中,该晶片封装构造200另包含有一晶片承座250,以供固着该晶片220,该晶片承座250亦能以电铸方法形成,可同样具有一电铸核心212与上、下接合层213、211,一接地焊线可接合在该晶片承座250上。在不同的实施例中,当该晶片承座250不需要打线焊接时,则该晶片承座250可不需要该上接合层213。
上述的晶片220,具有一主动面221、一背面222及复数个电极223,该些电极223可形成于该晶片220的该主动面221上,该些电极223除了可以如图3所示为焊垫形状,但亦可为凸块形状。该晶片220的该背面222是可利用胶膜类、B阶胶体(B-stage adhesive)、液体胶(liquid compound)等粘晶材料粘着于该晶片承座250。
上述的打线形成的该些焊线230,是电性连接该晶片220的该些电极223与该些打线接垫210的上接合层213,通常该些焊线230可为金线。
上述的封胶体240,是结合该晶片220与该些打线接垫210为一体并密封该些焊线230、该些电铸核心212与该些上接合层213。可利用压模、印刷或点胶方式提供该封胶体240,通常该封胶体240是为绝缘材料,包含无机填充剂、固化剂与色料等等。
其中,如图3所示,在该些打线接垫210中仅有该些下接合层211是显露在该封胶体240之外,该些电铸核心212不会有外露于该封胶体240的部份,而可以避免氧化生锈。较佳地,该些下接合层211的外露表面是与该封胶体240的底面241为共平面,以避免在产品搬运与使用过程该些下接合层211被刮伤或磨损。并且具有该些下接合层211内嵌于该封胶体240的型态,更可以避免该些下接合层211与该些电铸核心212的界面外露于大气中,而可以增进防锈的功效。
在本实施例中,该些下接合层211的防锈性能应较优于该些电铸核心212。例如相对于铜质的电铸核心212,该些下接合层211的材质是可选自于镍-金层、镍-钯-金层、锡层与锡铅共晶层的其中之一,或其它可供表面接合的抗氧化金属。而该些上接合层213的材质是可选自于镍-金层、镍-钯-金层与银层的其中之一,或其它可供焊接的金属。
因此,上述的晶片封装构造200具有以下的功效:一、具有防止电铸核心212由侧面产生生锈的功效,而可以提升产品可靠性;二、能够避免现有习知导线架的引脚的天线效应;三、该些打线接垫210的阵列排列能符合高密度的晶片封装。
请配合参阅图5、图6A~6G所示,图5是依据本发明的第一具体实施例,在该晶片封装构造的制程中所提供的导电模板的顶面示意图,图6A至图6G是该晶片封装构造在制程中的截面示意图。现将本发明的晶片封装构造的制造方法的第一具体实施例说明如下。该晶片封装构造200的制造方法,包括以下步骤:
首先,如图5与图6A所示,提供一刚性导电模板260,其具有一平坦表面,用以定义上述形成该些打线接垫210的共平面。再形成一电铸遮罩270于该导电模板260上,该电铸遮罩270是可由液态光阻与感光性干膜所构成。
如图6B所示,利用曝光显影的技术使得该电铸遮罩270图案化,而具有开孔图案271。
如图6C所示,依该电铸遮罩270的开孔图案271,并在该导电模板260的导通下,能以电铸技术依序形成一下接合层211、一电铸核心212与一上接合层213在该开孔图案271内,以构成复数个的该些打线接垫210于该导电模板260上,如此便能使该些打线接垫210阵列形成在同一平面。在本实施例中,并可同时形成该晶片承座250。
如图6D所示在移除该电铸遮罩270。如图6E所示在移除该电铸遮罩270之后,设置上述晶片220于该导电模板260的上方,在本实施例中,该晶片220是粘固于该晶片承座250。
如图6F所示,在不需要移除该导电模板260的条件下,接着,打线形成复数个焊线230,其是电性连接该些电极223与该些打线接垫210的上接合层213。
如图6G所示,之后,以半导体封装技术形成一封胶体240于该导电模板260上,该封胶体240是结合该晶片220与该些打线接垫210为一体并密封该些焊线230、该些电铸核心212与该些上接合层213,其中该些下接合层211仍是贴合于该导电模板260。
最后在该封胶体240形成之后,剥离该导电模板260,可使在该些打线接垫210中仅有该些下接合层211是显露在该封胶体240之外,而制得如图3所示的晶片封装构造200。因此,在前述的制造方法中,该导电模板260持续被使用在电铸、粘晶、打线与封装的步骤过程,不需要中途更换载具,而可以达到封装作业的一贯性。
请参阅图7及图8所示,图7是依据本发明的第二具体实施例,另一种具有阵列接垫的晶片封装构造的截面示意图,图8是该晶片封装构造的底面示意图。在本发明的具有阵列接垫的晶片封装构造的第二具体实施例中,揭示的另一种具有阵列接垫的晶片封装构造300,主要包含有与第一具体实施例大致相同的复数个打线接垫310、一晶片320、复数个焊线330以及一封胶体340,并可另包含复数个承载接垫350,以供固着该晶片320。
该些打线接垫310与该些承载接垫350,是由电铸技术形成,为阵列排列。较佳地,该些承载接垫350与该些打线接垫310是为等尺寸并为棋盘排列,其不需要额外规划与界定晶片承座的位置与尺寸,而可以达到共用公板,并兼具有分散承载晶片应力的功效。并且,如图7所示,该些打线接垫310是形成在同一平面。其中,每一打线接垫310或/及承载接垫350是包含有一下接合层311、一电铸核心312与一上接合层313。
该晶片320,是具有复数个电极321。
该打线形成的该些焊线330,是电性连接该晶片320的该些电极321与该些打线接垫310的上接合层313。
该封胶体340,是结合该晶片320、该些打线接垫310与该些承载接垫350成为一体,并且密封该些焊线330、该些电铸核心312与该些上接合层313。
其中,如图7所示,在该些打线接垫310与该些承载接垫350中,仅有该些下接合层311是显露在该封胶体340之外,该些电铸核心312不会有外露于该封胶体340的部份,而可以避免氧化生锈。
请参阅图图9所示,是依据本发明的第三具体实施例,另一种具有阵列接垫的晶片封装构造的截面示意图。本发明可进一步应用至非打线类型的不同晶片封装构造,在第三具体实施例中揭示的另一种具有阵列接垫的晶片封装构造400,主要包含复数个接垫410、一晶片420及一封胶体430。
该些接垫410,是阵列形成在同一平面,每一接垫410包含有一下接合层411与一电铸核心412,更可包含一上接合层413,使该电铸核心412位于该下接合层411与该上接合层413之间。
其中该些电铸核心412的材质是包含铜,具有导热佳与容易电铸形成的优点。并且该些电铸核心412的侧面412A是不被该下接合层411与该上接合层413所覆盖。
该晶片420,是具有复数个电极422,通常是形成在该晶片420的同一表面421上。该些电极422是电性连接至该些接垫410。在本实施例中,该些电极422是为凸块,该晶片420是以覆晶接合的方式设置于该些接垫410上。
较佳地,该些接垫410的排列方式为共用型,例如该些接垫410是为等尺寸并为棋盘排列。而依该晶片420的电极422数量不同变化,使得该些接垫410的数量能大于该些电极422,而使部分的该些接垫410为无电性传递的虚置垫410A(dummy pad)(如图9所示)。
该封胶体430,是结合该晶片420与该些接垫410为一体并密封该些电铸核心412的侧面412A,其中在该些接垫410中仅有该些下接合层411是显露在该封胶体430之外,以避免该些电铸核心412的锈化。较佳地,该些下接合层411是与该封胶体430的底面431为共平面,以使该些下接合层411内嵌于该封胶体430,使该些下接合层411免于被刮伤或磨损,更可以避免该些下接合层411与该些电铸核心412的界面外露于大气中,而可以增进防锈的功效。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (7)
1、一种具有阵列接垫的晶片封装构造,其特征在于其包含:
复数个打线接垫与复数个承载接垫,其是阵列形成在同一平面,每一打线接垫与承载接垫包含有一下接合层、一电铸核心与一上接合层,其中该电铸核心的材质是包含铜;
一晶片,其具有复数个电极,该晶片的背面仅固着于该些承载接垫上;
复数个焊线,其电性连接该些电极与该些打线接垫的上接合层;以及
一封胶体,其是结合该晶片与该些打线接垫为一体并密封该些焊线、该些电铸核心与该些上接合层,其中在该些打线接垫中仅有该些下接合层是显露在该封胶体之外。
2、根据权利要求1所述的具有阵列接垫的晶片封装构造,其特征在于其中所述的该些下接合层是选自于镍-金层、镍-钯-金层、锡层与锡铅共晶层的其中之一。
3、根据权利要求1所述的具有阵列接垫的晶片封装构造,其特征在于其中所述的该些上接合层是选自于镍-金层、镍-钯-金层与银层的其中之一。
4、根据权利要求1所述的具有阵列接垫的晶片封装构造,其特征在于其中所述的该些下接合层是与该封胶体的底面为共平面。
5、根据权利要求1所述的具有阵列接垫的晶片封装构造,其特征在于其中所述的该些承载接垫与该些打线接垫等尺寸并为棋盘排列。
6、一种晶片封装构造的制造方法,其特征在于其包括以下步骤:
提供一刚性导电模板;
形成一电铸遮罩于该导电模板上,并使其图案化;
依该电铸遮罩的开孔图案,电铸形成设有复数个打线接垫与复数个承载接垫于该导电模板上,该些打线接垫与该些承载接垫是阵列形成在同一平面,每一打线接垫与承载接垫包含有一下接合层、一电铸核心与一上接合层,其中该电铸核心的材质是包含铜;
设置至少一晶片于该导电模板上,该晶片的背面仅固着于该些承载接垫上;
形成复数个焊线,其是电性连接该些电极与该些打线接垫的上接合层;
形成一封胶体于该导电模板上,该封胶体是结合该晶片与该些打线接垫为一体并密封该些焊线、该些电铸核心与该些上接合层;以及
在该封胶体形成之后,剥离该导电模板,可使在该些打线接垫中仅有该些下接合层是显露在该封胶体之外。
7、根据权利要求6所述的晶片封装构造的制造方法,其特征在于其中所述的该些承载接垫与该些打线接垫等尺寸并为棋盘排列。
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