ATE95631T1 - Halbleiterpackung mit eingang/ausgangverbindungen hoher dichte. - Google Patents

Halbleiterpackung mit eingang/ausgangverbindungen hoher dichte.

Info

Publication number
ATE95631T1
ATE95631T1 AT87304417T AT87304417T ATE95631T1 AT E95631 T1 ATE95631 T1 AT E95631T1 AT 87304417 T AT87304417 T AT 87304417T AT 87304417 T AT87304417 T AT 87304417T AT E95631 T1 ATE95631 T1 AT E95631T1
Authority
AT
Austria
Prior art keywords
high density
semiconductor package
fingers
output connections
tape
Prior art date
Application number
AT87304417T
Other languages
English (en)
Inventor
Lawrence Arnold Greenberg
David Jacob Lando
Original Assignee
American Telephone & Telegraph
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone & Telegraph filed Critical American Telephone & Telegraph
Application granted granted Critical
Publication of ATE95631T1 publication Critical patent/ATE95631T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/479—Leadframes on or in insulating or insulated package substrates, interposers, or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/435—Shapes or dispositions of insulating layers on leadframes, e.g. bridging members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AT87304417T 1986-05-27 1987-05-19 Halbleiterpackung mit eingang/ausgangverbindungen hoher dichte. ATE95631T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/866,931 US4774635A (en) 1986-05-27 1986-05-27 Semiconductor package with high density I/O lead connection
EP87304417A EP0247775B1 (de) 1986-05-27 1987-05-19 Halbleiterpackung mit Eingang/Ausgang-Verbindungen hoher Dichte

Publications (1)

Publication Number Publication Date
ATE95631T1 true ATE95631T1 (de) 1993-10-15

Family

ID=25348753

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87304417T ATE95631T1 (de) 1986-05-27 1987-05-19 Halbleiterpackung mit eingang/ausgangverbindungen hoher dichte.

Country Status (7)

Country Link
US (1) US4774635A (de)
EP (1) EP0247775B1 (de)
JP (1) JP2671922B2 (de)
KR (1) KR960004562B1 (de)
AT (1) ATE95631T1 (de)
CA (1) CA1252912A (de)
DE (1) DE3787671T2 (de)

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US4974057A (en) * 1986-10-31 1990-11-27 Texas Instruments Incorporated Semiconductor device package with circuit board and resin
US4903113A (en) * 1988-01-15 1990-02-20 International Business Machines Corporation Enhanced tab package
US4987475A (en) * 1988-02-29 1991-01-22 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
JP2786209B2 (ja) * 1988-10-07 1998-08-13 株式会社日立製作所 忘却機能を有する知識データ管理方法
DE3834361A1 (de) * 1988-10-10 1990-04-12 Lsi Logic Products Gmbh Anschlussrahmen fuer eine vielzahl von anschluessen
US5466967A (en) * 1988-10-10 1995-11-14 Lsi Logic Products Gmbh Lead frame for a multiplicity of terminals
US4924291A (en) * 1988-10-24 1990-05-08 Motorola Inc. Flagless semiconductor package
US5183711A (en) * 1988-12-13 1993-02-02 Shinko Electric Industries Co., Ltd. Automatic bonding tape used in semiconductor device
JP2687152B2 (ja) * 1988-12-13 1997-12-08 新光電気工業株式会社 高周波半導体デバイス用のｔａｂテープ
DE3942843A1 (de) * 1989-12-23 1991-06-27 Itt Ind Gmbh Deutsche Verkapselte monolithisch integrierte schaltung
JPH02201948A (ja) * 1989-01-30 1990-08-10 Toshiba Corp 半導体装置パッケージ
US5255156A (en) * 1989-02-22 1993-10-19 The Boeing Company Bonding pad interconnection on a multiple chip module having minimum channel width
US5432127A (en) * 1989-06-30 1995-07-11 Texas Instruments Incorporated Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads
US5233220A (en) * 1989-06-30 1993-08-03 Texas Instruments Incorporated Balanced capacitance lead frame for integrated circuits and integrated circuit device with separate conductive layer
JPH0336614A (ja) * 1989-07-03 1991-02-18 Mitsumi Electric Co Ltd 回路モジュール
DE68905475T2 (de) * 1989-07-18 1993-09-16 Ibm Halbleiter-speichermodul hoeher dichte.
JPH0777256B2 (ja) * 1989-08-25 1995-08-16 株式会社東芝 樹脂封止型半導体装置
JPH0363774U (de) * 1989-10-23 1991-06-21
US5355017A (en) * 1990-04-06 1994-10-11 Sumitomo Special Metal Co. Ltd. Lead frame having a die pad with metal foil layers attached to the surfaces
EP0458469A1 (de) * 1990-05-24 1991-11-27 Nippon Steel Corporation Verbundleiterrahmen und ihn verwendende Halbleitervorrichtung
US5227662A (en) * 1990-05-24 1993-07-13 Nippon Steel Corporation Composite lead frame and semiconductor device using the same
US5173766A (en) * 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package
JP2744685B2 (ja) * 1990-08-08 1998-04-28 三菱電機株式会社 半導体装置
US5233131A (en) * 1990-12-19 1993-08-03 Vlsi Technology, Inc. Integrated circuit die-to-leadframe interconnect assembly system
JPH04280462A (ja) * 1991-03-08 1992-10-06 Mitsubishi Electric Corp リードフレームおよびこのリードフレームを使用した半導体装置
KR940007649B1 (ko) * 1991-04-03 1994-08-22 삼성전자 주식회사 반도체 패키지
US5177591A (en) * 1991-08-20 1993-01-05 Emanuel Norbert T Multi-layered fluid soluble alignment bars
US5231755A (en) * 1991-08-20 1993-08-03 Emanuel Technology, Inc. Method of forming soluble alignment bars
KR930006868A (ko) * 1991-09-11 1993-04-22 문정환 반도체 패키지
KR940006083B1 (ko) * 1991-09-11 1994-07-06 금성일렉트론 주식회사 Loc 패키지 및 그 제조방법
US5249354A (en) * 1991-09-25 1993-10-05 American Telephone & Telegraph Co. Method of making electronic component packages
WO1993017455A2 (en) * 1992-02-20 1993-09-02 Vlsi Technology, Inc. Integrated-circuit package configuration for packaging an integrated-circuit die and method of packaging an integrated-circuit die
US5266833A (en) * 1992-03-30 1993-11-30 Capps David F Integrated circuit bus structure
US5365409A (en) * 1993-02-20 1994-11-15 Vlsi Technology, Inc. Integrated circuit package design having an intermediate die-attach substrate bonded to a leadframe
US5384487A (en) * 1993-05-05 1995-01-24 Lsi Logic Corporation Off-axis power branches for interior bond pad arrangements
US5567655A (en) * 1993-05-05 1996-10-22 Lsi Logic Corporation Method for forming interior bond pads having zig-zag linear arrangement
US5424492A (en) * 1994-01-06 1995-06-13 Dell Usa, L.P. Optimal PCB routing methodology for high I/O density interconnect devices
US5455387A (en) * 1994-07-18 1995-10-03 Olin Corporation Semiconductor package with chip redistribution interposer
US5939775A (en) * 1996-11-05 1999-08-17 Gcb Technologies, Llc Leadframe structure and process for packaging intergrated circuits
US6201292B1 (en) * 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
US6342731B1 (en) * 1997-12-31 2002-01-29 Micron Technology, Inc. Vertically mountable semiconductor device, assembly, and methods
JP3914651B2 (ja) * 1999-02-26 2007-05-16 エルピーダメモリ株式会社 メモリモジュールおよびその製造方法
JP2004253706A (ja) * 2003-02-21 2004-09-09 Seiko Epson Corp リードフレーム、半導体チップのパッケージング部材、半導体装置の製造方法、及び、半導体装置

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US31967A (en) * 1861-04-09 Improvement in cotton-presses
USRE31967E (en) 1975-07-07 1985-08-13 National Semiconductor Corporation Gang bonding interconnect tape for semiconductive devices and method of making same
JPS56100436A (en) * 1980-01-17 1981-08-12 Toshiba Corp Manufacture of semiconductor element
US4371912A (en) * 1980-10-01 1983-02-01 Motorola, Inc. Method of mounting interrelated components
JPS57207356A (en) * 1981-06-15 1982-12-20 Fujitsu Ltd Semiconductor device
JPS5815241A (ja) * 1981-07-20 1983-01-28 Sumitomo Electric Ind Ltd 半導体装置用基板
JPS58107659A (ja) * 1981-12-21 1983-06-27 Seiko Keiyo Kogyo Kk Ｉｃの実装装置
JPS58122763A (ja) * 1982-01-14 1983-07-21 Toshiba Corp 樹脂封止型半導体装置
DE3219055A1 (de) * 1982-05-21 1983-11-24 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Verfahren zur herstellung eines filmtraegers mit leiterstrukturen
US4498122A (en) * 1982-12-29 1985-02-05 At&T Bell Laboratories High-speed, high pin-out LSI chip package
JPS60227454A (ja) * 1984-04-26 1985-11-12 Nec Corp 半導体素子用リ−ドフレ−ム
DE3516954A1 (de) * 1984-05-14 1985-11-14 Gigabit Logic, Inc., Newbury Park, Calif. Montierte integrierte schaltung
US4631820A (en) * 1984-08-23 1986-12-30 Canon Kabushiki Kaisha Mounting assembly and mounting method for an electronic component
JPS61183936A (ja) * 1985-02-08 1986-08-16 Toshiba Corp 半導体装置
JPS622628A (ja) * 1985-06-28 1987-01-08 Toshiba Corp 半導体装置
US4754317A (en) * 1986-04-28 1988-06-28 Monolithic Memories, Inc. Integrated circuit die-to-lead frame interconnection assembly and method

Also Published As

Publication number Publication date
EP0247775A2 (de) 1987-12-02
EP0247775B1 (de) 1993-10-06
DE3787671T2 (de) 1994-02-03
US4774635A (en) 1988-09-27
DE3787671D1 (de) 1993-11-11
KR960004562B1 (ko) 1996-04-09
EP0247775A3 (en) 1988-01-20
CA1252912A (en) 1989-04-18
KR870011692A (ko) 1987-12-26
JP2671922B2 (ja) 1997-11-05
JPS6324647A (ja) 1988-02-02

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee