EP0247775B1 - Halbleiterpackung mit Eingang/Ausgang-Verbindungen hoher Dichte - Google Patents

Halbleiterpackung mit Eingang/Ausgang-Verbindungen hoher Dichte Download PDF

Info

Publication number
EP0247775B1
EP0247775B1 EP87304417A EP87304417A EP0247775B1 EP 0247775 B1 EP0247775 B1 EP 0247775B1 EP 87304417 A EP87304417 A EP 87304417A EP 87304417 A EP87304417 A EP 87304417A EP 0247775 B1 EP0247775 B1 EP 0247775B1
Authority
EP
European Patent Office
Prior art keywords
conductors
paddle
fingers
pad
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP87304417A
Other languages
English (en)
French (fr)
Other versions
EP0247775A3 (en
EP0247775A2 (de
Inventor
Lawrence Arnold Greenberg
David Jacob Lando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc, AT&T Corp filed Critical American Telephone and Telegraph Co Inc
Priority to AT87304417T priority Critical patent/ATE95631T1/de
Publication of EP0247775A2 publication Critical patent/EP0247775A2/de
Publication of EP0247775A3 publication Critical patent/EP0247775A3/en
Application granted granted Critical
Publication of EP0247775B1 publication Critical patent/EP0247775B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Definitions

  • This invention relates to semiconductor device packages, and in particular to a package requiring a high density of connections from the semiconductor to external leads.
  • the semiconductor chip is electrically connected to outside circuitry by means of a lead frame.
  • the lead frame may be thought of as a solid metal picture frame with fingers radiating inward from either two opposing sides or from all four sides toward the geometric center of the frame. Also radiating inward from each of the four corners of the frame is a finger which terminates on a square or rectangular piece of metal, typically referred to as a paddle, which occupies a portion of the geometric center.
  • One major surface of the chip is bonded to the paddle, and contact pads on the opposite surface are electrically coupled to the lead frame fingers by bonding conductive wires to the pads and fingers.
  • the chip and a portion of the lead frame fingers are then encapsulated or molded in a material such as an epoxy or plastic molding compound, and the molded package body and lead frame fingers are cut from the frame.
  • the lead frame fingers are then formed to provide a means of electrically connecting the package to the second level interconnection board, which is typically a printed circuit board.
  • the severed fingers therefore constitute the I/O (Input/Output) leads for the semiconductor chip.
  • a further problem which exists in many semiconductor packages is inadequate heat removal from the chip during operation. This is more troublesome as chips become more complex and are required to do more functions. It is, therefore, also desirable to provide a semiconductor package with efficient heat dissipation.
  • EP-A-0 247 644 discloses a lead frame assembly with a semiconductor chip mounted on a central paddle. Conductor pads on the chip are connected to conductors of the lead frame by 3 sets of conductors.
  • the lead frame, 10 includes a first plurality of conductive fingers, such as 11, radiating inward from the solid picture-frame-like perimeter, 12. In this example, the fingers are present on all four sides of the perimeter, but may also be present on any lesser number of sides.
  • the lead frame also includes a paddle, 13, located at the center, with a second plurality of conductive fingers, such as 14, coupled to the paddle and extending to the four comers of the perimeter.
  • a gap, such as 15, is formed between the first plurality of conductive fingers (11) and the paddle on all four sides of the paddle.
  • the paddle, fingers and perimeter are typically formed from a sheet of metal such as alloyed copper.
  • the frame includes a total of 200 fingers, such as 11, extending to each side of the paddle (50 on each side). At their narrowest point, the fingers are approximately 8 mils (.2 mm) wide with a spacing of 8 mils (.2 mm) between each finger on a side ( thus producing a 16 mil (.4 mm) pitch).
  • the paddle is typically approximately 350 mils x 350 mils (8.9 x 8.9 mm).
  • the gap, 15, between the paddle and the fingers is approximately 10 mils (.25 mm). It would be desirable to bring the conductive fingers closer to the semiconductor device to be bonded to the paddle, but it is difficult to do this since the fingers cannot generally be made narrower than 8 mils (.2 mm).
  • This width limitation is due primarily to the fact that a lead frame is etched from a sheet of metal approximately 8 mils (.2 mm) thick and the etching features are limited to the thickness. (The lead frame can also be stamped from sheet metal, but similar dimensional limitations apply).
  • this element comprises a third plurality of conductive fingers, such as 16, formed on an insulating layer 17 mounted on the paddle 13.
  • These conductive fingers correspond in number and position to the conductive fingers 11 of the lead frame and have their outer ends 23 extending approximately 10 mils (.25 mm) beyond the insulating layer and bonded to the upper surface of an associated conductive finger, while their inner ends 24 either form a gap, 40, extending approximately 10 mils (.25mm) from the sides of a hole, 18, formed in the insulating layer, or extend right up to the sides of the hole, 18.
  • the outer dimension of the insulating layer, 17, is shown as slightly smaller than the paddle, it could be equal to or greater than the sin of the paddle.
  • the portion of the paddle, 13, exposed by the hole, 18, forms a mounting pad 41 for a semiconductor chip to be described.
  • the fingers 16 preferably form a gap 40 with the pad which is less than the gap 42 between the lead frame fingers 11 and the pad.
  • the additional element was formed from a wire-bondable tape which was supplied by 3M Company for Tape Automated Bonding (TAB) packages.
  • the conductive fingers were made of 99.9% copper plated to a thickness of approximately 2 mils (.05 mm) and each had a width of 8 mils (.2 mm) and a separation between fingers of approximately 2 mils (.05 mm) to produce a pitch of 10 mils (.25 mm).
  • the fingers, 16, can be placed closer together than the lead frame fingers 11, since the former are fabricated by plating rather than etching or stamping. Further, even if fingers 16 were etched, they are thinner and so can be placed closer together.
  • the standard tape was modified by punching the hole, 18, in the insulator 17 at the center. The hole measured approximately 250 mils x 250 mils (6.4 x 6.4 mm).
  • the insulating layer, 17, was bonded to the underlying paddle, 13, and the conductive fingers 16 on the insulator were bonded to their corresponding fingers 11 of the lead frame by thermocompression bonding. This typically involves heating the structure at a temperature of approximately 550 degrees C for .2 seconds while applying pressure of approximately 40 PSI (.28 M Pa).
  • the semiconductor chip, 20 was placed in the hole 18 of the insulating layer 17 so that the back surface of the chip was in mechanical contact with the mounting portion of the underlying paddle, 13.
  • the chip was bonded to the paddle by conductive epoxy.
  • the paddle and connected fingers, 14, therefore provided a ground connection to the back surface of the chip.
  • the paddle provided an excellent heat sink during the operation of the chip.
  • the calculated heat dissipation for a 148 pin package assuming natural convection cooling was approximately 32 degrees per watt for this embodiment, which was approximately 3 degrees per watt better than when the chip was bonded to a conductive pad on the tape (FIG. 4).
  • the chip measured approximately 190 mils x 200 mils (4.8 x 5.1 mm).
  • the front surface of the chip, 20, included a plurality of bonding pads, such as 21, on its periphery. These pads were made of aluminum with a thickness of approximately 1 micron and measured approximately 4 mils x 4 mils (.1 x .1 mm). The pads were also spaced approximately 4 mils (.1 mm) apart. Electrical connection between each of these pads and their corresponding conductive fingers on the insulating layer was provided by wires 22 attached to the pad and finger by standard wire bonding techniques. This involved ball bonding one end of a wire to a pad and then wedge bonding the other end of the wire to the conductive finger while heating to a temperature of 200 degrees C.
  • the smaller pitch of the conductive fingers 16 formed on the insulating layer 17 permits the fingers to be brought closer to the semiconductor device, 20, than is practical for the lead frame fingers for a high density interconnect package. This allows a relatively short span for the wires 22 to traverse and thereby reduces the possibility of failures in the wire connections.
  • FIG. 4 While the embodiment of FIG. 3 appears preferable in terms of maximum heat dissipation, the embodiment illustrated in FIG. 4, where corresponding elements are similarly numbered, may also be useful. (For the sake of clarity, the lead frame is not shown in FIG. 4.) It will be noted that the major distinction in the embodiment of FIG. 4 is that the device, 20, is bonded to a conductive material pad, 30, which is formed on the insulating layer 17 at the center of the conductive finger pattern. Tabs 32-35 also extend from the corners of the pad 30 out beyond the ends of the insulator 17. The layer 17 is bonded to the paddle (13 of FIG. 2) and the fingers, 16, are bonded to the lead frame fingers (11 of Fig. 2) as before.
  • the Tabs 32-35 are thermocompression bonded to corresponding fingers (14 of FIG. 2) coupled to the paddle. Ground connection to the device is, therefore, provided through pad 30 and tabs 32-35 rather than through the paddle 13. In fact, in this embodiment the paddle can be dispensed with and ground connections made by wire-bonding or thermocompression bonding the tabs 32-35 to appropriate conductors of the lead frame.
  • the pad 30 was made of copper, with a thin layer (approximately 30 micro-inches or .75 micros) of gold on the surface. The pad was approximately 220 mils (5.6 mm) long, 220 mils (5.6 mm) wide and 2 mils (.05 mm) thick.
  • FIGS. 3 or 4 is encapsulated with a standard material, such as room temperature vulcanizing silicone rubber, which covered the device, conductive fingers on the insulator, the paddle, and at least a portion of the conductive fingers of the lead frame.
  • the fingers of the lead frame are then cut from the perimeter 12 and appropriately formed so that each would comprise an I/O lead for the package suitable for connection for instance to printed circuit boards.
  • a typical final package is shown in a perspective view in FIG. 5 with the encapsulant shown as element 31.
  • the package described herein appears most advantageous for semiconductor devices requiring a high number of I/O leads, i.e., at least 15 on a side.
  • the invention is also advantageous where it is desired to reduce the size of the chip, for example to less than 100 mils (2.5 mm) on a side, so that a higher density of interconnection is required.
  • the invention is most advantageous where a pitch of less than 16 mils (.4 mm) is desirable for the ends of the conductive fingers nearest the chip so that wire spans of less than 150 mils (3.8 mm) can be achieved.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Claims (6)

  1. Halbleitereinrichtungs-Gehäuse mit einem Leitungsrahmen (10) mit einer, einem in der Mitte angeordneten Fläche (30) oder Paddel (13), einer mit einer Hauptoberfläche an einem Befestigungsabschnitt (30 oder 41) der Fläche oder des Paddels direkt befestigten Halbleitereinrichtung und mit Anschlußflächen für das Bonden (21), die an dem Außenumfang deren gegenüberliegenden Hauptoberfläche angeordnet sind, mit leitfähigen Fingern (11) des Leitungsrahmens, die als erste Vielzahl von Leitern (11) dienen, wobei ein Ende von jedem in enger flächiger Nähe zu der Fläche oder dem Paddel ist, mit einem isolierenden Band oder einer isolierenden Schicht (17), die auf dem Paddel oder der Fläche ausgebildet ist, einer anderen Vielzahl an Leitern (16), die auf dem isolierenden Band oder der Schicht ausgebildet ist, wobei jeder Leiter der anderen Vielzahl von Leitern in direktem elektrischen Kontakt mit besagtem einen Ende eines jeweiligen Leiters der ersten Vielzahl von Leitern steht und mit einem Bonddraht mit einer jeweiligen Bond-Anschlußfläche der Halbleitereinrichtung verbunden ist, dadurch gekennzeichnet, daß die Fläche oder das Paddel als leitfähige Befestigungsfläche und Wärmesenke für die Halbleitereinrichtung dient und daß jeder Leiter der besagten anderen Vielzahl an Leitern (16) sich über den Außenumfang des isolierenden Bandes oder der Schicht (17) erstreckt und besagten direkten Kontakt mit dem besagten einen Ende des jeweiligen Leiters aus der ersten Vielzahl von Leitern bildet.
  2. Gehäuse nach Anspruch 1, dadurch gekennzeichnet, daß die Länge jedes Bonddrahtes geringer als 3,8 mm (150 mils) ist.
  3. Gehäuse nach Anspruch 1, dadurch gekennzeichnet, daß die Anzahl der Drahtverbindungen zwischen den Bond-Anschlußflächen und der Leiter besagter anderer Vielzahl von Leitern (16) wenigstens 15 Stück pro Seite der Halbleitereinrichtung beträgt.
  4. Gehäuse nach Anspruch 1, dadurch gekennzeichnet, daß der Abstand der Leiter besagter anderer Vielzahl von Leitern (16) geringer als 0,4 mm (16 mils) ist.
  5. Gehäuse nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, daß die isolierende Schicht eine Öffnung (18) in sich enthält, um den Befestigungsabschnitt zu bilden.
  6. Gehäuse nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, daß die sich über den Außenumfang des isolierenden Bandes oder der Schicht erstreckenden Leiter an die jeweiligen ersten Leiter thermokompressionsgebondet sind.
EP87304417A 1986-05-27 1987-05-19 Halbleiterpackung mit Eingang/Ausgang-Verbindungen hoher Dichte Expired - Lifetime EP0247775B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT87304417T ATE95631T1 (de) 1986-05-27 1987-05-19 Halbleiterpackung mit eingang/ausgangverbindungen hoher dichte.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/866,931 US4774635A (en) 1986-05-27 1986-05-27 Semiconductor package with high density I/O lead connection
US866931 1992-04-10

Publications (3)

Publication Number Publication Date
EP0247775A2 EP0247775A2 (de) 1987-12-02
EP0247775A3 EP0247775A3 (en) 1988-01-20
EP0247775B1 true EP0247775B1 (de) 1993-10-06

Family

ID=25348753

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87304417A Expired - Lifetime EP0247775B1 (de) 1986-05-27 1987-05-19 Halbleiterpackung mit Eingang/Ausgang-Verbindungen hoher Dichte

Country Status (7)

Country Link
US (1) US4774635A (de)
EP (1) EP0247775B1 (de)
JP (1) JP2671922B2 (de)
KR (1) KR960004562B1 (de)
AT (1) ATE95631T1 (de)
CA (1) CA1252912A (de)
DE (1) DE3787671T2 (de)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2582013B2 (ja) * 1991-02-08 1997-02-19 株式会社東芝 樹脂封止型半導体装置及びその製造方法
US4974057A (en) * 1986-10-31 1990-11-27 Texas Instruments Incorporated Semiconductor device package with circuit board and resin
US4903113A (en) * 1988-01-15 1990-02-20 International Business Machines Corporation Enhanced tab package
US4987475A (en) * 1988-02-29 1991-01-22 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
JP2786209B2 (ja) * 1988-10-07 1998-08-13 株式会社日立製作所 忘却機能を有する知識データ管理方法
DE3834361A1 (de) * 1988-10-10 1990-04-12 Lsi Logic Products Gmbh Anschlussrahmen fuer eine vielzahl von anschluessen
US5466967A (en) * 1988-10-10 1995-11-14 Lsi Logic Products Gmbh Lead frame for a multiplicity of terminals
US4924291A (en) * 1988-10-24 1990-05-08 Motorola Inc. Flagless semiconductor package
US5183711A (en) * 1988-12-13 1993-02-02 Shinko Electric Industries Co., Ltd. Automatic bonding tape used in semiconductor device
JP2687152B2 (ja) * 1988-12-13 1997-12-08 新光電気工業株式会社 高周波半導体デバイス用のｔａｂテープ
DE3942843A1 (de) * 1989-12-23 1991-06-27 Itt Ind Gmbh Deutsche Verkapselte monolithisch integrierte schaltung
JPH02201948A (ja) * 1989-01-30 1990-08-10 Toshiba Corp 半導体装置パッケージ
US5255156A (en) * 1989-02-22 1993-10-19 The Boeing Company Bonding pad interconnection on a multiple chip module having minimum channel width
US5233220A (en) * 1989-06-30 1993-08-03 Texas Instruments Incorporated Balanced capacitance lead frame for integrated circuits and integrated circuit device with separate conductive layer
US5432127A (en) * 1989-06-30 1995-07-11 Texas Instruments Incorporated Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads
JPH0336614A (ja) * 1989-07-03 1991-02-18 Mitsumi Electric Co Ltd 回路モジュール
EP0408779B1 (de) * 1989-07-18 1993-03-17 International Business Machines Corporation Halbleiter-Speichermodul höher Dichte
JPH0777256B2 (ja) * 1989-08-25 1995-08-16 株式会社東芝 樹脂封止型半導体装置
JPH0363774U (de) * 1989-10-23 1991-06-21
US5355017A (en) * 1990-04-06 1994-10-11 Sumitomo Special Metal Co. Ltd. Lead frame having a die pad with metal foil layers attached to the surfaces
EP0458469A1 (de) * 1990-05-24 1991-11-27 Nippon Steel Corporation Verbundleiterrahmen und ihn verwendende Halbleitervorrichtung
US5227662A (en) * 1990-05-24 1993-07-13 Nippon Steel Corporation Composite lead frame and semiconductor device using the same
US5173766A (en) * 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package
JP2744685B2 (ja) * 1990-08-08 1998-04-28 三菱電機株式会社 半導体装置
US5233131A (en) * 1990-12-19 1993-08-03 Vlsi Technology, Inc. Integrated circuit die-to-leadframe interconnect assembly system
JPH04280462A (ja) * 1991-03-08 1992-10-06 Mitsubishi Electric Corp リードフレームおよびこのリードフレームを使用した半導体装置
KR940007649B1 (ko) * 1991-04-03 1994-08-22 삼성전자 주식회사 반도체 패키지
US5177591A (en) * 1991-08-20 1993-01-05 Emanuel Norbert T Multi-layered fluid soluble alignment bars
US5231755A (en) * 1991-08-20 1993-08-03 Emanuel Technology, Inc. Method of forming soluble alignment bars
KR930006868A (ko) * 1991-09-11 1993-04-22 문정환 반도체 패키지
KR940006083B1 (ko) * 1991-09-11 1994-07-06 금성일렉트론 주식회사 Loc 패키지 및 그 제조방법
US5249354A (en) * 1991-09-25 1993-10-05 American Telephone & Telegraph Co. Method of making electronic component packages
JP2691799B2 (ja) * 1992-02-20 1997-12-17 ブイ・エル・エス・アイ・テクノロジー・インコーポレイテッド リードフレームに接合された介在ダイ取付基板を有する集積回路パッケージ設計
US5266833A (en) * 1992-03-30 1993-11-30 Capps David F Integrated circuit bus structure
US5365409A (en) * 1993-02-20 1994-11-15 Vlsi Technology, Inc. Integrated circuit package design having an intermediate die-attach substrate bonded to a leadframe
US5567655A (en) * 1993-05-05 1996-10-22 Lsi Logic Corporation Method for forming interior bond pads having zig-zag linear arrangement
US5384487A (en) * 1993-05-05 1995-01-24 Lsi Logic Corporation Off-axis power branches for interior bond pad arrangements
US5424492A (en) * 1994-01-06 1995-06-13 Dell Usa, L.P. Optimal PCB routing methodology for high I/O density interconnect devices
US5455387A (en) * 1994-07-18 1995-10-03 Olin Corporation Semiconductor package with chip redistribution interposer
US5939775A (en) * 1996-11-05 1999-08-17 Gcb Technologies, Llc Leadframe structure and process for packaging intergrated circuits
US6201292B1 (en) * 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
US6342731B1 (en) * 1997-12-31 2002-01-29 Micron Technology, Inc. Vertically mountable semiconductor device, assembly, and methods
JP3914651B2 (ja) * 1999-02-26 2007-05-16 エルピーダメモリ株式会社 メモリモジュールおよびその製造方法
JP2004253706A (ja) * 2003-02-21 2004-09-09 Seiko Epson Corp リードフレーム、半導体チップのパッケージング部材、半導体装置の製造方法、及び、半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4480013A (en) * 1981-07-20 1984-10-30 Sumitomo Electric Industries, Ltd. Substrate for use in semiconductor apparatus
EP0247644A1 (de) * 1986-04-28 1987-12-02 Advanced Micro Devices, Inc. Verbindung zwischen integrierter Schaltung und Leiterrahmen mittels Brückenstruktur

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US31967A (en) * 1861-04-09 Improvement in cotton-presses
USRE31967E (en) 1975-07-07 1985-08-13 National Semiconductor Corporation Gang bonding interconnect tape for semiconductive devices and method of making same
JPS56100436A (en) * 1980-01-17 1981-08-12 Toshiba Corp Manufacture of semiconductor element
US4371912A (en) * 1980-10-01 1983-02-01 Motorola, Inc. Method of mounting interrelated components
JPS57207356A (en) * 1981-06-15 1982-12-20 Fujitsu Ltd Semiconductor device
JPS58107659A (ja) * 1981-12-21 1983-06-27 Seiko Keiyo Kogyo Kk Ｉｃの実装装置
JPS58122763A (ja) * 1982-01-14 1983-07-21 Toshiba Corp 樹脂封止型半導体装置
DE3219055A1 (de) * 1982-05-21 1983-11-24 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Verfahren zur herstellung eines filmtraegers mit leiterstrukturen
US4498122A (en) * 1982-12-29 1985-02-05 At&T Bell Laboratories High-speed, high pin-out LSI chip package
JPS60227454A (ja) * 1984-04-26 1985-11-12 Nec Corp 半導体素子用リ−ドフレ−ム
DE3516954A1 (de) * 1984-05-14 1985-11-14 Gigabit Logic, Inc., Newbury Park, Calif. Montierte integrierte schaltung
US4631820A (en) * 1984-08-23 1986-12-30 Canon Kabushiki Kaisha Mounting assembly and mounting method for an electronic component
JPS61183936A (ja) * 1985-02-08 1986-08-16 Toshiba Corp 半導体装置
JPS622628A (ja) * 1985-06-28 1987-01-08 Toshiba Corp 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4480013A (en) * 1981-07-20 1984-10-30 Sumitomo Electric Industries, Ltd. Substrate for use in semiconductor apparatus
EP0247644A1 (de) * 1986-04-28 1987-12-02 Advanced Micro Devices, Inc. Verbindung zwischen integrierter Schaltung und Leiterrahmen mittels Brückenstruktur

Also Published As

Publication number Publication date
KR870011692A (ko) 1987-12-26
EP0247775A3 (en) 1988-01-20
ATE95631T1 (de) 1993-10-15
KR960004562B1 (ko) 1996-04-09
CA1252912A (en) 1989-04-18
DE3787671D1 (de) 1993-11-11
JP2671922B2 (ja) 1997-11-05
JPS6324647A (ja) 1988-02-02
EP0247775A2 (de) 1987-12-02
US4774635A (en) 1988-09-27
DE3787671T2 (de) 1994-02-03

Similar Documents

Publication Publication Date Title
EP0247775B1 (de) Halbleiterpackung mit Eingang/Ausgang-Verbindungen hoher Dichte
US5365409A (en) Integrated circuit package design having an intermediate die-attach substrate bonded to a leadframe
EP0498446B1 (de) Verkapselte Anordnung mehrerer Halbleiterbausteine und Herstellungsverfahren dafür
US5639694A (en) Method for making single layer leadframe having groundplane capability
CA1201820A (en) Semiconductor integrated circuit including a lead frame chip support
KR100294719B1 (ko) 수지밀봉형 반도체장치 및 그 제조방법, 리드프레임
US5373188A (en) Packaged semiconductor device including multiple semiconductor chips and cross-over lead
US6458625B2 (en) Multi chip semiconductor package and method of construction
US5420460A (en) Thin cavity down ball grid array package based on wirebond technology
US4939570A (en) High power, pluggable tape automated bonding package
US4949224A (en) Structure for mounting a semiconductor device
US5563443A (en) Packaged semiconductor device utilizing leadframe attached on a semiconductor chip
JPH06224246A (ja) 半導体素子用高多端子化パッケージ
JPH05109972A (ja) リードフレーム及び集積回路チツプのパツケージ・アセンブリ
US5796159A (en) Thermally efficient integrated circuit package
US7508060B2 (en) Multi-chip semiconductor connector assemblies
US5168345A (en) Semiconductor device having a universal die size inner lead layout
US6791166B1 (en) Stackable lead frame package using exposed internal lead traces
US5808872A (en) Semiconductor package and method of mounting the same on circuit board
USRE36894E (en) Semiconductor package with high density I/O lead connection
US5220486A (en) Ic packing device
EP0436126A2 (de) Kunststoffumhüllte Halbleiteranordnung
US6057594A (en) High power dissipating tape ball grid array package
JP2691799B2 (ja) リードフレームに接合された介在ダイ取付基板を有する集積回路パッケージ設計
KR100474193B1 (ko) 비지에이패키지및그제조방법

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH DE FR GB IT LI NL SE

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH DE FR GB IT LI NL SE

17P Request for examination filed

Effective date: 19880708

17Q First examination report despatched

Effective date: 19900711

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH DE FR GB IT LI NL SE

REF Corresponds to:

Ref document number: 95631

Country of ref document: AT

Date of ref document: 19931015

Kind code of ref document: T

REF Corresponds to:

Ref document number: 3787671

Country of ref document: DE

Date of ref document: 19931111

ITF It: translation for a ep patent filed
ET Fr: translation filed
RAP4 Party data changed (patent owner data changed or rights of a patent transferred)

Owner name: AT&T CORP.

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
EAL Se: european patent in force in sweden

Ref document number: 87304417.6

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: AT

Payment date: 20010320

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: SE

Payment date: 20010321

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 20010323

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20010426

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 20010427

Year of fee payment: 15

Ref country code: BE

Payment date: 20010427

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20010502

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20010629

Year of fee payment: 15

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020519

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020519

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020520

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020531

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020531

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020531

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20021201

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20021203

EUG Se: european patent has lapsed
GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20020519

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030131

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 20021201

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050519