KR960040102A - 금속기재 다층 회로 기판 및 그 제조 방법과 이를 구비하는 반도체 모듈 - Google Patents

금속기재 다층 회로 기판 및 그 제조 방법과 이를 구비하는 반도체 모듈 Download PDF

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KR960040102A
KR960040102A KR1019960010843A KR19960010843A KR960040102A KR 960040102 A KR960040102 A KR 960040102A KR 1019960010843 A KR1019960010843 A KR 1019960010843A KR 19960010843 A KR19960010843 A KR 19960010843A KR 960040102 A KR960040102 A KR 960040102A
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metal
circuit board
insulating adhesive
based multilayer
adhesive layer
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KR1019960010843A
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KR100382631B1 (ko
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도시끼 사이또
나오미 요네무라
도모히로 미야꼬시
마꼬또 후꾸다
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야노 쓰네오
덴끼가가꾸고오교 가부시끼가이샤
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Priority claimed from JP8700195A external-priority patent/JPH08148781A/ja
Priority claimed from JP8700295A external-priority patent/JP3199599B2/ja
Priority claimed from JP8804595A external-priority patent/JP3282776B2/ja
Application filed by 야노 쓰네오, 덴끼가가꾸고오교 가부시끼가이샤 filed Critical 야노 쓰네오
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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
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    • H05K1/0203—Cooling of mounted components
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    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
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    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
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Abstract

금속판과, 하나 이상의 금속 산화물 및/또는 하나 이상의 금속 질화물을 함유하는 제 1절연성 접착층에 의하여 상기 금속판상에 결합되는 회로 기판으로 이루어지는 금속기재 다층 회로 기판이 제공되었다.

Description

금속기재 다층 회로 기판 및 그 제조 방법과 이를 구비하는 반도체 모듈
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 본 발명의 금속기재 (metal-base) 다층 회로 기판의 한 실시예를 설명하는 단면도, 제 6도는 본 발명의 금속기재 다층 회로 기판으로 사용된 금속기재 회로 기판을 설명하는 단면도.

Claims (16)

  1. 금속판과, 하나 이상의 금속 산화물 및/또는 하나 이상의 금속 질화물을 함유하는 제 1절연성 접착층에 의하여 상기 금속판상에 결합되는 회로 기판으로 이루어지는 금속기재 다층 회로 기판.
  2. 제 1항에 있어서, 상기 제 1절연성 접착층의 열 전도성은 35×10-4cal/㎝·sec·℃ 내지 150×10-4cal/㎝·sec·℃이며, 두께는 20㎛ 내지 200㎛인 것을 특징으로 하는 금속기재 다층 회로 기판.
  3. 제 1항에 있어서, 상기 금속 산화물은 알루미늄 산화물 또는 규소 산화물이며, 상기 금속 질화물은 보론질화물인 것을 특징으로 하는 금속기재 다층 회로 기판.
  4. 제 1항에 있어서, 상기 제 1회로 기판상에서 상기 제 1절연층 접착층과 마주대하는 상기 제 1회로 도체층의 표면 거칠기 (Rz)는 0.1㎛ 내지 10㎛인 것을 특징으로 하는 금속기재 다층 회로 기판.
  5. 제 4항에 있어서, 상기 회로 기판상의 상기 제 1회로 도체층에는 상기 제 1절연성 접착층과 마주대하는 도금된 구리층이 제공됨을 특징으로 하는 금속기재 다층 회로 기판.
  6. 제 5항에 있어서, 상기 도금된 구리층은 최소한 니켈 또는 코발트중의 하나를 포함함을 특징으로 하는 금속기재 다층 회로 기판.
  7. 제 1항에 있어서, 상기 회로 기판은, 하나 이상의 금속 산화물 및/또는 하나 이상의 금속 질화물을 함유하는 제 2절연성 접착층에 의하여 결합되는 두개 이상의 회로 도체층을 구비함을 특징으로 하는 금속기재 다층 회로 기판.
  8. 제 7항에 있어서, 상기 제 2절연성 접착층의 열 전도성은 35×104cal/㎝·sec·℃ 내지 150×10-4cal/㎝·sec·℃이며, 두께는 40㎛ 내지 200㎛인 것을 특징으로 하는 금속기재 다층 회로 기판.
  9. 제 1항에 있어서, 열 전도성이 높은 전도성 접착제를 사용하여 상기 제 1절연성 접착층상에 열 방출 전자장치를 장착함을 특징으로 하는 금속기재 다층 회로 기판.
  10. 제 9항에 있어서, 상기 제 1절연성 접착층과 상기 열 전도성이 높은 전도성 접착제 사이에 금속층이 제공됨을 특징으로 하는 금속기재 다층 회로 기판.
  11. 금속판과, 제 1절연성 접착층에 의하여 상기 금속판상에 형성된 제 1회로 도체층을 구비하는 금속기재 회로 기판의 상기 제 1회로 도체층상에 제 2절연성 접착층에 의하여 제 2회로 도체층을 형성하는 단계 (1)과, 상기 제 2회로 도체층과 상기 제 1회로 도체층을 전기적으로 연결시키는 관통홀을 형성시키는 단계 (2)와, 상기 제 2회로 도체층에 회로를 형성하는 단계 (3)으로 이루어지는, 청구항 1에 기재된 금속기재 다층 회로 기판의 제조방법.
  12. 제 11항에 있어서, 상기 제 1절연성 접착층은 단계 (2)전에 열경화되는 것을 특징으로 하는 금속기재 다층 회로 기판 제조 방법.
  13. 제 11항에 있어서, 상기 관통홀을 형성하기 위한 단계 (2)에서, 상기 제 2회로 도체층의 소정 부분을 에칭하여 제거함으로서 홀을 형성하고, 상기 홀을 통과하도록 레이저 빔을 조사하여 상기 제 2절연성 접착층을 제거함으로서 관통홀을 형성하는 것을 특징으로 하는 금속기재 다층 회로 기판 제조 방법.
  14. 제 11항에 있어서, 상기 제 1회로 도체층의 두께는 5㎛ 내지 150㎛인 것을 특징으로 하는 금속기재 다층 회로 기판 제조 방법.
  15. 청구항 8항에 기재된 금속기재 다층 회로 기판과 상기 회로 기판상에 장착된 반도체 장치를 구비하며, 알루미늄 와이어 또는 금 와이어에 의하여 와이어 본딩된 반도체 모듈.
  16. 제 15항에 있어서, 상기 회로 기판의 제 1절연성 접착층과 마주대하는 상기 제 1회로 도체층은 차폐 패턴으로 사용됨을 특징으로 하는 반도체 모듈.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960010843A 1995-04-12 1996-04-10 금속기재다층회로기판과이를구비하는반도체모듈 KR100382631B1 (ko)

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JP8700195A JPH08148781A (ja) 1994-09-19 1995-04-12 金属ベース多層回路基板
JP95-87001 1995-04-12
JP8700295A JP3199599B2 (ja) 1995-04-12 1995-04-12 金属ベース多層回路基板
JP95-87002 1995-04-12
JP95-88045 1995-04-13
JP8804595A JP3282776B2 (ja) 1995-04-13 1995-04-13 金属ベース多層回路基板
JP23400195 1995-09-12
JP95-234001 1995-09-12

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