KR970706604A - 반도체 장치 및 그의 실장 구조체(Semiconductor Device and lit Mounting Structure) - Google Patents
반도체 장치 및 그의 실장 구조체(Semiconductor Device and lit Mounting Structure)Info
- Publication number
- KR970706604A KR970706604A KR1019970701814A KR19970701814A KR970706604A KR 970706604 A KR970706604 A KR 970706604A KR 1019970701814 A KR1019970701814 A KR 1019970701814A KR 19970701814 A KR19970701814 A KR 19970701814A KR 970706604 A KR970706604 A KR 970706604A
- Authority
- KR
- South Korea
- Prior art keywords
- multilayer wiring
- layer
- semiconductor device
- mounting substrate
- insulator
- Prior art date
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract
반도체 칩(1)의 실장 기판측 상에 실장 기판과 전기적으로 접속된 반도체층을 갖는 다중 배선 구조가 설치되어 고 그의 다층 배선 구조체의 상기 실장 기판측의 표면에 볼형으로 배치된 불형 단자(5)를 갖고, 또 상기 다층 배선 구조체는 실장후의 반도체 칩과 실장 기판과의 열응력을 완화하는 완충층(7)과 다층 배선층(14)로 구성된 반도체 장치이다.
종래의 반도체 장치와 비교하여 배선 거리가 짧기 때문에, 인덕턴스 성분이 작고 속도가 고속화될 수 있다. 또한, 그라운드층과 전원층 간의 거리가 짧기 때문에 작동시의 노이즈가 경감될 수 있고, 다층 배선 구조체의 완충층이 실장시의 열응력을 완화시키고, 접속 신뢰도가 향상된다. 또, 와이어 본딩에 생략되어 단위 면적당 단자 수도 증가되었다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명을 실현하기 위한 축차 적충법에 의한 제법의 모식도이다. 제3도는 본 발명을 실현하기 위한 필름 적충법에 의한 제법의 모식도이다. 제4도는 실시예 1의 반도체 장치의 단면 모식도이다. 제5도는 실시예2의 반도체 장치의 단면 모식도이다.
Claims (19)
- 반도체 칩의 실장 기판측면 상에 실장 기판과 전기적으로 접속된 반도체층을 갖는 다층 배선 구조체가 설치되어 있고, 상기 다층 배선 구조체의 상기 실장 기판측의 표면에 그리드 얼이상으로 배치된 단자를 갖고, 또한 상기 다층 배선 구조체는 실장후의 반도체 칩과 실장 기판 사이에서 발생한 열응력을 완화하는 완충층과 다층 배선층으로 구성된 것을 특징으로 하는 반도체 장치.
- 반도체 칩의 실장 기판측면 상에 실장 기판과 전기적으로 접ㅈ속된 전도층을 갖는 다층 배선 구조제가 설치 되어 있고, 상기 다층 배선 구조체의 상기 실장 기판측의 표면에 그리두 어레이상으로 배치된 볼형 단자를 갖고, 또한 상기 다층 배선 구조체의 전기 신호를 전달하는 다층 배선 구조층의 층간 절연층은 실장후의 반도체 칩과 실장 기판 사이에서 발생한 열응력을 완화하는 재료로 구성된 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 다층의 배선 구조체 1개에 대하여 2개 이상의 반도체 칩이 설치된 반도체 장치.
- 제1항에 있어서, 상기 다층 배선 구조체가 3개 이상의 도체층을 갖고, 상기 도체층이 그라운드층, 전원층 및 배선층을 구비하고 있는 반도체 장치.
- 제1항에 있어서, 상기 완충층은 절연체와 이 절연체를 관통하여 형성된 복수의 도체로 이루어지고, 이 돛는 반도체 칩의 기판측면에 대하여 수직으로 검산상으로 형성되어 있고, 상기 절연체는 탄성율이 10㎏/㎟이하의 유기 고분자 재료로 구성된 것인 반도체 장치.
- 제1항에 있어서, 상기 완충층은 절연체와 이 절연체를 관통하여 형성된 복수의 도체로 이루어지고, 이도체는 반도체 칩의 기판측면에 대하여 수직으로 검산상으로 형성되어 있고, 상기 절연체는 플라이미드 절연막인 반도체 장치.
- 제1항에 있어서, 상기 완충층은 절연체와 이 절연체를 관통하여 형성된 복수의 도체로 이루어지고, 이 도체는 반도체 칩의 기판측면에 대하여 수직으로 검산상으로 구성되어 있고, 상기 절연체는 탄성율이 10㎏/㎟이하인 엘라스토머 및 저탄성 엔지니어링 플라스틱으로부터 선택된 재료로 구성된 반도체 장치.
- 제1항에 있어서, 상기 완충층은 절연체와 이 절연체를 관통하여 형성된 복수의 도체로 이루어지고, 이 도체는 반도체 칩의 기판측면에 대하여 수직으로 검산상으로 구성되고, 상기 절연체는 탄성율이 10㎏/㎟이하인 실리콘제의 엘라스토며, 불소계 렐라스토머, 또는 이들을 조합한 것인 반도체 장치.
- 제1항에 있어서, 상기 다층 배선층의 층간 절연층이 탄성율이 10㎏/㎟이하인 유기 고분자로 구성된 것인 반도체 장치.
- 제1항 또는 제2항에 있어서, 상기 다층 배선층의 층간 적연층이 폴리아미드 절연막인 반도체 장치.
- 제1항에 있어서, 상기 다층 배선층의 층간 절연층이 탄성율이 10㎏/㎟이하인 엘라스토머 및 저탄성 엔지니어링 플라스틱으로부터 선택된 것인 반도체 장치.
- 제1항에 있어서, 상기 다층 배선층의 층간 절연층이 탄성율이 10㎏/㎟이하인 실리콘계의 엘라스토머 불소계 엘라스토머, 또는 이들을 조합한 것인 반도체 장치.
- 제1항에 있어서, 상기 다층 배선 구조체의 실장 기판으로의 접속을 위한 불형 단자가 주석, 아연, 납을 포함한 땜납 합금, 은, 동 또는 금, 또는 이들을 금으로 피복시킨 금속 재료로 형성된 것인 반도체 장치.
- 제1항에 있어서, 상기 반도체 칩이 동작시에 있어서 방열을 위한 히트 스프레터를 갖는 반도체 장치.
- 제14항에 있어서 ,상기 히트 스프레더가 상기 반도체 칩 또는 반도체 칩과 이것에 접속된 상기 완충층이 매설되도록 구성된 것인 반도체 장치.
- 반도체 칩의 실장 기판측면 상에 실장 기판과 전기적으로 접속된 반도체층을 갖는 다층 배선 구조체가 설치되어 있고, 상기 다층 배선 구조체의 상기 실장 기판측의 표면에 그리두 어레이상으로 배치된 볼형 단자를 갖고, 또한 상기 다층 배선구조체는 실장후의 반도체 칩과 실장 기판 사이에서 발생한 영응력을 완화하는 완충층과 다층 배선층으로 구성되고, 상기 그리드 어레이 상으로 배치된 볼형 단자에 의해 상기 실장 기판 상에 접속, 탑재된 것을 특징으로 하는 실장 구조체.
- 반도체 칩외 실장 기판측면 상에 실장 기판과 전기적으로 접속된 전도층을 갖는 다층 배선 구조체가 설치되어 있고, 상기 다층 배선 구조체의 상기 실장 기판측의 표면에 그리드 어레이상으로 배치된 볼형 단자를 갖고, 또한 상기 다층 배선 구조체의 전기 신호를 전달하는 다층 배선층의 층간 절연층은 실장후의 반도체칩과 실장 기판 사이에서 발생한 열응력을 완화하는 재료로 구성되고, 상기 다층배선 구조체는 상기 그리고 어레이 상으로 배치된 볼형 단자에 의해 상기 실장 기판 상기 접속, 탑재된 것을 특징으로 하는 실장 구조체.
- 제16항에 있어서, 상기 완충층은 절연체와 상기 절연체를 관통하여 형성된복수의 도체로 이루어지고 이 도체는 반도체 칩의 기판측면 상에 대하여 수직으로 검산상으로 형성되고, 상기 절연체는 탄성율이 10㎏/㎟이하인 유기 고분자 재료로 구성된 것인 실장 구조체.
- 제16항에 있어서, 상기 다층 배선층의 층간 절연층이 탄성율이 10㎏/㎟이하인 유기 고분자 재료로 구성된 것인 실장 구조체.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
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JP2015176907A (ja) * | 2014-03-13 | 2015-10-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9960328B2 (en) | 2016-09-06 | 2018-05-01 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
KR102145219B1 (ko) * | 2018-07-27 | 2020-08-18 | 삼성전자주식회사 | 반도체 패키지 및 이를 포함하는 안테나 모듈 |
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1995
- 1995-04-12 WO PCT/JP1995/000714 patent/WO1996009645A1/ja not_active Application Discontinuation
- 1995-04-12 US US08/809,233 patent/US6028364A/en not_active Expired - Lifetime
- 1995-04-12 KR KR1019970701814A patent/KR100398714B1/ko not_active IP Right Cessation
Cited By (1)
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KR100336769B1 (ko) * | 1999-11-04 | 2002-05-16 | 박종섭 | 웨이퍼 레벨의 칩 사이즈 패키지 및 그 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
US6028364A (en) | 2000-02-22 |
KR100398714B1 (ko) | 2003-11-14 |
WO1996009645A1 (fr) | 1996-03-28 |
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