KR910005443A - 직접 장착 반도체 팩케이지 - Google Patents

직접 장착 반도체 팩케이지 Download PDF

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KR910005443A
KR910005443A KR1019900012532A KR900012532A KR910005443A KR 910005443 A KR910005443 A KR 910005443A KR 1019900012532 A KR1019900012532 A KR 1019900012532A KR 900012532 A KR900012532 A KR 900012532A KR 910005443 A KR910005443 A KR 910005443A
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circuit
semiconductor package
circuit board
semiconductor device
opening
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KR1019900012532A
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엠.치우 안소니
레스트 호워드
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엔.라이스 머레트
텍사스 인스트루먼츠 인코포레이티드
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Publication of KR910005443A publication Critical patent/KR910005443A/ko

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    • G—PHYSICS
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    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
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    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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Abstract

내용 없음

Description

직접 장착 반도체 팩케이지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 반도체 장치를 장착할 수 있는 인쇄 회로 기판을 도시한 도면,
제3도는 인쇄 회로 기판상에 장착된 반도체 장치를 도시한 도면,
제4도는 회로 기판상에 장착된 반도체 장치의 단면도.

Claims (14)

  1. 반도체 장치 및 인쇄 회로 기판 구조물의 반도체 팩케이지에 있어서, 기판내에 소정의 개구의 연부로 연장하는, 기판을 관통하는 다수의 개구를 갖고 있는, 기판상에 회로를 갖고 있는 인쇄 회로 기판, 기판상의 회로와 접속된 회로 기판상에 상승된 접속 패드, 및 절연 기부상의 회로 부분이 인쇄 회로 기판에 걸쳐 연장하여 인쇄회로 기판상의 회로와 접속하도록 인쇄 회로 기판내의 소정의 개구내에 배치된 절연 기부상의 회로에 접속된 반도체 장치를 포함하는 것을 특징으로 하는 반도체 팩케이지.
  2. 제1항에 있어서, 인쇄 회로 기판내의 개구내에 수동 전자 부품을 포함하고, 인쇄 회로 기판상의 회로와 접속되는 것을 특징으로 하는 반도체 팩케이지.
  3. 제1항에 있어서, 다수의 회로 기판이 모듈을 형성하도록 적층되고, 상기 상승된 접촉 패드에 의해 전기적으로 상호 접속되는 것을 특징으로 하는 반도체 팩케이지.
  4. 제1항에 있어서, 반도체 장치가 갖고 있는 개구내에 방열판을 포함하는 것을 특징으로 하는 반도체 팩케이지.
  5. 제3항에 있어서, 적층형 기판들사이에 절연 물질을 포함하는 것을 특징으로 하는 반도체 팩케이지.
  6. 제1항에 있어서, 반도체가 절연 기부 및 이의 접속부를 절단함으로써 장착한후에 인쇄 회로 기판으로 부터 제거되는 것을 특징으로 하는 반도체 팩케이지.
  7. 다수의 반도체 장치가 연속 가요성 기부 물질상의 개구내에 장착되는데, 개구내에 장착된 각각의 반도체 장치용의 반복성 도체 패턴을 갖고 있고, 연속 기부 물질의 전장을 따라 연장하는 2개의 도체를 갖고 있는 반도체 팩케이지에 있어서, 도체 패턴내의 각각의 도체상에 형성된 검사 패드, 개구에 걸쳐 연장하고, 개구내에 장착된 반도체 장치에 접속된 도체 패턴내의 각각의 도체, 전력 접속부를 각각의 반도체 장치에 제공하는 연속 기부 물질의 전장을 따라 연장하는 2개의 도체들 중 한 도체, 접지 접속부를 반도체 장치에 제공하는 2개의 도체들중 다른 도체, 및 전력 접속부와 각각의 반도체 장치사이의 휴우즈 링크를 포함하는 것을 특징으로 하는 반도체 팩케이지.
  8. 제7항에 있어서, 접지 접속부와 반도체 장치사이의 휴우즈 링크를 포함하는 것을 특징으로 하는 반도체 팩케이지.
  9. 제7항에 있어서, 도체 패턴내의 상기 도체상에 접속 패드가 형성되는 것을 특징으로 하는 반도체 팩케이지.
  10. 제7항에 있어서, 접속 패드 및 검사 지점이 도체 패턴상에 형성되고, 기부 물질상의 반도체 장치 및 접속부 부분이 접속 패드와 검사 지점사이를 절단함으로써 제거되는 것을 특징으로 하는 반도체 팩케이지.
  11. 다수의 적층형 회로 기판, 각각의 회로 기판상에 상호 접속되고, 요구된 기능의 전자 시스템을 형성하기 위해 모듈내의 다른 회로 기판에 상호 접속된 다수의 반도체 장치 및 회로 구성 부품을 포함하는 회로 모듈에 있어서, 최소한 한 표면상에 도전성 회로를 갖고 있고, 소정의 개구에 걸쳐 연장하는 최소한의 회로 부분을 갖고 있는 각각의 기판을 관통하는 다수의 개구를 각각 갖고 있는 다수의 회로 기판, 개구내의 반도체 장치 및/또는 전자 구성 부품이 개구의 외부로는 연장되지 않고, 개구에 걸쳐 연장하는 회로에 접속되도록 회로 기판내의 개구내에 모두 장착된 다수의 반도체 장치 및/또는 전자 구성 부품, 및 회로 기판들이 모듈을 형성하기 위해 적층되는 경우, 접촉 패드가 회로 기판을 상호 접속시키기 위해 서로 전기적으로 접속하도록 회로 기판상의 요구된 위치에 형성된 접속 패드를 포함하는 것을 특징으로 하는 회로 모듈.
  12. 제11항에 있어서, 반도체 장치내에 갖고 있는, 최소한 소정의 개구내에 배치된 방열판을 포함하는 것을 특징으로 하는 회로 모듈.
  13. 제11항에 있어서, 인접 기판으로 부터 한 기판상의 회로를 절연시키기 위해 회로 기판들사이의 절연 물질의 박막층을 포함하는 것을 특징으로 하는 회로 모듈.
  14. 제11항에 있어서, 접촉 패드가 인접 회로 기판들사이의 회로를 공기 절연시키기 위해 회로 기판에서 떨어져 보유되는 것을 특징으로 하는 회로 모듈.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900012532A 1989-08-15 1990-08-14 직접 장착 반도체 팩케이지 KR910005443A (ko)

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US6097200A (en) * 1996-10-07 2000-08-01 Aetrium Incorporated Modular, semiconductor reliability test system
JP2002009236A (ja) 2000-06-21 2002-01-11 Shinko Electric Ind Co Ltd 多層半導体装置及びその製造方法
CN102177582B (zh) * 2008-08-07 2014-07-09 意法半导体股份有限公司 用于在测试集成在半导体晶片上的多个电子器件期间并行供应电力的电路
JP4864126B2 (ja) * 2009-08-26 2012-02-01 ルネサスエレクトロニクス株式会社 Ｔｃｐ型半導体装置
EP2290686A3 (en) 2009-08-28 2011-04-20 STMicroelectronics S.r.l. Method to perform electrical testing and assembly of electronic devices

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US3544857A (en) * 1966-08-16 1970-12-01 Signetics Corp Integrated circuit assembly with lead structure and method
JPS5750069B2 (ko) * 1974-08-27 1982-10-25
JPS5419656A (en) * 1977-07-15 1979-02-14 Hitachi Ltd Bonding tool
US4750092A (en) * 1985-11-20 1988-06-07 Kollmorgen Technologies Corporation Interconnection package suitable for electronic devices and methods for producing same

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