KR970061017A - 도체층부착이방성도전시트 및 이를 사용한 배선기판 - Google Patents
도체층부착이방성도전시트 및 이를 사용한 배선기판 Download PDFInfo
- Publication number
- KR970061017A KR970061017A KR1019970000992A KR19970000992A KR970061017A KR 970061017 A KR970061017 A KR 970061017A KR 1019970000992 A KR1019970000992 A KR 1019970000992A KR 19970000992 A KR19970000992 A KR 19970000992A KR 970061017 A KR970061017 A KR 970061017A
- Authority
- KR
- South Korea
- Prior art keywords
- anisotropic conductive
- conductive sheet
- wiring
- wiring board
- electrically connected
- Prior art date
Links
- 239000004020 conductor Substances 0.000 title claims 3
- 239000000758 substrate Substances 0.000 claims 4
- 239000002184 metal Substances 0.000 claims 2
- 239000011231 conductive filler Substances 0.000 claims 1
- 238000010292 electrical insulation Methods 0.000 claims 1
- 239000011888 foil Substances 0.000 claims 1
- 239000000843 powder Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
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- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract
상하의 배선패턴 사이의 전기적 접속이 용이하고, 용이하게 제조할 수 있고, 또 두께도 얇게 할 수 있는 배선기관을 제공한다. 해결수단은 한쪽 면에 배선패턴(62)이 형성된 이방성도전시트(52)를 복수매적층으로하여 고착되고, 또 최하층의 이방성도전시트(52)의 다른쪽 면에서, 표면에 배선패턴(60)이 형성된 프린트배선기관(58)면에 고착되고, 상기 배선패텬(60, 62) 사이가 상기 이방성도전시트(52)를 거쳐서 전기적으로 접속되어 있고, 최상층의 아방성도전시트(52)의 배선패턴(62)의 외부접속부(62a)를 노출하여 전기적으로 절연피막(64)이 형성되어 있는 것을 특징으로 한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 실시예를 나타낸 단면도.
제2도는 제1도의 부분확대도.
제14도는 배선기판의 다른 예를 나타낸 단면설명도.
제15도는 이방성도전시트를 다층으로 형성한 배선기판의 단면설명도.
제16도는 외부접속단자의 구조를 나타낸 단면.
Claims (9)
- 수지중에 금속분등의 도전필러가 배합된 이방성도전시트의 표면에 도체층이 형성되어 있는것을 특징으로 하는 도체부착이방성도전시트.
- 제1항에 있어서, 도체층이 금속박인 것이 특징인 도체부착이방성도전시트.
- 도면에 배선패턴이 형성된 기판면에, 한쪽 면에 배선패턴이 형성된 이방성도전시트의 다른쪽 면이 고착되고, 이 배선패턴이 형성된 이방성도전시트를 거쳐서 전기적으로 접속되어 있고, 상기 이방성도전시트에 형성된 배선패턴의 외부접속부를 노출하여 전기적절연피막이 형성되어 있는 것을 특징으로 하는 배선기관.
- 제3항에 있어서, 상기 이방성도전시트에 형성된 배선패턴에 의해 상기 아방성도전시트가 압압됨으로서 전기적으로 접속되어 있는 것을 특징으로 하는 배선기판.
- 제3항에 있어서, 상기 기판에 형성된 배선패턴에 범프가 형성되고, 이 범프에 의해 상기 아방성도전시트가 압압됨으로서 전기적으로 접속되어 있는 것을 특징으로 하는 배선기판.
- 한쪽 면에 배선패턴이 형성된 이방성도전시트가 복수매적층되어 고착되고, 또 최하층의 이방성도전시트의 다른쪽 면이 표면에 배선패턴이 형성된 기판면에 고착된고, 상기 배선패턴 사이가 상기 이방성도전시트를 거쳐서 전기적으로 접속되어 있고, 최상층의 이방성도전시트에 형성된 배선패턴의 외부접속부를 노출하여 전기적절연피막이 형성되어 있는 것을 특징으로 하는 배선기판.
- 제6항에 있어서, 상기 이방성도전시트에 형성된 배선패턴에 의해 상기 이방성도전시트가 압압됨으로서 전기적으로 접속되어 있는 것을 특징으로 하는 배선기판.
- 제6항에 있어서, 상기 기판에 형성된 배선패턴 및 내층이 되는 이방성도전시트에 형성된 배선패턴에 범프가 형성되고, 이 범프에 의해 상기 이방성도전시트가 압압됨으로서 전기적으로 접속되어 있는 것을 특징으로 하는 배선기판.
- 제6항에 내지 제8항중 어느 한항에 있어서, 상기 배선패텬중 어느 하나의 전원용 또는 접지용 베타패턴으로 형성되어 있는 것을 특징으로 하는 배선기판.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
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Application Number | Priority Date | Filing Date | Title |
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JP00761396A JP3549316B2 (ja) | 1995-03-24 | 1996-01-19 | 配線基板 |
JP96-007613 | 1996-01-19 | ||
JP007613 | 1996-01-19 |
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KR970061017A true KR970061017A (ko) | 1997-08-12 |
KR100274333B1 KR100274333B1 (ko) | 2001-01-15 |
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KR1019970000992A KR100274333B1 (ko) | 1996-01-19 | 1997-01-15 | 도체층부착 이방성 도전시트 및 이를 사용한 배선기판 |
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US (2) | US5886415A (ko) |
EP (1) | EP0786808B1 (ko) |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2002015259A1 (en) * | 2000-08-02 | 2002-02-21 | Korea Advanced Institute Of Science And Technology | High reliability non-conductive adhesives for non-solder flip chip bondings and flip chip bonding method using the same |
KR100347135B1 (ko) * | 1999-12-24 | 2002-07-31 | 주식회사 하이닉스반도체 | 웨이퍼 레벨의 멀티칩 패키지 및 그 제조방법 |
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US6111317A (en) * | 1996-01-18 | 2000-08-29 | Kabushiki Kaisha Toshiba | Flip-chip connection type semiconductor integrated circuit device |
KR100274333B1 (ko) * | 1996-01-19 | 2001-01-15 | 모기 쥰이찌 | 도체층부착 이방성 도전시트 및 이를 사용한 배선기판 |
US6034437A (en) * | 1997-06-06 | 2000-03-07 | Rohm Co., Ltd. | Semiconductor device having a matrix of bonding pads |
KR100357757B1 (ko) | 1997-11-21 | 2003-01-24 | 로무 가부시키가이샤 | 반도체장치및그제조방법 |
US6137063A (en) * | 1998-02-27 | 2000-10-24 | Micron Technology, Inc. | Electrical interconnections |
JP2000022039A (ja) * | 1998-07-06 | 2000-01-21 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6489183B1 (en) * | 1998-07-17 | 2002-12-03 | Micron Technology, Inc. | Method of manufacturing a taped semiconductor device |
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- 1997-01-17 US US08/786,615 patent/US5886415A/en not_active Expired - Lifetime
- 1997-01-17 EP EP97300275A patent/EP0786808B1/en not_active Expired - Lifetime
- 1997-01-17 DE DE69711735T patent/DE69711735T2/de not_active Expired - Lifetime
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1998
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KR100347135B1 (ko) * | 1999-12-24 | 2002-07-31 | 주식회사 하이닉스반도체 | 웨이퍼 레벨의 멀티칩 패키지 및 그 제조방법 |
WO2002015259A1 (en) * | 2000-08-02 | 2002-02-21 | Korea Advanced Institute Of Science And Technology | High reliability non-conductive adhesives for non-solder flip chip bondings and flip chip bonding method using the same |
US6930399B2 (en) | 2000-08-02 | 2005-08-16 | Korea Advanced Institute Of Science And Technology | High reliability non-conductive adhesives for non-solder flip chip bondings and flip chip bonding method using the same |
Also Published As
Publication number | Publication date |
---|---|
DE69711735D1 (de) | 2002-05-16 |
EP0786808A1 (en) | 1997-07-30 |
DE69711735T2 (de) | 2002-11-21 |
US5886415A (en) | 1999-03-23 |
KR100274333B1 (ko) | 2001-01-15 |
US6121688A (en) | 2000-09-19 |
EP0786808B1 (en) | 2002-04-10 |
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