KR940008109A - 반도체집적회로장치 - Google Patents

반도체집적회로장치 Download PDF

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Publication number
KR940008109A
KR940008109A KR1019930016669A KR930016669A KR940008109A KR 940008109 A KR940008109 A KR 940008109A KR 1019930016669 A KR1019930016669 A KR 1019930016669A KR 930016669 A KR930016669 A KR 930016669A KR 940008109 A KR940008109 A KR 940008109A
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KR
South Korea
Prior art keywords
reference potential
layer
circuit device
potential layer
integrated circuit
Prior art date
Application number
KR1019930016669A
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English (en)
Inventor
간지 오쯔까
다까유끼 오끼나가
유지 시라이
다까시 미와
도시히로 쯔보이
죠지 마쯔가미
Original Assignee
가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
스즈끼 진이찌로
히다찌초엘에스아이엔지니어링 가부시끼가이샤
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Application filed by 가나이 쯔또무, 가부시끼가이샤 히다찌세이사꾸쇼, 스즈끼 진이찌로, 히다찌초엘에스아이엔지니어링 가부시끼가이샤 filed Critical 가나이 쯔또무
Publication of KR940008109A publication Critical patent/KR940008109A/ko

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    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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Abstract

반도체집적회로장치에 관한 것으로써, 여러개의 신호선의 동시전환에 대해서 접지선 Vss의 전위의 요동을 저감하고, 동작속의 고속화를 도모하기 위해, 여려개의 신호선(109), 전원공급선(110) 및 접지선(107)을 갖고,여러개의 신호선(109)는 쌍방향 전류로로 되는 회로 구성으로 되어 있는 반도체집적회로장치에 있어서, 각 신호선(109)가 전원공급선(110)과 접지선(107)사이에 마련되고, 각각을 적층구조로 구성한다.
이러한 장치를 이용하는 것에 의해 여러개의 신호선의 동시전환에 대해서 접지의 전위의 요동의 저감화, 동작속도의 고속화 및 접지의 리이드의 갯수를 저감할 수 있다.

Description

반도체집적회로장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본발명의 기본구성을 설명하기 위한 단면도.
제5도는 제4도의 동가회로도.
제6도는 본발명의 실시에 1인 QFP구조를 채용하는 수지봉지형 반도체장치의 구성을 도시한 일부 절단 평면도.
제7도는 제6도의 측면도.
제8도는 제6도에 도시한 X-X절단선으로 자른 단면도.
제9도는 제8도에 도시한 반도체칩과 패케이지내 전송로의 접속부의 구성을 설명하기 위한 확대사시도.
제16도는 본 발명의 실시에 4인 주요부 구성을 설명하기 위한 단면도.

Claims (12)

  1. 그 주표면에 여러개의 제1, 제2및 제3의 본딩패드를 갖는 반도체펠릿, 상기 반도체펠릿의 주표면과 평행한 제1의 면에는 상기 반도체 펠릿에 기준전위를 공급하는 역할을 하고 있는 제1의 기준전위층이 형성되고, 상기제1의 면과 대항하고 상기 반도체펠릿의 주표면과 평행한 제2의 면에는 제2의 기준전위층이 형성되어 있는 절연성의 다층기관, 상기 다층기관의 내부층으로써 상기 제1의 기준전위층과 상기 제2의 기준전위층사이에 마련되며,또한 상기 제1 및 제2의 기준전위층과 일정한 간격을 갖도록 배치되어 있고, 쌍방향 전류로로 되는 회로 구성으로되어 있는 여러개의 신호배선층, 상기 제1의 본딩패드와 상기 제1의 기준전위층사이, 상가 제2의 본딩패드와 상기 신호배선층사이 및 상기 제3의 본딩패드와 상기 제2의 기준전위층사이를 각각 전기적으로 접속하는 와이어,상기 제1의 기준전위층, 상기 제2의 기준전위층 및 상기 신호 배선층의 각각에 전기적으로 접속된 여러개의 외부인출용 리이드 및 상기 반도체펠릿, 상기 다층기판 및 상기 와이어를 그안에 봉하고 있는 수지봉지체를 포함하는 반도체집적회로장치.
  2. 제1항에 있어서, 상기 제1 및 제2의 기준전위층의 선폭은 상기 신호배선층의 선폭과 같던가 그이상인 반도체집적회로장치.
  3. 제1항에 있어서, 상기 제1의 기준전위층은 전원전위배선층인 반도체집적회로장치.
  4. 제1항에 있어서, 상기 제2의 기준전위층은 접지전위배선층인 반도체집적회로장치.
  5. 제1항에 있어서, 상기 제1의 기준전위층은 1개의 평면으로 이루어지는 반도체집격회로장치.
  6. 제1항에 있어서, 상기 제2의 기준전위층은 1개의 평면으로 이루어지는 반도체칩적회로장치.
  7. 그 주표면에 여러개의 제1, 제2 및 제3의 본딩패드를 갖는 반도체펠릿, 상기 반도체펠릿을 지지하기 위한 베이스기판, 상기 반도체펠릿의 주표면과 평행한 제1의 면에는 상기 반도체 펠릿에 기준전위를 공급하는 역할을 하고 있는 제1의 기준전위층이 형성되고, 상기 제1의 면과 대항하는 제2의 면 및 상기 제1의 면과 상기 제2의면사이로 연장하는 측면에는 제2의 기준전위층이 형성되어 있고, 상기 베이스기판에 부착되어 있는 절연성의 다층 기판, 상기 다층기판의 내부층으로써 상기 제1의 기준전위와 상기 제2의 기준전위층 사이에 마련되며, 또한 상기 제1 및 제2의 기준전위층과 일정한 간격을 갖도록 배치되어 있고, 쌍방향전류로로 되는 회로구성으로 되어있는 여러개의 신호배선층, 상기 제1의 본딩패드와 상기 제1의 기준전위층사이, 상기 제2의 본딩패드와 상기 신호배선층사이 및 상기 제3의 본딩패드와 상기 제2의 기준전위층사이를 각각 전기적으로 접속하는 와이어, 상기제1의 기준전위층, 상기 제2의 기준전위층 및 상기 신호 배선층이 각각에 전기적으로 접속된 여러개의 외부인출용 리이드 및 상기 반도체펠릿, 상기 다층기판 및 상기 와이어를 그 안에 봉하고 있는 수지봉지체를 포함하는 반도체집적회로장치.
  8. 제7항에 있어서, 상기 제1 및 제2의 기준전위층의 선폭은 상기 신호배선층의 선폭과 같던가 그 이상인 반도체집적회로장치.
  9. 제7항에 있어서, 상기 제1의 기준전위층은 전원전위배선층인 반도체집적회로장치.
  10. 제7항에 있어서, 상기 제2의 기준전위층은 접지전위배선층인 반도체집적회로장치.
  11. 제7항에 있어서, 상기 제1의 기준전위층은 1개의 평면으로 이루어지는 반도체칩적회로장치.
  12. 제7항에 있어서, 상기 제2의 기준전위층은 2개의 평면으로 이루어지는 반도체집적회로 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930016669A 1992-09-07 1993-08-26 반도체집적회로장치 KR940008109A (ko)

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